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-rw-r--r--arch/sparc64/mm/init.c11
-rw-r--r--arch/sparc64/mm/ultra.S2
2 files changed, 11 insertions, 2 deletions
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index 4e821b3ecb03..217de3ea29e8 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -49,6 +49,7 @@
49#include <asm/sstate.h> 49#include <asm/sstate.h>
50#include <asm/mdesc.h> 50#include <asm/mdesc.h>
51#include <asm/cpudata.h> 51#include <asm/cpudata.h>
52#include <asm/irq.h>
52 53
53#define MAX_PHYS_ADDRESS (1UL << 42UL) 54#define MAX_PHYS_ADDRESS (1UL << 42UL)
54#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL) 55#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
@@ -1771,6 +1772,16 @@ void __init paging_init(void)
1771 if (tlb_type == hypervisor) 1772 if (tlb_type == hypervisor)
1772 sun4v_mdesc_init(); 1773 sun4v_mdesc_init();
1773 1774
1775 /* Once the OF device tree and MDESC have been setup, we know
1776 * the list of possible cpus. Therefore we can allocate the
1777 * IRQ stacks.
1778 */
1779 for_each_possible_cpu(i) {
1780 /* XXX Use node local allocations... XXX */
1781 softirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1782 hardirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1783 }
1784
1774 /* Setup bootmem... */ 1785 /* Setup bootmem... */
1775 last_valid_pfn = end_pfn = bootmem_init(phys_base); 1786 last_valid_pfn = end_pfn = bootmem_init(phys_base);
1776 1787
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
index ff1dc44d363e..86773e89dc1b 100644
--- a/arch/sparc64/mm/ultra.S
+++ b/arch/sparc64/mm/ultra.S
@@ -480,7 +480,6 @@ xcall_sync_tick:
480 b rtrap_xcall 480 b rtrap_xcall
481 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 481 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
482 482
483#ifdef CONFIG_MAGIC_SYSRQ
484 .globl xcall_fetch_glob_regs 483 .globl xcall_fetch_glob_regs
485xcall_fetch_glob_regs: 484xcall_fetch_glob_regs:
486 sethi %hi(global_reg_snapshot), %g1 485 sethi %hi(global_reg_snapshot), %g1
@@ -511,7 +510,6 @@ xcall_fetch_glob_regs:
511 membar #StoreStore 510 membar #StoreStore
512 stx %g3, [%g1 + GR_SNAP_THREAD] 511 stx %g3, [%g1 + GR_SNAP_THREAD]
513 retry 512 retry
514#endif /* CONFIG_MAGIC_SYSRQ */
515 513
516#ifdef DCACHE_ALIASING_POSSIBLE 514#ifdef DCACHE_ALIASING_POSSIBLE
517 .align 32 515 .align 32