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-rw-r--r--arch/sparc64/mm/ultra.S31
1 files changed, 29 insertions, 2 deletions
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
index 796e005dad8b..9bb2d90a9df6 100644
--- a/arch/sparc64/mm/ultra.S
+++ b/arch/sparc64/mm/ultra.S
@@ -1,7 +1,7 @@
1/* $Id: ultra.S,v 1.72 2002/02/09 19:49:31 davem Exp $ 1/*
2 * ultra.S: Don't expand these all over the place... 2 * ultra.S: Don't expand these all over the place...
3 * 3 *
4 * Copyright (C) 1997, 2000 David S. Miller (davem@redhat.com) 4 * Copyright (C) 1997, 2000, 2008 David S. Miller (davem@davemloft.net)
5 */ 5 */
6 6
7#include <asm/asi.h> 7#include <asm/asi.h>
@@ -15,6 +15,7 @@
15#include <asm/thread_info.h> 15#include <asm/thread_info.h>
16#include <asm/cacheflush.h> 16#include <asm/cacheflush.h>
17#include <asm/hypervisor.h> 17#include <asm/hypervisor.h>
18#include <asm/cpudata.h>
18 19
19 /* Basically, most of the Spitfire vs. Cheetah madness 20 /* Basically, most of the Spitfire vs. Cheetah madness
20 * has to do with the fact that Cheetah does not support 21 * has to do with the fact that Cheetah does not support
@@ -514,6 +515,32 @@ xcall_report_regs:
514 b rtrap_xcall 515 b rtrap_xcall
515 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 516 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
516 517
518#ifdef CONFIG_MAGIC_SYSRQ
519 .globl xcall_fetch_glob_regs
520xcall_fetch_glob_regs:
521 sethi %hi(global_reg_snapshot), %g1
522 or %g1, %lo(global_reg_snapshot), %g1
523 __GET_CPUID(%g2)
524 sllx %g2, 6, %g3
525 add %g1, %g3, %g1
526 rdpr %tstate, %g7
527 stx %g7, [%g1 + GR_SNAP_TSTATE]
528 rdpr %tpc, %g7
529 stx %g7, [%g1 + GR_SNAP_TPC]
530 rdpr %tnpc, %g7
531 stx %g7, [%g1 + GR_SNAP_TNPC]
532 stx %o7, [%g1 + GR_SNAP_O7]
533 stx %i7, [%g1 + GR_SNAP_I7]
534 sethi %hi(trap_block), %g7
535 or %g7, %lo(trap_block), %g7
536 sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2
537 add %g7, %g2, %g7
538 ldx [%g7 + TRAP_PER_CPU_THREAD], %g3
539 membar #StoreStore
540 stx %g3, [%g1 + GR_SNAP_THREAD]
541 retry
542#endif /* CONFIG_MAGIC_SYSRQ */
543
517#ifdef DCACHE_ALIASING_POSSIBLE 544#ifdef DCACHE_ALIASING_POSSIBLE
518 .align 32 545 .align 32
519 .globl xcall_flush_dcache_page_cheetah 546 .globl xcall_flush_dcache_page_cheetah