2 files changed, 1 insertions, 74 deletions
diff --git a/arch/sparc64/lib/Makefile b/arch/sparc64/lib/Makefile
index 6201f1040982..40dbeec7e5d6 100644
--- a/arch/sparc64/lib/Makefile
+++ b/arch/sparc64/lib/Makefile
@@ -12,7 +12,7 @@ lib-y := PeeCeeI.o copy_page.o clear_page.o strlen.o strncmp.o \
         U1memcpy.o U1copy_from_user.o U1copy_to_user.o \
         U3memcpy.o U3copy_from_user.o U3copy_to_user.o U3patch.o \
         copy_in_user.o user_fixup.o memmove.o \
-         mcount.o ipcsum.o rwsem.o xor.o find_bit.o delay.o mb.o
+         mcount.o ipcsum.o rwsem.o xor.o find_bit.o delay.o
 lib-$(CONFIG_DEBUG_SPINLOCK) += debuglocks.o
 lib-$(CONFIG_HAVE_DEC_LOCK) += dec_and_lock.o
diff --git a/arch/sparc64/lib/mb.S b/arch/sparc64/lib/mb.S
deleted file mode 100644
index 4004f748619f..000000000000
--- a/arch/sparc64/lib/mb.S
+++ /dev/null
@@ -1,73 +0,0 @@
-/* mb.S: Out of line memory barriers.
- *
- * Copyright (C) 2005 David S. Miller (davem@davemloft.net)
- */
-        /* These are here in an effort to more fully work around
-         * Spitfire Errata #51.  Essentially, if a memory barrier
-         * occurs soon after a mispredicted branch, the chip can stop
-         * executing instructions until a trap occurs.  Therefore, if
-         * interrupts are disabled, the chip can hang forever.
-         *
-         * It used to be believed that the memory barrier had to be
-         * right in the delay slot, but a case has been traced
-         * recently wherein the memory barrier was one instruction
-         * after the branch delay slot and the chip still hung.  The
-         * offending sequence was the following in sym_wakeup_done()
-         * of the sym53c8xx_2 driver:
-         *
-         *      call    sym_ccb_from_dsa, 0
-         *       movge  %icc, 0, %l0
-         *      brz,pn  %o0, .LL1303
-         *       mov    %o0, %l2
-         *      membar  #LoadLoad
-         *
-         * The branch has to be mispredicted for the bug to occur.
-         * Therefore, we put the memory barrier explicitly into a
-         * "branch always, predicted taken" delay slot to avoid the
-         * problem case.
-         */
-        .text
-99:     retl
-         nop
-        .globl  mb
-mb:     ba,pt   %xcc, 99b
-         membar #LoadLoad | #LoadStore | #StoreStore | #StoreLoad
-        .size   mb, .-mb
-        .globl  rmb
-rmb:    ba,pt   %xcc, 99b
-         membar #LoadLoad
-        .size   rmb, .-rmb
-        .globl  wmb
-wmb:    ba,pt   %xcc, 99b
-         membar #StoreStore
-        .size   wmb, .-wmb
-        .globl  membar_storeload
-membar_storeload:
-        ba,pt   %xcc, 99b
-         membar #StoreLoad
-        .size   membar_storeload, .-membar_storeload
-        .globl  membar_storeload_storestore
-membar_storeload_storestore:
-        ba,pt   %xcc, 99b
-         membar #StoreLoad | #StoreStore
-        .size   membar_storeload_storestore, .-membar_storeload_storestore
-        .globl  membar_storeload_loadload
-membar_storeload_loadload:
-        ba,pt   %xcc, 99b
-         membar #StoreLoad | #LoadLoad
-        .size   membar_storeload_loadload, .-membar_storeload_loadload
-        .globl  membar_storestore_loadstore
-membar_storestore_loadstore:
-        ba,pt   %xcc, 99b
-         membar #StoreStore | #LoadStore
-        .size   membar_storestore_loadstore, .-membar_storestore_loadstore

diff --git a/arch/sparc64/lib/Makefile b/arch/sparc64/lib/Makefile index 6201f1040982..40dbeec7e5d6 100644 --- a/arch/sparc64/lib/Makefile +++ b/arch/sparc64/lib/Makefile
@@ -12,7 +12,7 @@ lib-y := PeeCeeI.o copy_page.o clear_page.o strlen.o strncmp.o \
12	U1memcpy.o U1copy_from_user.o U1copy_to_user.o \	12	U1memcpy.o U1copy_from_user.o U1copy_to_user.o \
13	U3memcpy.o U3copy_from_user.o U3copy_to_user.o U3patch.o \	13	U3memcpy.o U3copy_from_user.o U3copy_to_user.o U3patch.o \
14	copy_in_user.o user_fixup.o memmove.o \	14	copy_in_user.o user_fixup.o memmove.o \
15	mcount.o ipcsum.o rwsem.o xor.o find_bit.o delay.o mb.o	15	mcount.o ipcsum.o rwsem.o xor.o find_bit.o delay.o
16		16
17	lib-$(CONFIG_DEBUG_SPINLOCK) += debuglocks.o	17	lib-$(CONFIG_DEBUG_SPINLOCK) += debuglocks.o
18	lib-$(CONFIG_HAVE_DEC_LOCK) += dec_and_lock.o	18	lib-$(CONFIG_HAVE_DEC_LOCK) += dec_and_lock.o


diff --git a/arch/sparc64/lib/mb.S b/arch/sparc64/lib/mb.S deleted file mode 100644 index 4004f748619f..000000000000 --- a/arch/sparc64/lib/mb.S +++ /dev/null
@@ -1,73 +0,0 @@
1	/* mb.S: Out of line memory barriers.
2	*
3	* Copyright (C) 2005 David S. Miller (davem@davemloft.net)
4	*/
5
6	/* These are here in an effort to more fully work around
7	* Spitfire Errata #51. Essentially, if a memory barrier
8	* occurs soon after a mispredicted branch, the chip can stop
9	* executing instructions until a trap occurs. Therefore, if
10	* interrupts are disabled, the chip can hang forever.
11	*
12	* It used to be believed that the memory barrier had to be
13	* right in the delay slot, but a case has been traced
14	* recently wherein the memory barrier was one instruction
15	* after the branch delay slot and the chip still hung. The
16	* offending sequence was the following in sym_wakeup_done()
17	* of the sym53c8xx_2 driver:
18	*
19	* call sym_ccb_from_dsa, 0
20	* movge %icc, 0, %l0
21	* brz,pn %o0, .LL1303
22	* mov %o0, %l2
23	* membar #LoadLoad
24	*
25	* The branch has to be mispredicted for the bug to occur.
26	* Therefore, we put the memory barrier explicitly into a
27	* "branch always, predicted taken" delay slot to avoid the
28	* problem case.
29	*/
30
31	.text
32
33	99: retl
34	nop
35
36	.globl mb
37	mb: ba,pt %xcc, 99b
38	membar #LoadLoad \| #LoadStore \| #StoreStore \| #StoreLoad
39	.size mb, .-mb
40
41	.globl rmb
42	rmb: ba,pt %xcc, 99b
43	membar #LoadLoad
44	.size rmb, .-rmb
45
46	.globl wmb
47	wmb: ba,pt %xcc, 99b
48	membar #StoreStore
49	.size wmb, .-wmb
50
51	.globl membar_storeload
52	membar_storeload:
53	ba,pt %xcc, 99b
54	membar #StoreLoad
55	.size membar_storeload, .-membar_storeload
56
57	.globl membar_storeload_storestore
58	membar_storeload_storestore:
59	ba,pt %xcc, 99b
60	membar #StoreLoad \| #StoreStore
61	.size membar_storeload_storestore, .-membar_storeload_storestore
62
63	.globl membar_storeload_loadload
64	membar_storeload_loadload:
65	ba,pt %xcc, 99b
66	membar #StoreLoad \| #LoadLoad
67	.size membar_storeload_loadload, .-membar_storeload_loadload
68
69	.globl membar_storestore_loadstore
70	membar_storestore_loadstore:
71	ba,pt %xcc, 99b
72	membar #StoreStore \| #LoadStore
73	.size membar_storestore_loadstore, .-membar_storestore_loadstore