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-rw-r--r--arch/sparc64/lib/atomic.S26
1 files changed, 0 insertions, 26 deletions
diff --git a/arch/sparc64/lib/atomic.S b/arch/sparc64/lib/atomic.S
index 70ac4186f62b..0268210ca168 100644
--- a/arch/sparc64/lib/atomic.S
+++ b/arch/sparc64/lib/atomic.S
@@ -43,29 +43,10 @@ atomic_sub: /* %o0 = decrement, %o1 = atomic_ptr */
432: BACKOFF_SPIN(%o2, %o3, 1b) 432: BACKOFF_SPIN(%o2, %o3, 1b)
44 .size atomic_sub, .-atomic_sub 44 .size atomic_sub, .-atomic_sub
45 45
46 /* On SMP we need to use memory barriers to ensure
47 * correct memory operation ordering, nop these out
48 * for uniprocessor.
49 */
50#ifdef CONFIG_SMP
51
52#define ATOMIC_PRE_BARRIER membar #StoreLoad | #LoadLoad;
53#define ATOMIC_POST_BARRIER \
54 ba,pt %xcc, 80b; \
55 membar #StoreLoad | #StoreStore
56
5780: retl
58 nop
59#else
60#define ATOMIC_PRE_BARRIER
61#define ATOMIC_POST_BARRIER
62#endif
63
64 .globl atomic_add_ret 46 .globl atomic_add_ret
65 .type atomic_add_ret,#function 47 .type atomic_add_ret,#function
66atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ 48atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
67 BACKOFF_SETUP(%o2) 49 BACKOFF_SETUP(%o2)
68 ATOMIC_PRE_BARRIER
691: lduw [%o1], %g1 501: lduw [%o1], %g1
70 add %g1, %o0, %g7 51 add %g1, %o0, %g7
71 cas [%o1], %g1, %g7 52 cas [%o1], %g1, %g7
@@ -73,7 +54,6 @@ atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
73 bne,pn %icc, 2f 54 bne,pn %icc, 2f
74 add %g7, %o0, %g7 55 add %g7, %o0, %g7
75 sra %g7, 0, %o0 56 sra %g7, 0, %o0
76 ATOMIC_POST_BARRIER
77 retl 57 retl
78 nop 58 nop
792: BACKOFF_SPIN(%o2, %o3, 1b) 592: BACKOFF_SPIN(%o2, %o3, 1b)
@@ -83,7 +63,6 @@ atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
83 .type atomic_sub_ret,#function 63 .type atomic_sub_ret,#function
84atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */ 64atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
85 BACKOFF_SETUP(%o2) 65 BACKOFF_SETUP(%o2)
86 ATOMIC_PRE_BARRIER
871: lduw [%o1], %g1 661: lduw [%o1], %g1
88 sub %g1, %o0, %g7 67 sub %g1, %o0, %g7
89 cas [%o1], %g1, %g7 68 cas [%o1], %g1, %g7
@@ -91,7 +70,6 @@ atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
91 bne,pn %icc, 2f 70 bne,pn %icc, 2f
92 sub %g7, %o0, %g7 71 sub %g7, %o0, %g7
93 sra %g7, 0, %o0 72 sra %g7, 0, %o0
94 ATOMIC_POST_BARRIER
95 retl 73 retl
96 nop 74 nop
972: BACKOFF_SPIN(%o2, %o3, 1b) 752: BACKOFF_SPIN(%o2, %o3, 1b)
@@ -131,7 +109,6 @@ atomic64_sub: /* %o0 = decrement, %o1 = atomic_ptr */
131 .type atomic64_add_ret,#function 109 .type atomic64_add_ret,#function
132atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ 110atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
133 BACKOFF_SETUP(%o2) 111 BACKOFF_SETUP(%o2)
134 ATOMIC_PRE_BARRIER
1351: ldx [%o1], %g1 1121: ldx [%o1], %g1
136 add %g1, %o0, %g7 113 add %g1, %o0, %g7
137 casx [%o1], %g1, %g7 114 casx [%o1], %g1, %g7
@@ -139,7 +116,6 @@ atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
139 bne,pn %xcc, 2f 116 bne,pn %xcc, 2f
140 add %g7, %o0, %g7 117 add %g7, %o0, %g7
141 mov %g7, %o0 118 mov %g7, %o0
142 ATOMIC_POST_BARRIER
143 retl 119 retl
144 nop 120 nop
1452: BACKOFF_SPIN(%o2, %o3, 1b) 1212: BACKOFF_SPIN(%o2, %o3, 1b)
@@ -149,7 +125,6 @@ atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
149 .type atomic64_sub_ret,#function 125 .type atomic64_sub_ret,#function
150atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */ 126atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
151 BACKOFF_SETUP(%o2) 127 BACKOFF_SETUP(%o2)
152 ATOMIC_PRE_BARRIER
1531: ldx [%o1], %g1 1281: ldx [%o1], %g1
154 sub %g1, %o0, %g7 129 sub %g1, %o0, %g7
155 casx [%o1], %g1, %g7 130 casx [%o1], %g1, %g7
@@ -157,7 +132,6 @@ atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
157 bne,pn %xcc, 2f 132 bne,pn %xcc, 2f
158 sub %g7, %o0, %g7 133 sub %g7, %o0, %g7
159 mov %g7, %o0 134 mov %g7, %o0
160 ATOMIC_POST_BARRIER
161 retl 135 retl
162 nop 136 nop
1632: BACKOFF_SPIN(%o2, %o3, 1b) 1372: BACKOFF_SPIN(%o2, %o3, 1b)