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-rw-r--r--arch/sparc64/lib/VISsave.S131
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1/* $Id: VISsave.S,v 1.6 2002/02/09 19:49:30 davem Exp $
2 * VISsave.S: Code for saving FPU register state for
3 * VIS routines. One should not call this directly,
4 * but use macros provided in <asm/visasm.h>.
5 *
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
7 */
8
9#include <asm/asi.h>
10#include <asm/page.h>
11#include <asm/ptrace.h>
12#include <asm/visasm.h>
13#include <asm/thread_info.h>
14
15 .text
16 .globl VISenter, VISenterhalf
17
18 /* On entry: %o5=current FPRS value, %g7 is callers address */
19 /* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
20
21 /* Nothing special need be done here to handle pre-emption, this
22 * FPU save/restore mechanism is already preemption safe.
23 */
24
25 .align 32
26VISenter:
27 ldub [%g6 + TI_FPDEPTH], %g1
28 brnz,a,pn %g1, 1f
29 cmp %g1, 1
30 stb %g0, [%g6 + TI_FPSAVED]
31 stx %fsr, [%g6 + TI_XFSR]
329: jmpl %g7 + %g0, %g0
33 nop
341: bne,pn %icc, 2f
35
36 srl %g1, 1, %g1
37vis1: ldub [%g6 + TI_FPSAVED], %g3
38 stx %fsr, [%g6 + TI_XFSR]
39 or %g3, %o5, %g3
40 stb %g3, [%g6 + TI_FPSAVED]
41 rd %gsr, %g3
42 clr %g1
43 ba,pt %xcc, 3f
44
45 stx %g3, [%g6 + TI_GSR]
462: add %g6, %g1, %g3
47 cmp %o5, FPRS_DU
48 be,pn %icc, 6f
49 sll %g1, 3, %g1
50 stb %o5, [%g3 + TI_FPSAVED]
51 rd %gsr, %g2
52 add %g6, %g1, %g3
53 stx %g2, [%g3 + TI_GSR]
54
55 add %g6, %g1, %g2
56 stx %fsr, [%g2 + TI_XFSR]
57 sll %g1, 5, %g1
583: andcc %o5, FPRS_DL|FPRS_DU, %g0
59 be,pn %icc, 9b
60 add %g6, TI_FPREGS, %g2
61 andcc %o5, FPRS_DL, %g0
62 membar #StoreStore | #LoadStore
63
64 be,pn %icc, 4f
65 add %g6, TI_FPREGS+0x40, %g3
66 stda %f0, [%g2 + %g1] ASI_BLK_P
67 stda %f16, [%g3 + %g1] ASI_BLK_P
68 andcc %o5, FPRS_DU, %g0
69 be,pn %icc, 5f
704: add %g1, 128, %g1
71 stda %f32, [%g2 + %g1] ASI_BLK_P
72
73 stda %f48, [%g3 + %g1] ASI_BLK_P
745: membar #Sync
75 jmpl %g7 + %g0, %g0
76 nop
77
786: ldub [%g3 + TI_FPSAVED], %o5
79 or %o5, FPRS_DU, %o5
80 add %g6, TI_FPREGS+0x80, %g2
81 stb %o5, [%g3 + TI_FPSAVED]
82
83 sll %g1, 5, %g1
84 add %g6, TI_FPREGS+0xc0, %g3
85 wr %g0, FPRS_FEF, %fprs
86 membar #StoreStore | #LoadStore
87 stda %f32, [%g2 + %g1] ASI_BLK_P
88 stda %f48, [%g3 + %g1] ASI_BLK_P
89 membar #Sync
90 jmpl %g7 + %g0, %g0
91
92 nop
93
94 .align 32
95VISenterhalf:
96 ldub [%g6 + TI_FPDEPTH], %g1
97 brnz,a,pn %g1, 1f
98 cmp %g1, 1
99 stb %g0, [%g6 + TI_FPSAVED]
100 stx %fsr, [%g6 + TI_XFSR]
101 clr %o5
102 jmpl %g7 + %g0, %g0
103 wr %g0, FPRS_FEF, %fprs
104
1051: bne,pn %icc, 2f
106 srl %g1, 1, %g1
107 ba,pt %xcc, vis1
108 sub %g7, 8, %g7
1092: addcc %g6, %g1, %g3
110 sll %g1, 3, %g1
111 andn %o5, FPRS_DU, %g2
112 stb %g2, [%g3 + TI_FPSAVED]
113
114 rd %gsr, %g2
115 add %g6, %g1, %g3
116 stx %g2, [%g3 + TI_GSR]
117 add %g6, %g1, %g2
118 stx %fsr, [%g2 + TI_XFSR]
119 sll %g1, 5, %g1
1203: andcc %o5, FPRS_DL, %g0
121 be,pn %icc, 4f
122 add %g6, TI_FPREGS, %g2
123
124 membar #StoreStore | #LoadStore
125 add %g6, TI_FPREGS+0x40, %g3
126 stda %f0, [%g2 + %g1] ASI_BLK_P
127 stda %f16, [%g3 + %g1] ASI_BLK_P
128 membar #Sync
1294: and %o5, FPRS_DU, %o5
130 jmpl %g7 + %g0, %g0
131 wr %o5, FPRS_FEF, %fprs
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