diff options
Diffstat (limited to 'arch/sparc64/kernel/tsb.S')
-rw-r--r-- | arch/sparc64/kernel/tsb.S | 42 |
1 files changed, 27 insertions, 15 deletions
diff --git a/arch/sparc64/kernel/tsb.S b/arch/sparc64/kernel/tsb.S index c848c8847cdc..a53ec6fb7697 100644 --- a/arch/sparc64/kernel/tsb.S +++ b/arch/sparc64/kernel/tsb.S | |||
@@ -4,6 +4,7 @@ | |||
4 | */ | 4 | */ |
5 | 5 | ||
6 | #include <asm/tsb.h> | 6 | #include <asm/tsb.h> |
7 | #include <asm/hypervisor.h> | ||
7 | 8 | ||
8 | .text | 9 | .text |
9 | .align 32 | 10 | .align 32 |
@@ -233,6 +234,7 @@ tsb_flush: | |||
233 | * %o1: TSB register value | 234 | * %o1: TSB register value |
234 | * %o2: TSB virtual address | 235 | * %o2: TSB virtual address |
235 | * %o3: TSB mapping locked PTE | 236 | * %o3: TSB mapping locked PTE |
237 | * %o4: Hypervisor TSB descriptor physical address | ||
236 | * | 238 | * |
237 | * We have to run this whole thing with interrupts | 239 | * We have to run this whole thing with interrupts |
238 | * disabled so that the current cpu doesn't change | 240 | * disabled so that the current cpu doesn't change |
@@ -251,30 +253,40 @@ __tsb_context_switch: | |||
251 | add %g2, %g1, %g2 | 253 | add %g2, %g1, %g2 |
252 | stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR] | 254 | stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR] |
253 | 255 | ||
254 | 661: mov TSB_REG, %g1 | 256 | sethi %hi(tlb_type), %g1 |
255 | stxa %o1, [%g1] ASI_DMMU | 257 | lduw [%g1 + %lo(tlb_type)], %g1 |
256 | .section .sun4v_2insn_patch, "ax" | 258 | cmp %g1, 3 |
257 | .word 661b | 259 | bne,pt %icc, 1f |
260 | nop | ||
261 | |||
262 | /* Hypervisor TSB switch. */ | ||
258 | mov SCRATCHPAD_UTSBREG1, %g1 | 263 | mov SCRATCHPAD_UTSBREG1, %g1 |
259 | stxa %o1, [%g1] ASI_SCRATCHPAD | 264 | stxa %o1, [%g1] ASI_SCRATCHPAD |
260 | .previous | 265 | mov -1, %g2 |
266 | mov SCRATCHPAD_UTSBREG2, %g1 | ||
267 | stxa %g2, [%g1] ASI_SCRATCHPAD | ||
261 | 268 | ||
262 | membar #Sync | 269 | mov HV_FAST_MMU_TSB_CTXNON0, %o0 |
270 | mov 1, %o1 | ||
271 | mov %o4, %o2 | ||
272 | ta HV_FAST_TRAP | ||
273 | |||
274 | ba,pt %xcc, 9f | ||
275 | nop | ||
263 | 276 | ||
264 | 661: stxa %o1, [%g1] ASI_IMMU | 277 | /* SUN4U TSB switch. */ |
278 | 1: mov TSB_REG, %g1 | ||
279 | stxa %o1, [%g1] ASI_DMMU | ||
280 | membar #Sync | ||
281 | stxa %o1, [%g1] ASI_IMMU | ||
265 | membar #Sync | 282 | membar #Sync |
266 | .section .sun4v_2insn_patch, "ax" | ||
267 | .word 661b | ||
268 | nop | ||
269 | nop | ||
270 | .previous | ||
271 | 283 | ||
272 | brz %o2, 9f | 284 | 2: brz %o2, 9f |
273 | nop | 285 | nop |
274 | 286 | ||
275 | sethi %hi(sparc64_highest_unlocked_tlb_ent), %o4 | 287 | sethi %hi(sparc64_highest_unlocked_tlb_ent), %g2 |
276 | mov TLB_TAG_ACCESS, %g1 | 288 | mov TLB_TAG_ACCESS, %g1 |
277 | lduw [%o4 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2 | 289 | lduw [%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2 |
278 | stxa %o2, [%g1] ASI_DMMU | 290 | stxa %o2, [%g1] ASI_DMMU |
279 | membar #Sync | 291 | membar #Sync |
280 | sllx %g2, 3, %g2 | 292 | sllx %g2, 3, %g2 |