diff options
Diffstat (limited to 'arch/sparc64/kernel/traps.c')
-rw-r--r-- | arch/sparc64/kernel/traps.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c index 56b203a2af69..a9f4596d7c2b 100644 --- a/arch/sparc64/kernel/traps.c +++ b/arch/sparc64/kernel/traps.c | |||
@@ -421,6 +421,25 @@ asmlinkage void cee_log(unsigned long ce_status, | |||
421 | } | 421 | } |
422 | } | 422 | } |
423 | 423 | ||
424 | int cheetah_pcache_forced_on; | ||
425 | |||
426 | void cheetah_enable_pcache(void) | ||
427 | { | ||
428 | unsigned long dcr; | ||
429 | |||
430 | printk("CHEETAH: Enabling P-Cache on cpu %d.\n", | ||
431 | smp_processor_id()); | ||
432 | |||
433 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | ||
434 | : "=r" (dcr) | ||
435 | : "i" (ASI_DCU_CONTROL_REG)); | ||
436 | dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL); | ||
437 | __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" | ||
438 | "membar #Sync" | ||
439 | : /* no outputs */ | ||
440 | : "r" (dcr), "i" (ASI_DCU_CONTROL_REG)); | ||
441 | } | ||
442 | |||
424 | /* Cheetah error trap handling. */ | 443 | /* Cheetah error trap handling. */ |
425 | static unsigned long ecache_flush_physbase; | 444 | static unsigned long ecache_flush_physbase; |
426 | static unsigned long ecache_flush_linesize; | 445 | static unsigned long ecache_flush_linesize; |