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-rw-r--r--arch/sparc64/kernel/sbus.c1243
1 files changed, 1243 insertions, 0 deletions
diff --git a/arch/sparc64/kernel/sbus.c b/arch/sparc64/kernel/sbus.c
new file mode 100644
index 000000000000..14d9c3a21b9a
--- /dev/null
+++ b/arch/sparc64/kernel/sbus.c
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1/* $Id: sbus.c,v 1.19 2002/01/23 11:27:32 davem Exp $
2 * sbus.c: UltraSparc SBUS controller support.
3 *
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 */
6
7#include <linux/kernel.h>
8#include <linux/types.h>
9#include <linux/mm.h>
10#include <linux/spinlock.h>
11#include <linux/slab.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14
15#include <asm/page.h>
16#include <asm/sbus.h>
17#include <asm/io.h>
18#include <asm/upa.h>
19#include <asm/cache.h>
20#include <asm/dma.h>
21#include <asm/irq.h>
22#include <asm/starfire.h>
23
24#include "iommu_common.h"
25
26/* These should be allocated on an SMP_CACHE_BYTES
27 * aligned boundary for optimal performance.
28 *
29 * On SYSIO, using an 8K page size we have 1GB of SBUS
30 * DMA space mapped. We divide this space into equally
31 * sized clusters. We allocate a DMA mapping from the
32 * cluster that matches the order of the allocation, or
33 * if the order is greater than the number of clusters,
34 * we try to allocate from the last cluster.
35 */
36
37#define NCLUSTERS 8UL
38#define ONE_GIG (1UL * 1024UL * 1024UL * 1024UL)
39#define CLUSTER_SIZE (ONE_GIG / NCLUSTERS)
40#define CLUSTER_MASK (CLUSTER_SIZE - 1)
41#define CLUSTER_NPAGES (CLUSTER_SIZE >> IO_PAGE_SHIFT)
42#define MAP_BASE ((u32)0xc0000000)
43
44struct sbus_iommu {
45/*0x00*/spinlock_t lock;
46
47/*0x08*/iopte_t *page_table;
48/*0x10*/unsigned long strbuf_regs;
49/*0x18*/unsigned long iommu_regs;
50/*0x20*/unsigned long sbus_control_reg;
51
52/*0x28*/volatile unsigned long strbuf_flushflag;
53
54 /* If NCLUSTERS is ever decresed to 4 or lower,
55 * you must increase the size of the type of
56 * these counters. You have been duly warned. -DaveM
57 */
58/*0x30*/struct {
59 u16 next;
60 u16 flush;
61 } alloc_info[NCLUSTERS];
62
63 /* The lowest used consistent mapping entry. Since
64 * we allocate consistent maps out of cluster 0 this
65 * is relative to the beginning of closter 0.
66 */
67/*0x50*/u32 lowest_consistent_map;
68};
69
70/* Offsets from iommu_regs */
71#define SYSIO_IOMMUREG_BASE 0x2400UL
72#define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
73#define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
74#define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
75#define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
76#define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
77#define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
78#define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
79#define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
80
81#define IOMMU_DRAM_VALID (1UL << 30UL)
82
83static void __iommu_flushall(struct sbus_iommu *iommu)
84{
85 unsigned long tag = iommu->iommu_regs + IOMMU_TAGDIAG;
86 int entry;
87
88 for (entry = 0; entry < 16; entry++) {
89 upa_writeq(0, tag);
90 tag += 8UL;
91 }
92 upa_readq(iommu->sbus_control_reg);
93
94 for (entry = 0; entry < NCLUSTERS; entry++) {
95 iommu->alloc_info[entry].flush =
96 iommu->alloc_info[entry].next;
97 }
98}
99
100static void iommu_flush(struct sbus_iommu *iommu, u32 base, unsigned long npages)
101{
102 while (npages--)
103 upa_writeq(base + (npages << IO_PAGE_SHIFT),
104 iommu->iommu_regs + IOMMU_FLUSH);
105 upa_readq(iommu->sbus_control_reg);
106}
107
108/* Offsets from strbuf_regs */
109#define SYSIO_STRBUFREG_BASE 0x2800UL
110#define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
111#define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */
112#define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */
113#define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */
114#define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */
115#define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */
116#define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */
117
118#define STRBUF_TAG_VALID 0x02UL
119
120static void strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned long npages)
121{
122 iommu->strbuf_flushflag = 0UL;
123 while (npages--)
124 upa_writeq(base + (npages << IO_PAGE_SHIFT),
125 iommu->strbuf_regs + STRBUF_PFLUSH);
126
127 /* Whoopee cushion! */
128 upa_writeq(__pa(&iommu->strbuf_flushflag),
129 iommu->strbuf_regs + STRBUF_FSYNC);
130 upa_readq(iommu->sbus_control_reg);
131 while (iommu->strbuf_flushflag == 0UL)
132 membar("#LoadLoad");
133}
134
135static iopte_t *alloc_streaming_cluster(struct sbus_iommu *iommu, unsigned long npages)
136{
137 iopte_t *iopte, *limit, *first, *cluster;
138 unsigned long cnum, ent, nent, flush_point, found;
139
140 cnum = 0;
141 nent = 1;
142 while ((1UL << cnum) < npages)
143 cnum++;
144 if(cnum >= NCLUSTERS) {
145 nent = 1UL << (cnum - NCLUSTERS);
146 cnum = NCLUSTERS - 1;
147 }
148 iopte = iommu->page_table + (cnum * CLUSTER_NPAGES);
149
150 if (cnum == 0)
151 limit = (iommu->page_table +
152 iommu->lowest_consistent_map);
153 else
154 limit = (iopte + CLUSTER_NPAGES);
155
156 iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
157 flush_point = iommu->alloc_info[cnum].flush;
158
159 first = iopte;
160 cluster = NULL;
161 found = 0;
162 for (;;) {
163 if (iopte_val(*iopte) == 0UL) {
164 found++;
165 if (!cluster)
166 cluster = iopte;
167 } else {
168 /* Used cluster in the way */
169 cluster = NULL;
170 found = 0;
171 }
172
173 if (found == nent)
174 break;
175
176 iopte += (1 << cnum);
177 ent++;
178 if (iopte >= limit) {
179 iopte = (iommu->page_table + (cnum * CLUSTER_NPAGES));
180 ent = 0;
181
182 /* Multiple cluster allocations must not wrap */
183 cluster = NULL;
184 found = 0;
185 }
186 if (ent == flush_point)
187 __iommu_flushall(iommu);
188 if (iopte == first)
189 goto bad;
190 }
191
192 /* ent/iopte points to the last cluster entry we're going to use,
193 * so save our place for the next allocation.
194 */
195 if ((iopte + (1 << cnum)) >= limit)
196 ent = 0;
197 else
198 ent = ent + 1;
199 iommu->alloc_info[cnum].next = ent;
200 if (ent == flush_point)
201 __iommu_flushall(iommu);
202
203 /* I've got your streaming cluster right here buddy boy... */
204 return cluster;
205
206bad:
207 printk(KERN_EMERG "sbus: alloc_streaming_cluster of npages(%ld) failed!\n",
208 npages);
209 return NULL;
210}
211
212static void free_streaming_cluster(struct sbus_iommu *iommu, u32 base, unsigned long npages)
213{
214 unsigned long cnum, ent, nent;
215 iopte_t *iopte;
216
217 cnum = 0;
218 nent = 1;
219 while ((1UL << cnum) < npages)
220 cnum++;
221 if(cnum >= NCLUSTERS) {
222 nent = 1UL << (cnum - NCLUSTERS);
223 cnum = NCLUSTERS - 1;
224 }
225 ent = (base & CLUSTER_MASK) >> (IO_PAGE_SHIFT + cnum);
226 iopte = iommu->page_table + ((base - MAP_BASE) >> IO_PAGE_SHIFT);
227 do {
228 iopte_val(*iopte) = 0UL;
229 iopte += 1 << cnum;
230 } while(--nent);
231
232 /* If the global flush might not have caught this entry,
233 * adjust the flush point such that we will flush before
234 * ever trying to reuse it.
235 */
236#define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
237 if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
238 iommu->alloc_info[cnum].flush = ent;
239#undef between
240}
241
242/* We allocate consistent mappings from the end of cluster zero. */
243static iopte_t *alloc_consistent_cluster(struct sbus_iommu *iommu, unsigned long npages)
244{
245 iopte_t *iopte;
246
247 iopte = iommu->page_table + (1 * CLUSTER_NPAGES);
248 while (iopte > iommu->page_table) {
249 iopte--;
250 if (!(iopte_val(*iopte) & IOPTE_VALID)) {
251 unsigned long tmp = npages;
252
253 while (--tmp) {
254 iopte--;
255 if (iopte_val(*iopte) & IOPTE_VALID)
256 break;
257 }
258 if (tmp == 0) {
259 u32 entry = (iopte - iommu->page_table);
260
261 if (entry < iommu->lowest_consistent_map)
262 iommu->lowest_consistent_map = entry;
263 return iopte;
264 }
265 }
266 }
267 return NULL;
268}
269
270static void free_consistent_cluster(struct sbus_iommu *iommu, u32 base, unsigned long npages)
271{
272 iopte_t *iopte = iommu->page_table + ((base - MAP_BASE) >> IO_PAGE_SHIFT);
273
274 if ((iopte - iommu->page_table) == iommu->lowest_consistent_map) {
275 iopte_t *walk = iopte + npages;
276 iopte_t *limit;
277
278 limit = iommu->page_table + CLUSTER_NPAGES;
279 while (walk < limit) {
280 if (iopte_val(*walk) != 0UL)
281 break;
282 walk++;
283 }
284 iommu->lowest_consistent_map =
285 (walk - iommu->page_table);
286 }
287
288 while (npages--)
289 *iopte++ = __iopte(0UL);
290}
291
292void *sbus_alloc_consistent(struct sbus_dev *sdev, size_t size, dma_addr_t *dvma_addr)
293{
294 unsigned long order, first_page, flags;
295 struct sbus_iommu *iommu;
296 iopte_t *iopte;
297 void *ret;
298 int npages;
299
300 if (size <= 0 || sdev == NULL || dvma_addr == NULL)
301 return NULL;
302
303 size = IO_PAGE_ALIGN(size);
304 order = get_order(size);
305 if (order >= 10)
306 return NULL;
307 first_page = __get_free_pages(GFP_KERNEL, order);
308 if (first_page == 0UL)
309 return NULL;
310 memset((char *)first_page, 0, PAGE_SIZE << order);
311
312 iommu = sdev->bus->iommu;
313
314 spin_lock_irqsave(&iommu->lock, flags);
315 iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
316 if (iopte == NULL) {
317 spin_unlock_irqrestore(&iommu->lock, flags);
318 free_pages(first_page, order);
319 return NULL;
320 }
321
322 /* Ok, we're committed at this point. */
323 *dvma_addr = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
324 ret = (void *) first_page;
325 npages = size >> IO_PAGE_SHIFT;
326 while (npages--) {
327 *iopte++ = __iopte(IOPTE_VALID | IOPTE_CACHE | IOPTE_WRITE |
328 (__pa(first_page) & IOPTE_PAGE));
329 first_page += IO_PAGE_SIZE;
330 }
331 iommu_flush(iommu, *dvma_addr, size >> IO_PAGE_SHIFT);
332 spin_unlock_irqrestore(&iommu->lock, flags);
333
334 return ret;
335}
336
337void sbus_free_consistent(struct sbus_dev *sdev, size_t size, void *cpu, dma_addr_t dvma)
338{
339 unsigned long order, npages;
340 struct sbus_iommu *iommu;
341
342 if (size <= 0 || sdev == NULL || cpu == NULL)
343 return;
344
345 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
346 iommu = sdev->bus->iommu;
347
348 spin_lock_irq(&iommu->lock);
349 free_consistent_cluster(iommu, dvma, npages);
350 iommu_flush(iommu, dvma, npages);
351 spin_unlock_irq(&iommu->lock);
352
353 order = get_order(size);
354 if (order < 10)
355 free_pages((unsigned long)cpu, order);
356}
357
358dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr, size_t size, int dir)
359{
360 struct sbus_iommu *iommu = sdev->bus->iommu;
361 unsigned long npages, pbase, flags;
362 iopte_t *iopte;
363 u32 dma_base, offset;
364 unsigned long iopte_bits;
365
366 if (dir == SBUS_DMA_NONE)
367 BUG();
368
369 pbase = (unsigned long) ptr;
370 offset = (u32) (pbase & ~IO_PAGE_MASK);
371 size = (IO_PAGE_ALIGN(pbase + size) - (pbase & IO_PAGE_MASK));
372 pbase = (unsigned long) __pa(pbase & IO_PAGE_MASK);
373
374 spin_lock_irqsave(&iommu->lock, flags);
375 npages = size >> IO_PAGE_SHIFT;
376 iopte = alloc_streaming_cluster(iommu, npages);
377 if (iopte == NULL)
378 goto bad;
379 dma_base = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
380 npages = size >> IO_PAGE_SHIFT;
381 iopte_bits = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
382 if (dir != SBUS_DMA_TODEVICE)
383 iopte_bits |= IOPTE_WRITE;
384 while (npages--) {
385 *iopte++ = __iopte(iopte_bits | (pbase & IOPTE_PAGE));
386 pbase += IO_PAGE_SIZE;
387 }
388 npages = size >> IO_PAGE_SHIFT;
389 spin_unlock_irqrestore(&iommu->lock, flags);
390
391 return (dma_base | offset);
392
393bad:
394 spin_unlock_irqrestore(&iommu->lock, flags);
395 BUG();
396 return 0;
397}
398
399void sbus_unmap_single(struct sbus_dev *sdev, dma_addr_t dma_addr, size_t size, int direction)
400{
401 struct sbus_iommu *iommu = sdev->bus->iommu;
402 u32 dma_base = dma_addr & IO_PAGE_MASK;
403 unsigned long flags;
404
405 size = (IO_PAGE_ALIGN(dma_addr + size) - dma_base);
406
407 spin_lock_irqsave(&iommu->lock, flags);
408 free_streaming_cluster(iommu, dma_base, size >> IO_PAGE_SHIFT);
409 strbuf_flush(iommu, dma_base, size >> IO_PAGE_SHIFT);
410 spin_unlock_irqrestore(&iommu->lock, flags);
411}
412
413#define SG_ENT_PHYS_ADDRESS(SG) \
414 (__pa(page_address((SG)->page)) + (SG)->offset)
415
416static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg, int nused, int nelems, unsigned long iopte_bits)
417{
418 struct scatterlist *dma_sg = sg;
419 struct scatterlist *sg_end = sg + nelems;
420 int i;
421
422 for (i = 0; i < nused; i++) {
423 unsigned long pteval = ~0UL;
424 u32 dma_npages;
425
426 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
427 dma_sg->dma_length +
428 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
429 do {
430 unsigned long offset;
431 signed int len;
432
433 /* If we are here, we know we have at least one
434 * more page to map. So walk forward until we
435 * hit a page crossing, and begin creating new
436 * mappings from that spot.
437 */
438 for (;;) {
439 unsigned long tmp;
440
441 tmp = (unsigned long) SG_ENT_PHYS_ADDRESS(sg);
442 len = sg->length;
443 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
444 pteval = tmp & IO_PAGE_MASK;
445 offset = tmp & (IO_PAGE_SIZE - 1UL);
446 break;
447 }
448 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
449 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
450 offset = 0UL;
451 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
452 break;
453 }
454 sg++;
455 }
456
457 pteval = ((pteval & IOPTE_PAGE) | iopte_bits);
458 while (len > 0) {
459 *iopte++ = __iopte(pteval);
460 pteval += IO_PAGE_SIZE;
461 len -= (IO_PAGE_SIZE - offset);
462 offset = 0;
463 dma_npages--;
464 }
465
466 pteval = (pteval & IOPTE_PAGE) + len;
467 sg++;
468
469 /* Skip over any tail mappings we've fully mapped,
470 * adjusting pteval along the way. Stop when we
471 * detect a page crossing event.
472 */
473 while (sg < sg_end &&
474 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
475 (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
476 ((pteval ^
477 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
478 pteval += sg->length;
479 sg++;
480 }
481 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
482 pteval = ~0UL;
483 } while (dma_npages != 0);
484 dma_sg++;
485 }
486}
487
488int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int dir)
489{
490 struct sbus_iommu *iommu = sdev->bus->iommu;
491 unsigned long flags, npages;
492 iopte_t *iopte;
493 u32 dma_base;
494 struct scatterlist *sgtmp;
495 int used;
496 unsigned long iopte_bits;
497
498 if (dir == SBUS_DMA_NONE)
499 BUG();
500
501 /* Fast path single entry scatterlists. */
502 if (nents == 1) {
503 sg->dma_address =
504 sbus_map_single(sdev,
505 (page_address(sg->page) + sg->offset),
506 sg->length, dir);
507 sg->dma_length = sg->length;
508 return 1;
509 }
510
511 npages = prepare_sg(sg, nents);
512
513 spin_lock_irqsave(&iommu->lock, flags);
514 iopte = alloc_streaming_cluster(iommu, npages);
515 if (iopte == NULL)
516 goto bad;
517 dma_base = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
518
519 /* Normalize DVMA addresses. */
520 sgtmp = sg;
521 used = nents;
522
523 while (used && sgtmp->dma_length) {
524 sgtmp->dma_address += dma_base;
525 sgtmp++;
526 used--;
527 }
528 used = nents - used;
529
530 iopte_bits = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
531 if (dir != SBUS_DMA_TODEVICE)
532 iopte_bits |= IOPTE_WRITE;
533
534 fill_sg(iopte, sg, used, nents, iopte_bits);
535#ifdef VERIFY_SG
536 verify_sglist(sg, nents, iopte, npages);
537#endif
538 spin_unlock_irqrestore(&iommu->lock, flags);
539
540 return used;
541
542bad:
543 spin_unlock_irqrestore(&iommu->lock, flags);
544 BUG();
545 return 0;
546}
547
548void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
549{
550 unsigned long size, flags;
551 struct sbus_iommu *iommu;
552 u32 dvma_base;
553 int i;
554
555 /* Fast path single entry scatterlists. */
556 if (nents == 1) {
557 sbus_unmap_single(sdev, sg->dma_address, sg->dma_length, direction);
558 return;
559 }
560
561 dvma_base = sg[0].dma_address & IO_PAGE_MASK;
562 for (i = 0; i < nents; i++) {
563 if (sg[i].dma_length == 0)
564 break;
565 }
566 i--;
567 size = IO_PAGE_ALIGN(sg[i].dma_address + sg[i].dma_length) - dvma_base;
568
569 iommu = sdev->bus->iommu;
570 spin_lock_irqsave(&iommu->lock, flags);
571 free_streaming_cluster(iommu, dvma_base, size >> IO_PAGE_SHIFT);
572 strbuf_flush(iommu, dvma_base, size >> IO_PAGE_SHIFT);
573 spin_unlock_irqrestore(&iommu->lock, flags);
574}
575
576void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev, dma_addr_t base, size_t size, int direction)
577{
578 struct sbus_iommu *iommu = sdev->bus->iommu;
579 unsigned long flags;
580
581 size = (IO_PAGE_ALIGN(base + size) - (base & IO_PAGE_MASK));
582
583 spin_lock_irqsave(&iommu->lock, flags);
584 strbuf_flush(iommu, base & IO_PAGE_MASK, size >> IO_PAGE_SHIFT);
585 spin_unlock_irqrestore(&iommu->lock, flags);
586}
587
588void sbus_dma_sync_single_for_device(struct sbus_dev *sdev, dma_addr_t base, size_t size, int direction)
589{
590}
591
592void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
593{
594 struct sbus_iommu *iommu = sdev->bus->iommu;
595 unsigned long flags, size;
596 u32 base;
597 int i;
598
599 base = sg[0].dma_address & IO_PAGE_MASK;
600 for (i = 0; i < nents; i++) {
601 if (sg[i].dma_length == 0)
602 break;
603 }
604 i--;
605 size = IO_PAGE_ALIGN(sg[i].dma_address + sg[i].dma_length) - base;
606
607 spin_lock_irqsave(&iommu->lock, flags);
608 strbuf_flush(iommu, base, size >> IO_PAGE_SHIFT);
609 spin_unlock_irqrestore(&iommu->lock, flags);
610}
611
612void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
613{
614}
615
616/* Enable 64-bit DVMA mode for the given device. */
617void sbus_set_sbus64(struct sbus_dev *sdev, int bursts)
618{
619 struct sbus_iommu *iommu = sdev->bus->iommu;
620 int slot = sdev->slot;
621 unsigned long cfg_reg;
622 u64 val;
623
624 cfg_reg = iommu->sbus_control_reg;
625 switch (slot) {
626 case 0:
627 cfg_reg += 0x20UL;
628 break;
629 case 1:
630 cfg_reg += 0x28UL;
631 break;
632 case 2:
633 cfg_reg += 0x30UL;
634 break;
635 case 3:
636 cfg_reg += 0x38UL;
637 break;
638 case 13:
639 cfg_reg += 0x40UL;
640 break;
641 case 14:
642 cfg_reg += 0x48UL;
643 break;
644 case 15:
645 cfg_reg += 0x50UL;
646 break;
647
648 default:
649 return;
650 };
651
652 val = upa_readq(cfg_reg);
653 if (val & (1UL << 14UL)) {
654 /* Extended transfer mode already enabled. */
655 return;
656 }
657
658 val |= (1UL << 14UL);
659
660 if (bursts & DMA_BURST8)
661 val |= (1UL << 1UL);
662 if (bursts & DMA_BURST16)
663 val |= (1UL << 2UL);
664 if (bursts & DMA_BURST32)
665 val |= (1UL << 3UL);
666 if (bursts & DMA_BURST64)
667 val |= (1UL << 4UL);
668 upa_writeq(val, cfg_reg);
669}
670
671/* SBUS SYSIO INO number to Sparc PIL level. */
672static unsigned char sysio_ino_to_pil[] = {
673 0, 4, 4, 7, 5, 7, 8, 9, /* SBUS slot 0 */
674 0, 4, 4, 7, 5, 7, 8, 9, /* SBUS slot 1 */
675 0, 4, 4, 7, 5, 7, 8, 9, /* SBUS slot 2 */
676 0, 4, 4, 7, 5, 7, 8, 9, /* SBUS slot 3 */
677 4, /* Onboard SCSI */
678 5, /* Onboard Ethernet */
679/*XXX*/ 8, /* Onboard BPP */
680 0, /* Bogon */
681 13, /* Audio */
682/*XXX*/15, /* PowerFail */
683 0, /* Bogon */
684 0, /* Bogon */
685 12, /* Zilog Serial Channels (incl. Keyboard/Mouse lines) */
686 11, /* Floppy */
687 0, /* Spare Hardware (bogon for now) */
688 0, /* Keyboard (bogon for now) */
689 0, /* Mouse (bogon for now) */
690 0, /* Serial (bogon for now) */
691 0, 0, /* Bogon, Bogon */
692 10, /* Timer 0 */
693 11, /* Timer 1 */
694 0, 0, /* Bogon, Bogon */
695 15, /* Uncorrectable SBUS Error */
696 15, /* Correctable SBUS Error */
697 15, /* SBUS Error */
698/*XXX*/ 0, /* Power Management (bogon for now) */
699};
700
701/* INO number to IMAP register offset for SYSIO external IRQ's.
702 * This should conform to both Sunfire/Wildfire server and Fusion
703 * desktop designs.
704 */
705#define SYSIO_IMAP_SLOT0 0x2c04UL
706#define SYSIO_IMAP_SLOT1 0x2c0cUL
707#define SYSIO_IMAP_SLOT2 0x2c14UL
708#define SYSIO_IMAP_SLOT3 0x2c1cUL
709#define SYSIO_IMAP_SCSI 0x3004UL
710#define SYSIO_IMAP_ETH 0x300cUL
711#define SYSIO_IMAP_BPP 0x3014UL
712#define SYSIO_IMAP_AUDIO 0x301cUL
713#define SYSIO_IMAP_PFAIL 0x3024UL
714#define SYSIO_IMAP_KMS 0x302cUL
715#define SYSIO_IMAP_FLPY 0x3034UL
716#define SYSIO_IMAP_SHW 0x303cUL
717#define SYSIO_IMAP_KBD 0x3044UL
718#define SYSIO_IMAP_MS 0x304cUL
719#define SYSIO_IMAP_SER 0x3054UL
720#define SYSIO_IMAP_TIM0 0x3064UL
721#define SYSIO_IMAP_TIM1 0x306cUL
722#define SYSIO_IMAP_UE 0x3074UL
723#define SYSIO_IMAP_CE 0x307cUL
724#define SYSIO_IMAP_SBERR 0x3084UL
725#define SYSIO_IMAP_PMGMT 0x308cUL
726#define SYSIO_IMAP_GFX 0x3094UL
727#define SYSIO_IMAP_EUPA 0x309cUL
728
729#define bogon ((unsigned long) -1)
730static unsigned long sysio_irq_offsets[] = {
731 /* SBUS Slot 0 --> 3, level 1 --> 7 */
732 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
733 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
734 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
735 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
736 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
737 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
738 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
739 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
740
741 /* Onboard devices (not relevant/used on SunFire). */
742 SYSIO_IMAP_SCSI,
743 SYSIO_IMAP_ETH,
744 SYSIO_IMAP_BPP,
745 bogon,
746 SYSIO_IMAP_AUDIO,
747 SYSIO_IMAP_PFAIL,
748 bogon,
749 bogon,
750 SYSIO_IMAP_KMS,
751 SYSIO_IMAP_FLPY,
752 SYSIO_IMAP_SHW,
753 SYSIO_IMAP_KBD,
754 SYSIO_IMAP_MS,
755 SYSIO_IMAP_SER,
756 bogon,
757 bogon,
758 SYSIO_IMAP_TIM0,
759 SYSIO_IMAP_TIM1,
760 bogon,
761 bogon,
762 SYSIO_IMAP_UE,
763 SYSIO_IMAP_CE,
764 SYSIO_IMAP_SBERR,
765 SYSIO_IMAP_PMGMT,
766};
767
768#undef bogon
769
770#define NUM_SYSIO_OFFSETS (sizeof(sysio_irq_offsets) / sizeof(sysio_irq_offsets[0]))
771
772/* Convert Interrupt Mapping register pointer to associated
773 * Interrupt Clear register pointer, SYSIO specific version.
774 */
775#define SYSIO_ICLR_UNUSED0 0x3400UL
776#define SYSIO_ICLR_SLOT0 0x340cUL
777#define SYSIO_ICLR_SLOT1 0x344cUL
778#define SYSIO_ICLR_SLOT2 0x348cUL
779#define SYSIO_ICLR_SLOT3 0x34ccUL
780static unsigned long sysio_imap_to_iclr(unsigned long imap)
781{
782 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
783 return imap + diff;
784}
785
786unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
787{
788 struct sbus_bus *sbus = (struct sbus_bus *)buscookie;
789 struct sbus_iommu *iommu = sbus->iommu;
790 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
791 unsigned long imap, iclr;
792 int pil, sbus_level = 0;
793
794 pil = sysio_ino_to_pil[ino];
795 if (!pil) {
796 printk("sbus_irq_build: Bad SYSIO INO[%x]\n", ino);
797 panic("Bad SYSIO IRQ translations...");
798 }
799
800 if (PIL_RESERVED(pil))
801 BUG();
802
803 imap = sysio_irq_offsets[ino];
804 if (imap == ((unsigned long)-1)) {
805 prom_printf("get_irq_translations: Bad SYSIO INO[%x] cpu[%d]\n",
806 ino, pil);
807 prom_halt();
808 }
809 imap += reg_base;
810
811 /* SYSIO inconsistency. For external SLOTS, we have to select
812 * the right ICLR register based upon the lower SBUS irq level
813 * bits.
814 */
815 if (ino >= 0x20) {
816 iclr = sysio_imap_to_iclr(imap);
817 } else {
818 int sbus_slot = (ino & 0x18)>>3;
819
820 sbus_level = ino & 0x7;
821
822 switch(sbus_slot) {
823 case 0:
824 iclr = reg_base + SYSIO_ICLR_SLOT0;
825 break;
826 case 1:
827 iclr = reg_base + SYSIO_ICLR_SLOT1;
828 break;
829 case 2:
830 iclr = reg_base + SYSIO_ICLR_SLOT2;
831 break;
832 default:
833 case 3:
834 iclr = reg_base + SYSIO_ICLR_SLOT3;
835 break;
836 };
837
838 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
839 }
840 return build_irq(pil, sbus_level, iclr, imap);
841}
842
843/* Error interrupt handling. */
844#define SYSIO_UE_AFSR 0x0030UL
845#define SYSIO_UE_AFAR 0x0038UL
846#define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
847#define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
848#define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
849#define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
850#define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
851#define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
852#define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
853#define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */
854#define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
855#define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
856#define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
857static irqreturn_t sysio_ue_handler(int irq, void *dev_id, struct pt_regs *regs)
858{
859 struct sbus_bus *sbus = dev_id;
860 struct sbus_iommu *iommu = sbus->iommu;
861 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
862 unsigned long afsr_reg, afar_reg;
863 unsigned long afsr, afar, error_bits;
864 int reported;
865
866 afsr_reg = reg_base + SYSIO_UE_AFSR;
867 afar_reg = reg_base + SYSIO_UE_AFAR;
868
869 /* Latch error status. */
870 afsr = upa_readq(afsr_reg);
871 afar = upa_readq(afar_reg);
872
873 /* Clear primary/secondary error status bits. */
874 error_bits = afsr &
875 (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
876 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
877 upa_writeq(error_bits, afsr_reg);
878
879 /* Log the error. */
880 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
881 sbus->portid,
882 (((error_bits & SYSIO_UEAFSR_PPIO) ?
883 "PIO" :
884 ((error_bits & SYSIO_UEAFSR_PDRD) ?
885 "DVMA Read" :
886 ((error_bits & SYSIO_UEAFSR_PDWR) ?
887 "DVMA Write" : "???")))));
888 printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
889 sbus->portid,
890 (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
891 (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
892 (afsr & SYSIO_UEAFSR_MID) >> 37UL);
893 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
894 printk("SYSIO[%x]: Secondary UE errors [", sbus->portid);
895 reported = 0;
896 if (afsr & SYSIO_UEAFSR_SPIO) {
897 reported++;
898 printk("(PIO)");
899 }
900 if (afsr & SYSIO_UEAFSR_SDRD) {
901 reported++;
902 printk("(DVMA Read)");
903 }
904 if (afsr & SYSIO_UEAFSR_SDWR) {
905 reported++;
906 printk("(DVMA Write)");
907 }
908 if (!reported)
909 printk("(none)");
910 printk("]\n");
911
912 return IRQ_HANDLED;
913}
914
915#define SYSIO_CE_AFSR 0x0040UL
916#define SYSIO_CE_AFAR 0x0048UL
917#define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
918#define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
919#define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
920#define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
921#define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
922#define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
923#define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
924#define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
925#define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */
926#define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
927#define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
928#define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
929static irqreturn_t sysio_ce_handler(int irq, void *dev_id, struct pt_regs *regs)
930{
931 struct sbus_bus *sbus = dev_id;
932 struct sbus_iommu *iommu = sbus->iommu;
933 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
934 unsigned long afsr_reg, afar_reg;
935 unsigned long afsr, afar, error_bits;
936 int reported;
937
938 afsr_reg = reg_base + SYSIO_CE_AFSR;
939 afar_reg = reg_base + SYSIO_CE_AFAR;
940
941 /* Latch error status. */
942 afsr = upa_readq(afsr_reg);
943 afar = upa_readq(afar_reg);
944
945 /* Clear primary/secondary error status bits. */
946 error_bits = afsr &
947 (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
948 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
949 upa_writeq(error_bits, afsr_reg);
950
951 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
952 sbus->portid,
953 (((error_bits & SYSIO_CEAFSR_PPIO) ?
954 "PIO" :
955 ((error_bits & SYSIO_CEAFSR_PDRD) ?
956 "DVMA Read" :
957 ((error_bits & SYSIO_CEAFSR_PDWR) ?
958 "DVMA Write" : "???")))));
959
960 /* XXX Use syndrome and afar to print out module string just like
961 * XXX UDB CE trap handler does... -DaveM
962 */
963 printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
964 sbus->portid,
965 (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
966 (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
967 (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
968 (afsr & SYSIO_CEAFSR_MID) >> 37UL);
969 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
970
971 printk("SYSIO[%x]: Secondary CE errors [", sbus->portid);
972 reported = 0;
973 if (afsr & SYSIO_CEAFSR_SPIO) {
974 reported++;
975 printk("(PIO)");
976 }
977 if (afsr & SYSIO_CEAFSR_SDRD) {
978 reported++;
979 printk("(DVMA Read)");
980 }
981 if (afsr & SYSIO_CEAFSR_SDWR) {
982 reported++;
983 printk("(DVMA Write)");
984 }
985 if (!reported)
986 printk("(none)");
987 printk("]\n");
988
989 return IRQ_HANDLED;
990}
991
992#define SYSIO_SBUS_AFSR 0x2010UL
993#define SYSIO_SBUS_AFAR 0x2018UL
994#define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */
995#define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */
996#define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */
997#define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */
998#define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */
999#define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */
1000#define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */
1001#define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */
1002#define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */
1003#define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */
1004#define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */
1005#define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */
1006static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id, struct pt_regs *regs)
1007{
1008 struct sbus_bus *sbus = dev_id;
1009 struct sbus_iommu *iommu = sbus->iommu;
1010 unsigned long afsr_reg, afar_reg, reg_base;
1011 unsigned long afsr, afar, error_bits;
1012 int reported;
1013
1014 reg_base = iommu->sbus_control_reg - 0x2000UL;
1015 afsr_reg = reg_base + SYSIO_SBUS_AFSR;
1016 afar_reg = reg_base + SYSIO_SBUS_AFAR;
1017
1018 afsr = upa_readq(afsr_reg);
1019 afar = upa_readq(afar_reg);
1020
1021 /* Clear primary/secondary error status bits. */
1022 error_bits = afsr &
1023 (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
1024 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
1025 upa_writeq(error_bits, afsr_reg);
1026
1027 /* Log the error. */
1028 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
1029 sbus->portid,
1030 (((error_bits & SYSIO_SBAFSR_PLE) ?
1031 "Late PIO Error" :
1032 ((error_bits & SYSIO_SBAFSR_PTO) ?
1033 "Time Out" :
1034 ((error_bits & SYSIO_SBAFSR_PBERR) ?
1035 "Error Ack" : "???")))),
1036 (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
1037 printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
1038 sbus->portid,
1039 (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
1040 (afsr & SYSIO_SBAFSR_MID) >> 37UL);
1041 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
1042 printk("SYSIO[%x]: Secondary SBUS errors [", sbus->portid);
1043 reported = 0;
1044 if (afsr & SYSIO_SBAFSR_SLE) {
1045 reported++;
1046 printk("(Late PIO Error)");
1047 }
1048 if (afsr & SYSIO_SBAFSR_STO) {
1049 reported++;
1050 printk("(Time Out)");
1051 }
1052 if (afsr & SYSIO_SBAFSR_SBERR) {
1053 reported++;
1054 printk("(Error Ack)");
1055 }
1056 if (!reported)
1057 printk("(none)");
1058 printk("]\n");
1059
1060 /* XXX check iommu/strbuf for further error status XXX */
1061
1062 return IRQ_HANDLED;
1063}
1064
1065#define ECC_CONTROL 0x0020UL
1066#define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */
1067#define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */
1068#define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */
1069
1070#define SYSIO_UE_INO 0x34
1071#define SYSIO_CE_INO 0x35
1072#define SYSIO_SBUSERR_INO 0x36
1073
1074static void __init sysio_register_error_handlers(struct sbus_bus *sbus)
1075{
1076 struct sbus_iommu *iommu = sbus->iommu;
1077 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
1078 unsigned int irq;
1079 u64 control;
1080
1081 irq = sbus_build_irq(sbus, SYSIO_UE_INO);
1082 if (request_irq(irq, sysio_ue_handler,
1083 SA_SHIRQ, "SYSIO UE", sbus) < 0) {
1084 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
1085 sbus->portid);
1086 prom_halt();
1087 }
1088
1089 irq = sbus_build_irq(sbus, SYSIO_CE_INO);
1090 if (request_irq(irq, sysio_ce_handler,
1091 SA_SHIRQ, "SYSIO CE", sbus) < 0) {
1092 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
1093 sbus->portid);
1094 prom_halt();
1095 }
1096
1097 irq = sbus_build_irq(sbus, SYSIO_SBUSERR_INO);
1098 if (request_irq(irq, sysio_sbus_error_handler,
1099 SA_SHIRQ, "SYSIO SBUS Error", sbus) < 0) {
1100 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
1101 sbus->portid);
1102 prom_halt();
1103 }
1104
1105 /* Now turn the error interrupts on and also enable ECC checking. */
1106 upa_writeq((SYSIO_ECNTRL_ECCEN |
1107 SYSIO_ECNTRL_UEEN |
1108 SYSIO_ECNTRL_CEEN),
1109 reg_base + ECC_CONTROL);
1110
1111 control = upa_readq(iommu->sbus_control_reg);
1112 control |= 0x100UL; /* SBUS Error Interrupt Enable */
1113 upa_writeq(control, iommu->sbus_control_reg);
1114}
1115
1116/* Boot time initialization. */
1117void __init sbus_iommu_init(int prom_node, struct sbus_bus *sbus)
1118{
1119 struct linux_prom64_registers rprop;
1120 struct sbus_iommu *iommu;
1121 unsigned long regs, tsb_base;
1122 u64 control;
1123 int err, i;
1124
1125 sbus->portid = prom_getintdefault(sbus->prom_node,
1126 "upa-portid", -1);
1127
1128 err = prom_getproperty(prom_node, "reg",
1129 (char *)&rprop, sizeof(rprop));
1130 if (err < 0) {
1131 prom_printf("sbus_iommu_init: Cannot map SYSIO control registers.\n");
1132 prom_halt();
1133 }
1134 regs = rprop.phys_addr;
1135
1136 iommu = kmalloc(sizeof(*iommu) + SMP_CACHE_BYTES, GFP_ATOMIC);
1137 if (iommu == NULL) {
1138 prom_printf("sbus_iommu_init: Fatal error, kmalloc(iommu) failed\n");
1139 prom_halt();
1140 }
1141
1142 /* Align on E$ line boundary. */
1143 iommu = (struct sbus_iommu *)
1144 (((unsigned long)iommu + (SMP_CACHE_BYTES - 1UL)) &
1145 ~(SMP_CACHE_BYTES - 1UL));
1146
1147 memset(iommu, 0, sizeof(*iommu));
1148
1149 /* We start with no consistent mappings. */
1150 iommu->lowest_consistent_map = CLUSTER_NPAGES;
1151
1152 for (i = 0; i < NCLUSTERS; i++) {
1153 iommu->alloc_info[i].flush = 0;
1154 iommu->alloc_info[i].next = 0;
1155 }
1156
1157 /* Setup spinlock. */
1158 spin_lock_init(&iommu->lock);
1159
1160 /* Init register offsets. */
1161 iommu->iommu_regs = regs + SYSIO_IOMMUREG_BASE;
1162 iommu->strbuf_regs = regs + SYSIO_STRBUFREG_BASE;
1163
1164 /* The SYSIO SBUS control register is used for dummy reads
1165 * in order to ensure write completion.
1166 */
1167 iommu->sbus_control_reg = regs + 0x2000UL;
1168
1169 /* Link into SYSIO software state. */
1170 sbus->iommu = iommu;
1171
1172 printk("SYSIO: UPA portID %x, at %016lx\n",
1173 sbus->portid, regs);
1174
1175 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
1176 control = upa_readq(iommu->iommu_regs + IOMMU_CONTROL);
1177 control = ((7UL << 16UL) |
1178 (0UL << 2UL) |
1179 (1UL << 1UL) |
1180 (1UL << 0UL));
1181
1182 /* Using the above configuration we need 1MB iommu page
1183 * table (128K ioptes * 8 bytes per iopte). This is
1184 * page order 7 on UltraSparc.
1185 */
1186 tsb_base = __get_free_pages(GFP_ATOMIC, get_order(IO_TSB_SIZE));
1187 if (tsb_base == 0UL) {
1188 prom_printf("sbus_iommu_init: Fatal error, cannot alloc TSB table.\n");
1189 prom_halt();
1190 }
1191
1192 iommu->page_table = (iopte_t *) tsb_base;
1193 memset(iommu->page_table, 0, IO_TSB_SIZE);
1194
1195 upa_writeq(control, iommu->iommu_regs + IOMMU_CONTROL);
1196
1197 /* Clean out any cruft in the IOMMU using
1198 * diagnostic accesses.
1199 */
1200 for (i = 0; i < 16; i++) {
1201 unsigned long dram = iommu->iommu_regs + IOMMU_DRAMDIAG;
1202 unsigned long tag = iommu->iommu_regs + IOMMU_TAGDIAG;
1203
1204 dram += (unsigned long)i * 8UL;
1205 tag += (unsigned long)i * 8UL;
1206 upa_writeq(0, dram);
1207 upa_writeq(0, tag);
1208 }
1209 upa_readq(iommu->sbus_control_reg);
1210
1211 /* Give the TSB to SYSIO. */
1212 upa_writeq(__pa(tsb_base), iommu->iommu_regs + IOMMU_TSBBASE);
1213
1214 /* Setup streaming buffer, DE=1 SB_EN=1 */
1215 control = (1UL << 1UL) | (1UL << 0UL);
1216 upa_writeq(control, iommu->strbuf_regs + STRBUF_CONTROL);
1217
1218 /* Clear out the tags using diagnostics. */
1219 for (i = 0; i < 16; i++) {
1220 unsigned long ptag, ltag;
1221
1222 ptag = iommu->strbuf_regs + STRBUF_PTAGDIAG;
1223 ltag = iommu->strbuf_regs + STRBUF_LTAGDIAG;
1224 ptag += (unsigned long)i * 8UL;
1225 ltag += (unsigned long)i * 8UL;
1226
1227 upa_writeq(0UL, ptag);
1228 upa_writeq(0UL, ltag);
1229 }
1230
1231 /* Enable DVMA arbitration for all devices/slots. */
1232 control = upa_readq(iommu->sbus_control_reg);
1233 control |= 0x3fUL;
1234 upa_writeq(control, iommu->sbus_control_reg);
1235
1236 /* Now some Xfire specific grot... */
1237 if (this_is_starfire)
1238 sbus->starfire_cookie = starfire_hookup(sbus->portid);
1239 else
1240 sbus->starfire_cookie = NULL;
1241
1242 sysio_register_error_handlers(sbus);
1243}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 16:33:14 -0500