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-rw-r--r--arch/sparc64/kernel/pci_schizo.c2187
1 files changed, 2187 insertions, 0 deletions
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
new file mode 100644
index 000000000000..e93fcadc3722
--- /dev/null
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -0,0 +1,2187 @@
1/* $Id: pci_schizo.c,v 1.24 2002/01/23 11:27:32 davem Exp $
2 * pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
3 *
4 * Copyright (C) 2001, 2002, 2003 David S. Miller (davem@redhat.com)
5 */
6
7#include <linux/kernel.h>
8#include <linux/types.h>
9#include <linux/pci.h>
10#include <linux/init.h>
11#include <linux/slab.h>
12#include <linux/interrupt.h>
13
14#include <asm/pbm.h>
15#include <asm/iommu.h>
16#include <asm/irq.h>
17#include <asm/upa.h>
18
19#include "pci_impl.h"
20#include "iommu_common.h"
21
22/* All SCHIZO registers are 64-bits. The following accessor
23 * routines are how they are accessed. The REG parameter
24 * is a physical address.
25 */
26#define schizo_read(__reg) \
27({ u64 __ret; \
28 __asm__ __volatile__("ldxa [%1] %2, %0" \
29 : "=r" (__ret) \
30 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
31 : "memory"); \
32 __ret; \
33})
34#define schizo_write(__reg, __val) \
35 __asm__ __volatile__("stxa %0, [%1] %2" \
36 : /* no outputs */ \
37 : "r" (__val), "r" (__reg), \
38 "i" (ASI_PHYS_BYPASS_EC_E) \
39 : "memory")
40
41/* This is a convention that at least Excalibur and Merlin
42 * follow. I suppose the SCHIZO used in Starcat and friends
43 * will do similar.
44 *
45 * The only way I could see this changing is if the newlink
46 * block requires more space in Schizo's address space than
47 * they predicted, thus requiring an address space reorg when
48 * the newer Schizo is taped out.
49 */
50
51/* Streaming buffer control register. */
52#define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
53#define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
54#define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
55#define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
56#define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
57
58/* IOMMU control register. */
59#define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
60#define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
61#define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
62#define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
63#define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
64#define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
65#define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
66#define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
67#define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
68#define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
69#define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
70#define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
71#define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
72#define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
73#define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
74#define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
75#define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
76#define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
77
78/* Schizo config space address format is nearly identical to
79 * that of PSYCHO:
80 *
81 * 32 24 23 16 15 11 10 8 7 2 1 0
82 * ---------------------------------------------------------
83 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
84 * ---------------------------------------------------------
85 */
86#define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
87#define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
88 (((unsigned long)(BUS) << 16) | \
89 ((unsigned long)(DEVFN) << 8) | \
90 ((unsigned long)(REG)))
91
92static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
93 unsigned char bus,
94 unsigned int devfn,
95 int where)
96{
97 if (!pbm)
98 return NULL;
99 bus -= pbm->pci_first_busno;
100 return (void *)
101 (SCHIZO_CONFIG_BASE(pbm) |
102 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
103}
104
105/* Just make sure the bus number is in range. */
106static int schizo_out_of_range(struct pci_pbm_info *pbm,
107 unsigned char bus,
108 unsigned char devfn)
109{
110 if (bus < pbm->pci_first_busno ||
111 bus > pbm->pci_last_busno)
112 return 1;
113 return 0;
114}
115
116/* SCHIZO PCI configuration space accessors. */
117
118static int schizo_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
119 int where, int size, u32 *value)
120{
121 struct pci_pbm_info *pbm = bus_dev->sysdata;
122 unsigned char bus = bus_dev->number;
123 u32 *addr;
124 u16 tmp16;
125 u8 tmp8;
126
127 switch (size) {
128 case 1:
129 *value = 0xff;
130 break;
131 case 2:
132 *value = 0xffff;
133 break;
134 case 4:
135 *value = 0xffffffff;
136 break;
137 }
138
139 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
140 if (!addr)
141 return PCIBIOS_SUCCESSFUL;
142
143 if (schizo_out_of_range(pbm, bus, devfn))
144 return PCIBIOS_SUCCESSFUL;
145 switch (size) {
146 case 1:
147 pci_config_read8((u8 *)addr, &tmp8);
148 *value = tmp8;
149 break;
150
151 case 2:
152 if (where & 0x01) {
153 printk("pci_read_config_word: misaligned reg [%x]\n",
154 where);
155 return PCIBIOS_SUCCESSFUL;
156 }
157 pci_config_read16((u16 *)addr, &tmp16);
158 *value = tmp16;
159 break;
160
161 case 4:
162 if (where & 0x03) {
163 printk("pci_read_config_dword: misaligned reg [%x]\n",
164 where);
165 return PCIBIOS_SUCCESSFUL;
166 }
167 pci_config_read32(addr, value);
168 break;
169 }
170 return PCIBIOS_SUCCESSFUL;
171}
172
173static int schizo_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
174 int where, int size, u32 value)
175{
176 struct pci_pbm_info *pbm = bus_dev->sysdata;
177 unsigned char bus = bus_dev->number;
178 u32 *addr;
179
180 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
181 if (!addr)
182 return PCIBIOS_SUCCESSFUL;
183
184 if (schizo_out_of_range(pbm, bus, devfn))
185 return PCIBIOS_SUCCESSFUL;
186
187 switch (size) {
188 case 1:
189 pci_config_write8((u8 *)addr, value);
190 break;
191
192 case 2:
193 if (where & 0x01) {
194 printk("pci_write_config_word: misaligned reg [%x]\n",
195 where);
196 return PCIBIOS_SUCCESSFUL;
197 }
198 pci_config_write16((u16 *)addr, value);
199 break;
200
201 case 4:
202 if (where & 0x03) {
203 printk("pci_write_config_dword: misaligned reg [%x]\n",
204 where);
205 return PCIBIOS_SUCCESSFUL;
206 }
207
208 pci_config_write32(addr, value);
209 }
210 return PCIBIOS_SUCCESSFUL;
211}
212
213static struct pci_ops schizo_ops = {
214 .read = schizo_read_pci_cfg,
215 .write = schizo_write_pci_cfg,
216};
217
218/* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
219 * imap/iclr registers are per-PBM.
220 */
221#define SCHIZO_IMAP_BASE 0x1000UL
222#define SCHIZO_ICLR_BASE 0x1400UL
223
224static unsigned long schizo_imap_offset(unsigned long ino)
225{
226 return SCHIZO_IMAP_BASE + (ino * 8UL);
227}
228
229static unsigned long schizo_iclr_offset(unsigned long ino)
230{
231 return SCHIZO_ICLR_BASE + (ino * 8UL);
232}
233
234/* PCI SCHIZO INO number to Sparc PIL level. This table only matters for
235 * INOs which will not have an associated PCI device struct, ie. onboard
236 * EBUS devices and PCI controller internal error interrupts.
237 */
238static unsigned char schizo_pil_table[] = {
239/*0x00*/0, 0, 0, 0, /* PCI slot 0 Int A, B, C, D */
240/*0x04*/0, 0, 0, 0, /* PCI slot 1 Int A, B, C, D */
241/*0x08*/0, 0, 0, 0, /* PCI slot 2 Int A, B, C, D */
242/*0x0c*/0, 0, 0, 0, /* PCI slot 3 Int A, B, C, D */
243/*0x10*/0, 0, 0, 0, /* PCI slot 4 Int A, B, C, D */
244/*0x14*/0, 0, 0, 0, /* PCI slot 5 Int A, B, C, D */
245/*0x18*/4, /* SCSI */
246/*0x19*/4, /* second SCSI */
247/*0x1a*/0, /* UNKNOWN */
248/*0x1b*/0, /* UNKNOWN */
249/*0x1c*/8, /* Parallel */
250/*0x1d*/5, /* Ethernet */
251/*0x1e*/8, /* Firewire-1394 */
252/*0x1f*/9, /* USB */
253/*0x20*/13, /* Audio Record */
254/*0x21*/14, /* Audio Playback */
255/*0x22*/12, /* Serial */
256/*0x23*/4, /* EBUS I2C */
257/*0x24*/10, /* RTC Clock */
258/*0x25*/11, /* Floppy */
259/*0x26*/0, /* UNKNOWN */
260/*0x27*/0, /* UNKNOWN */
261/*0x28*/0, /* UNKNOWN */
262/*0x29*/0, /* UNKNOWN */
263/*0x2a*/10, /* UPA 1 */
264/*0x2b*/10, /* UPA 2 */
265/*0x2c*/0, /* UNKNOWN */
266/*0x2d*/0, /* UNKNOWN */
267/*0x2e*/0, /* UNKNOWN */
268/*0x2f*/0, /* UNKNOWN */
269/*0x30*/15, /* Uncorrectable ECC */
270/*0x31*/15, /* Correctable ECC */
271/*0x32*/15, /* PCI Bus A Error */
272/*0x33*/15, /* PCI Bus B Error */
273/*0x34*/15, /* Safari Bus Error */
274/*0x35*/0, /* Reserved */
275/*0x36*/0, /* Reserved */
276/*0x37*/0, /* Reserved */
277/*0x38*/0, /* Reserved for NewLink */
278/*0x39*/0, /* Reserved for NewLink */
279/*0x3a*/0, /* Reserved for NewLink */
280/*0x3b*/0, /* Reserved for NewLink */
281/*0x3c*/0, /* Reserved for NewLink */
282/*0x3d*/0, /* Reserved for NewLink */
283/*0x3e*/0, /* Reserved for NewLink */
284/*0x3f*/0, /* Reserved for NewLink */
285};
286
287static int __init schizo_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
288{
289 int ret;
290
291 if (pdev &&
292 pdev->vendor == PCI_VENDOR_ID_SUN &&
293 pdev->device == PCI_DEVICE_ID_SUN_RIO_USB)
294 return 9;
295
296 ret = schizo_pil_table[ino];
297 if (ret == 0 && pdev == NULL) {
298 ret = 4;
299 } else if (ret == 0) {
300 switch ((pdev->class >> 16) & 0xff) {
301 case PCI_BASE_CLASS_STORAGE:
302 ret = 4;
303 break;
304
305 case PCI_BASE_CLASS_NETWORK:
306 ret = 6;
307 break;
308
309 case PCI_BASE_CLASS_DISPLAY:
310 ret = 9;
311 break;
312
313 case PCI_BASE_CLASS_MULTIMEDIA:
314 case PCI_BASE_CLASS_MEMORY:
315 case PCI_BASE_CLASS_BRIDGE:
316 case PCI_BASE_CLASS_SERIAL:
317 ret = 10;
318 break;
319
320 default:
321 ret = 4;
322 break;
323 };
324 }
325
326 return ret;
327}
328
329static unsigned int schizo_irq_build(struct pci_pbm_info *pbm,
330 struct pci_dev *pdev,
331 unsigned int ino)
332{
333 struct ino_bucket *bucket;
334 unsigned long imap, iclr;
335 unsigned long imap_off, iclr_off;
336 int pil, ign_fixup;
337
338 ino &= PCI_IRQ_INO;
339 imap_off = schizo_imap_offset(ino);
340
341 /* Now build the IRQ bucket. */
342 pil = schizo_ino_to_pil(pdev, ino);
343
344 if (PIL_RESERVED(pil))
345 BUG();
346
347 imap = pbm->pbm_regs + imap_off;
348 imap += 4;
349
350 iclr_off = schizo_iclr_offset(ino);
351 iclr = pbm->pbm_regs + iclr_off;
352 iclr += 4;
353
354 /* On Schizo, no inofixup occurs. This is because each
355 * INO has it's own IMAP register. On Psycho and Sabre
356 * there is only one IMAP register for each PCI slot even
357 * though four different INOs can be generated by each
358 * PCI slot.
359 *
360 * But, for JBUS variants (essentially, Tomatillo), we have
361 * to fixup the lowest bit of the interrupt group number.
362 */
363 ign_fixup = 0;
364 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
365 if (pbm->portid & 1)
366 ign_fixup = (1 << 6);
367 }
368
369 bucket = __bucket(build_irq(pil, ign_fixup, iclr, imap));
370 bucket->flags |= IBF_PCI;
371
372 return __irq(bucket);
373}
374
375/* SCHIZO error handling support. */
376enum schizo_error_type {
377 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
378};
379
380static DEFINE_SPINLOCK(stc_buf_lock);
381static unsigned long stc_error_buf[128];
382static unsigned long stc_tag_buf[16];
383static unsigned long stc_line_buf[16];
384
385#define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
386#define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
387#define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
388#define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
389#define SCHIZO_SERR_INO 0x34 /* Safari interface error */
390
391struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino)
392{
393 ino &= IMAP_INO;
394 if (p->pbm_A.ino_bitmap & (1UL << ino))
395 return &p->pbm_A;
396 if (p->pbm_B.ino_bitmap & (1UL << ino))
397 return &p->pbm_B;
398
399 printk("PCI%d: No ino_bitmap entry for ino[%x], bitmaps "
400 "PBM_A[%016lx] PBM_B[%016lx]",
401 p->index, ino,
402 p->pbm_A.ino_bitmap,
403 p->pbm_B.ino_bitmap);
404 printk("PCI%d: Using PBM_A, report this problem immediately.\n",
405 p->index);
406
407 return &p->pbm_A;
408}
409
410static void schizo_clear_other_err_intr(struct pci_controller_info *p, int irq)
411{
412 struct pci_pbm_info *pbm;
413 struct ino_bucket *bucket;
414 unsigned long iclr;
415
416 /* Do not clear the interrupt for the other PCI bus.
417 *
418 * This "ACK both PBM IRQs" only needs to be performed
419 * for chip-wide error interrupts.
420 */
421 if ((irq & IMAP_INO) == SCHIZO_PCIERR_A_INO ||
422 (irq & IMAP_INO) == SCHIZO_PCIERR_B_INO)
423 return;
424
425 pbm = pbm_for_ino(p, irq);
426 if (pbm == &p->pbm_A)
427 pbm = &p->pbm_B;
428 else
429 pbm = &p->pbm_A;
430
431 irq = schizo_irq_build(pbm, NULL,
432 (pbm->portid << 6) | (irq & IMAP_INO));
433 bucket = __bucket(irq);
434 iclr = bucket->iclr;
435
436 upa_writel(ICLR_IDLE, iclr);
437}
438
439#define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
440#define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
441#define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
442
443#define SCHIZO_STCERR_WRITE 0x2UL
444#define SCHIZO_STCERR_READ 0x1UL
445
446#define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
447#define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
448#define SCHIZO_STCTAG_VALID 0x8000000000000000UL
449#define SCHIZO_STCTAG_READ 0x4000000000000000UL
450
451#define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
452#define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
453#define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
454#define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
455#define SCHIZO_STCLINE_VALID 0x0000000000600000UL
456#define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
457
458static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
459 enum schizo_error_type type)
460{
461 struct pci_strbuf *strbuf = &pbm->stc;
462 unsigned long regbase = pbm->pbm_regs;
463 unsigned long err_base, tag_base, line_base;
464 u64 control;
465 int i;
466
467 err_base = regbase + SCHIZO_STC_ERR;
468 tag_base = regbase + SCHIZO_STC_TAG;
469 line_base = regbase + SCHIZO_STC_LINE;
470
471 spin_lock(&stc_buf_lock);
472
473 /* This is __REALLY__ dangerous. When we put the
474 * streaming buffer into diagnostic mode to probe
475 * it's tags and error status, we _must_ clear all
476 * of the line tag valid bits before re-enabling
477 * the streaming buffer. If any dirty data lives
478 * in the STC when we do this, we will end up
479 * invalidating it before it has a chance to reach
480 * main memory.
481 */
482 control = schizo_read(strbuf->strbuf_control);
483 schizo_write(strbuf->strbuf_control,
484 (control | SCHIZO_STRBUF_CTRL_DENAB));
485 for (i = 0; i < 128; i++) {
486 unsigned long val;
487
488 val = schizo_read(err_base + (i * 8UL));
489 schizo_write(err_base + (i * 8UL), 0UL);
490 stc_error_buf[i] = val;
491 }
492 for (i = 0; i < 16; i++) {
493 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL));
494 stc_line_buf[i] = schizo_read(line_base + (i * 8UL));
495 schizo_write(tag_base + (i * 8UL), 0UL);
496 schizo_write(line_base + (i * 8UL), 0UL);
497 }
498
499 /* OK, state is logged, exit diagnostic mode. */
500 schizo_write(strbuf->strbuf_control, control);
501
502 for (i = 0; i < 16; i++) {
503 int j, saw_error, first, last;
504
505 saw_error = 0;
506 first = i * 8;
507 last = first + 8;
508 for (j = first; j < last; j++) {
509 unsigned long errval = stc_error_buf[j];
510 if (errval != 0) {
511 saw_error++;
512 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
513 pbm->name,
514 j,
515 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
516 (errval & SCHIZO_STCERR_READ) ? 1 : 0);
517 }
518 }
519 if (saw_error != 0) {
520 unsigned long tagval = stc_tag_buf[i];
521 unsigned long lineval = stc_line_buf[i];
522 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
523 pbm->name,
524 i,
525 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
526 (tagval & SCHIZO_STCTAG_VPN),
527 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
528 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
529
530 /* XXX Should spit out per-bank error information... -DaveM */
531 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
532 "V(%d)FOFN(%d)]\n",
533 pbm->name,
534 i,
535 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
536 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
537 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
538 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
539 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
540 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
541 }
542 }
543
544 spin_unlock(&stc_buf_lock);
545}
546
547/* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
548 * controller level errors.
549 */
550
551#define SCHIZO_IOMMU_TAG 0xa580UL
552#define SCHIZO_IOMMU_DATA 0xa600UL
553
554#define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
555#define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
556#define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
557#define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
558#define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
559#define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
560#define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
561
562#define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
563#define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
564#define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
565
566static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
567 enum schizo_error_type type)
568{
569 struct pci_iommu *iommu = pbm->iommu;
570 unsigned long iommu_tag[16];
571 unsigned long iommu_data[16];
572 unsigned long flags;
573 u64 control;
574 int i;
575
576 spin_lock_irqsave(&iommu->lock, flags);
577 control = schizo_read(iommu->iommu_control);
578 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
579 unsigned long base;
580 char *type_string;
581
582 /* Clear the error encountered bit. */
583 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
584 schizo_write(iommu->iommu_control, control);
585
586 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
587 case 0:
588 type_string = "Protection Error";
589 break;
590 case 1:
591 type_string = "Invalid Error";
592 break;
593 case 2:
594 type_string = "TimeOut Error";
595 break;
596 case 3:
597 default:
598 type_string = "ECC Error";
599 break;
600 };
601 printk("%s: IOMMU Error, type[%s]\n",
602 pbm->name, type_string);
603
604 /* Put the IOMMU into diagnostic mode and probe
605 * it's TLB for entries with error status.
606 *
607 * It is very possible for another DVMA to occur
608 * while we do this probe, and corrupt the system
609 * further. But we are so screwed at this point
610 * that we are likely to crash hard anyways, so
611 * get as much diagnostic information to the
612 * console as we can.
613 */
614 schizo_write(iommu->iommu_control,
615 control | SCHIZO_IOMMU_CTRL_DENAB);
616
617 base = pbm->pbm_regs;
618
619 for (i = 0; i < 16; i++) {
620 iommu_tag[i] =
621 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL));
622 iommu_data[i] =
623 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL));
624
625 /* Now clear out the entry. */
626 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0);
627 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0);
628 }
629
630 /* Leave diagnostic mode. */
631 schizo_write(iommu->iommu_control, control);
632
633 for (i = 0; i < 16; i++) {
634 unsigned long tag, data;
635
636 tag = iommu_tag[i];
637 if (!(tag & SCHIZO_IOMMU_TAG_ERR))
638 continue;
639
640 data = iommu_data[i];
641 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
642 case 0:
643 type_string = "Protection Error";
644 break;
645 case 1:
646 type_string = "Invalid Error";
647 break;
648 case 2:
649 type_string = "TimeOut Error";
650 break;
651 case 3:
652 default:
653 type_string = "ECC Error";
654 break;
655 };
656 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
657 "sz(%dK) vpg(%08lx)]\n",
658 pbm->name, i, type_string,
659 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
660 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
661 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
662 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
663 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
664 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
665 pbm->name, i,
666 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
667 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
668 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
669 }
670 }
671 if (pbm->stc.strbuf_enabled)
672 __schizo_check_stc_error_pbm(pbm, type);
673 spin_unlock_irqrestore(&iommu->lock, flags);
674}
675
676static void schizo_check_iommu_error(struct pci_controller_info *p,
677 enum schizo_error_type type)
678{
679 schizo_check_iommu_error_pbm(&p->pbm_A, type);
680 schizo_check_iommu_error_pbm(&p->pbm_B, type);
681}
682
683/* Uncorrectable ECC error status gathering. */
684#define SCHIZO_UE_AFSR 0x10030UL
685#define SCHIZO_UE_AFAR 0x10038UL
686
687#define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
688#define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
689#define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
690#define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
691#define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
692#define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
693#define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
694#define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
695#define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
696#define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
697#define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
698#define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
699#define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
700#define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
701
702static irqreturn_t schizo_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
703{
704 struct pci_controller_info *p = dev_id;
705 unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFSR;
706 unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFAR;
707 unsigned long afsr, afar, error_bits;
708 int reported, limit;
709
710 /* Latch uncorrectable error status. */
711 afar = schizo_read(afar_reg);
712
713 /* If either of the error pending bits are set in the
714 * AFSR, the error status is being actively updated by
715 * the hardware and we must re-read to get a clean value.
716 */
717 limit = 1000;
718 do {
719 afsr = schizo_read(afsr_reg);
720 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
721
722 /* Clear the primary/secondary error status bits. */
723 error_bits = afsr &
724 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
725 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
726 if (!error_bits)
727 return IRQ_NONE;
728 schizo_write(afsr_reg, error_bits);
729
730 /* Log the error. */
731 printk("PCI%d: Uncorrectable Error, primary error type[%s]\n",
732 p->index,
733 (((error_bits & SCHIZO_UEAFSR_PPIO) ?
734 "PIO" :
735 ((error_bits & SCHIZO_UEAFSR_PDRD) ?
736 "DMA Read" :
737 ((error_bits & SCHIZO_UEAFSR_PDWR) ?
738 "DMA Write" : "???")))));
739 printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
740 p->index,
741 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
742 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
743 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
744 printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
745 p->index,
746 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
747 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
748 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
749 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
750 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
751 printk("PCI%d: UE AFAR [%016lx]\n", p->index, afar);
752 printk("PCI%d: UE Secondary errors [", p->index);
753 reported = 0;
754 if (afsr & SCHIZO_UEAFSR_SPIO) {
755 reported++;
756 printk("(PIO)");
757 }
758 if (afsr & SCHIZO_UEAFSR_SDMA) {
759 reported++;
760 printk("(DMA)");
761 }
762 if (!reported)
763 printk("(none)");
764 printk("]\n");
765
766 /* Interrogate IOMMU for error status. */
767 schizo_check_iommu_error(p, UE_ERR);
768
769 schizo_clear_other_err_intr(p, irq);
770
771 return IRQ_HANDLED;
772}
773
774#define SCHIZO_CE_AFSR 0x10040UL
775#define SCHIZO_CE_AFAR 0x10048UL
776
777#define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
778#define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
779#define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
780#define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
781#define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
782#define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
783#define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
784#define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
785#define SCHIZO_CEAFSR_AID 0x000000001f000000UL
786#define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
787#define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
788#define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
789#define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
790#define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
791
792static irqreturn_t schizo_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
793{
794 struct pci_controller_info *p = dev_id;
795 unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFSR;
796 unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFAR;
797 unsigned long afsr, afar, error_bits;
798 int reported, limit;
799
800 /* Latch error status. */
801 afar = schizo_read(afar_reg);
802
803 /* If either of the error pending bits are set in the
804 * AFSR, the error status is being actively updated by
805 * the hardware and we must re-read to get a clean value.
806 */
807 limit = 1000;
808 do {
809 afsr = schizo_read(afsr_reg);
810 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
811
812 /* Clear primary/secondary error status bits. */
813 error_bits = afsr &
814 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
815 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
816 if (!error_bits)
817 return IRQ_NONE;
818 schizo_write(afsr_reg, error_bits);
819
820 /* Log the error. */
821 printk("PCI%d: Correctable Error, primary error type[%s]\n",
822 p->index,
823 (((error_bits & SCHIZO_CEAFSR_PPIO) ?
824 "PIO" :
825 ((error_bits & SCHIZO_CEAFSR_PDRD) ?
826 "DMA Read" :
827 ((error_bits & SCHIZO_CEAFSR_PDWR) ?
828 "DMA Write" : "???")))));
829
830 /* XXX Use syndrome and afar to print out module string just like
831 * XXX UDB CE trap handler does... -DaveM
832 */
833 printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
834 p->index,
835 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
836 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
837 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
838 printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
839 p->index,
840 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
841 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
842 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
843 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
844 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
845 printk("PCI%d: CE AFAR [%016lx]\n", p->index, afar);
846 printk("PCI%d: CE Secondary errors [", p->index);
847 reported = 0;
848 if (afsr & SCHIZO_CEAFSR_SPIO) {
849 reported++;
850 printk("(PIO)");
851 }
852 if (afsr & SCHIZO_CEAFSR_SDMA) {
853 reported++;
854 printk("(DMA)");
855 }
856 if (!reported)
857 printk("(none)");
858 printk("]\n");
859
860 schizo_clear_other_err_intr(p, irq);
861
862 return IRQ_HANDLED;
863}
864
865#define SCHIZO_PCI_AFSR 0x2010UL
866#define SCHIZO_PCI_AFAR 0x2018UL
867
868#define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
869#define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
870#define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
871#define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
872#define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
873#define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
874#define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
875#define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
876#define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
877#define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
878#define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
879#define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
880#define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
881#define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
882#define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
883#define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
884#define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
885
886#define SCHIZO_PCI_CTRL (0x2000UL)
887#define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
888#define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
889#define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
890#define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
891#define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
892#define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
893#define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
894#define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
895#define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
896#define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
897#define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
898#define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
899#define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
900#define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
901#define SCHIZO_PCICTRL_PTO_SHIFT 24UL
902#define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
903#define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
904#define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
905#define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
906#define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
907#define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
908#define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
909#define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
910#define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
911#define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
912#define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
913
914static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
915{
916 unsigned long csr_reg, csr, csr_error_bits;
917 irqreturn_t ret = IRQ_NONE;
918 u16 stat;
919
920 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
921 csr = schizo_read(csr_reg);
922 csr_error_bits =
923 csr & (SCHIZO_PCICTRL_BUS_UNUS |
924 SCHIZO_PCICTRL_TTO_ERR |
925 SCHIZO_PCICTRL_RTRY_ERR |
926 SCHIZO_PCICTRL_DTO_ERR |
927 SCHIZO_PCICTRL_SBH_ERR |
928 SCHIZO_PCICTRL_SERR);
929 if (csr_error_bits) {
930 /* Clear the errors. */
931 schizo_write(csr_reg, csr);
932
933 /* Log 'em. */
934 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
935 printk("%s: Bus unusable error asserted.\n",
936 pbm->name);
937 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
938 printk("%s: PCI TRDY# timeout error asserted.\n",
939 pbm->name);
940 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
941 printk("%s: PCI excessive retry error asserted.\n",
942 pbm->name);
943 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
944 printk("%s: PCI discard timeout error asserted.\n",
945 pbm->name);
946 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
947 printk("%s: PCI streaming byte hole error asserted.\n",
948 pbm->name);
949 if (csr_error_bits & SCHIZO_PCICTRL_SERR)
950 printk("%s: PCI SERR signal asserted.\n",
951 pbm->name);
952 ret = IRQ_HANDLED;
953 }
954 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
955 if (stat & (PCI_STATUS_PARITY |
956 PCI_STATUS_SIG_TARGET_ABORT |
957 PCI_STATUS_REC_TARGET_ABORT |
958 PCI_STATUS_REC_MASTER_ABORT |
959 PCI_STATUS_SIG_SYSTEM_ERROR)) {
960 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
961 pbm->name, stat);
962 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
963 ret = IRQ_HANDLED;
964 }
965 return ret;
966}
967
968static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
969{
970 struct pci_pbm_info *pbm = dev_id;
971 struct pci_controller_info *p = pbm->parent;
972 unsigned long afsr_reg, afar_reg, base;
973 unsigned long afsr, afar, error_bits;
974 int reported;
975
976 base = pbm->pbm_regs;
977
978 afsr_reg = base + SCHIZO_PCI_AFSR;
979 afar_reg = base + SCHIZO_PCI_AFAR;
980
981 /* Latch error status. */
982 afar = schizo_read(afar_reg);
983 afsr = schizo_read(afsr_reg);
984
985 /* Clear primary/secondary error status bits. */
986 error_bits = afsr &
987 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
988 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
989 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
990 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
991 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
992 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
993 if (!error_bits)
994 return schizo_pcierr_intr_other(pbm);
995 schizo_write(afsr_reg, error_bits);
996
997 /* Log the error. */
998 printk("%s: PCI Error, primary error type[%s]\n",
999 pbm->name,
1000 (((error_bits & SCHIZO_PCIAFSR_PMA) ?
1001 "Master Abort" :
1002 ((error_bits & SCHIZO_PCIAFSR_PTA) ?
1003 "Target Abort" :
1004 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
1005 "Excessive Retries" :
1006 ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
1007 "Parity Error" :
1008 ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
1009 "Timeout" :
1010 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
1011 "Bus Unusable" : "???"))))))));
1012 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
1013 pbm->name,
1014 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
1015 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
1016 ((afsr & SCHIZO_PCIAFSR_CFG) ?
1017 "Config" :
1018 ((afsr & SCHIZO_PCIAFSR_MEM) ?
1019 "Memory" :
1020 ((afsr & SCHIZO_PCIAFSR_IO) ?
1021 "I/O" : "???"))));
1022 printk("%s: PCI AFAR [%016lx]\n",
1023 pbm->name, afar);
1024 printk("%s: PCI Secondary errors [",
1025 pbm->name);
1026 reported = 0;
1027 if (afsr & SCHIZO_PCIAFSR_SMA) {
1028 reported++;
1029 printk("(Master Abort)");
1030 }
1031 if (afsr & SCHIZO_PCIAFSR_STA) {
1032 reported++;
1033 printk("(Target Abort)");
1034 }
1035 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
1036 reported++;
1037 printk("(Excessive Retries)");
1038 }
1039 if (afsr & SCHIZO_PCIAFSR_SPERR) {
1040 reported++;
1041 printk("(Parity Error)");
1042 }
1043 if (afsr & SCHIZO_PCIAFSR_STTO) {
1044 reported++;
1045 printk("(Timeout)");
1046 }
1047 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
1048 reported++;
1049 printk("(Bus Unusable)");
1050 }
1051 if (!reported)
1052 printk("(none)");
1053 printk("]\n");
1054
1055 /* For the error types shown, scan PBM's PCI bus for devices
1056 * which have logged that error type.
1057 */
1058
1059 /* If we see a Target Abort, this could be the result of an
1060 * IOMMU translation error of some sort. It is extremely
1061 * useful to log this information as usually it indicates
1062 * a bug in the IOMMU support code or a PCI device driver.
1063 */
1064 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
1065 schizo_check_iommu_error(p, PCI_ERR);
1066 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
1067 }
1068 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
1069 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
1070
1071 /* For excessive retries, PSYCHO/PBM will abort the device
1072 * and there is no way to specifically check for excessive
1073 * retries in the config space status registers. So what
1074 * we hope is that we'll catch it via the master/target
1075 * abort events.
1076 */
1077
1078 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
1079 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
1080
1081 schizo_clear_other_err_intr(p, irq);
1082
1083 return IRQ_HANDLED;
1084}
1085
1086#define SCHIZO_SAFARI_ERRLOG 0x10018UL
1087
1088#define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
1089
1090#define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
1091#define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
1092#define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
1093#define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
1094#define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
1095#define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
1096#define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
1097#define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
1098#define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
1099#define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
1100#define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
1101#define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
1102#define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
1103#define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
1104#define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
1105#define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
1106#define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
1107#define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
1108#define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
1109#define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
1110#define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
1111#define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
1112#define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
1113#define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
1114#define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
1115#define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
1116#define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
1117#define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
1118#define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
1119#define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
1120#define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
1121
1122/* We only expect UNMAP errors here. The rest of the Safari errors
1123 * are marked fatal and thus cause a system reset.
1124 */
1125static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id, struct pt_regs *regs)
1126{
1127 struct pci_controller_info *p = dev_id;
1128 u64 errlog;
1129
1130 errlog = schizo_read(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG);
1131 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG,
1132 errlog & ~(SAFARI_ERRLOG_ERROUT));
1133
1134 if (!(errlog & BUS_ERROR_UNMAP)) {
1135 printk("PCI%d: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
1136 p->index, errlog);
1137
1138 schizo_clear_other_err_intr(p, irq);
1139 return IRQ_HANDLED;
1140 }
1141
1142 printk("PCI%d: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
1143 p->index);
1144 schizo_check_iommu_error(p, SAFARI_ERR);
1145
1146 schizo_clear_other_err_intr(p, irq);
1147 return IRQ_HANDLED;
1148}
1149
1150/* Nearly identical to PSYCHO equivalents... */
1151#define SCHIZO_ECC_CTRL 0x10020UL
1152#define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
1153#define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
1154#define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
1155
1156#define SCHIZO_SAFARI_ERRCTRL 0x10008UL
1157#define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
1158#define SCHIZO_SAFARI_IRQCTRL 0x10010UL
1159#define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
1160
1161/* How the Tomatillo IRQs are routed around is pure guesswork here.
1162 *
1163 * All the Tomatillo devices I see in prtconf dumps seem to have only
1164 * a single PCI bus unit attached to it. It would seem they are seperate
1165 * devices because their PortID (ie. JBUS ID) values are all different
1166 * and thus the registers are mapped to totally different locations.
1167 *
1168 * However, two Tomatillo's look "similar" in that the only difference
1169 * in their PortID is the lowest bit.
1170 *
1171 * So if we were to ignore this lower bit, it certainly looks like two
1172 * PCI bus units of the same Tomatillo. I still have not really
1173 * figured this out...
1174 */
1175static void __init tomatillo_register_error_handlers(struct pci_controller_info *p)
1176{
1177 struct pci_pbm_info *pbm;
1178 unsigned int irq;
1179 struct ino_bucket *bucket;
1180 u64 tmp, err_mask, err_no_mask;
1181
1182 /* Build IRQs and register handlers. */
1183 pbm = pbm_for_ino(p, SCHIZO_UE_INO);
1184 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO);
1185 if (request_irq(irq, schizo_ue_intr,
1186 SA_SHIRQ, "TOMATILLO UE", p) < 0) {
1187 prom_printf("%s: Cannot register UE interrupt.\n",
1188 pbm->name);
1189 prom_halt();
1190 }
1191 bucket = __bucket(irq);
1192 tmp = upa_readl(bucket->imap);
1193 upa_writel(tmp, (pbm->pbm_regs +
1194 schizo_imap_offset(SCHIZO_UE_INO) + 4));
1195
1196 pbm = pbm_for_ino(p, SCHIZO_CE_INO);
1197 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO);
1198 if (request_irq(irq, schizo_ce_intr,
1199 SA_SHIRQ, "TOMATILLO CE", p) < 0) {
1200 prom_printf("%s: Cannot register CE interrupt.\n",
1201 pbm->name);
1202 prom_halt();
1203 }
1204 bucket = __bucket(irq);
1205 tmp = upa_readl(bucket->imap);
1206 upa_writel(tmp, (pbm->pbm_regs +
1207 schizo_imap_offset(SCHIZO_CE_INO) + 4));
1208
1209 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
1210 irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) |
1211 SCHIZO_PCIERR_A_INO));
1212 if (request_irq(irq, schizo_pcierr_intr,
1213 SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) {
1214 prom_printf("%s: Cannot register PBM A PciERR interrupt.\n",
1215 pbm->name);
1216 prom_halt();
1217 }
1218 bucket = __bucket(irq);
1219 tmp = upa_readl(bucket->imap);
1220 upa_writel(tmp, (pbm->pbm_regs +
1221 schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
1222
1223 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
1224 irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) |
1225 SCHIZO_PCIERR_B_INO));
1226 if (request_irq(irq, schizo_pcierr_intr,
1227 SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) {
1228 prom_printf("%s: Cannot register PBM B PciERR interrupt.\n",
1229 pbm->name);
1230 prom_halt();
1231 }
1232 bucket = __bucket(irq);
1233 tmp = upa_readl(bucket->imap);
1234 upa_writel(tmp, (pbm->pbm_regs +
1235 schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
1236
1237 pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
1238 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO);
1239 if (request_irq(irq, schizo_safarierr_intr,
1240 SA_SHIRQ, "TOMATILLO SERR", p) < 0) {
1241 prom_printf("%s: Cannot register SafariERR interrupt.\n",
1242 pbm->name);
1243 prom_halt();
1244 }
1245 bucket = __bucket(irq);
1246 tmp = upa_readl(bucket->imap);
1247 upa_writel(tmp, (pbm->pbm_regs +
1248 schizo_imap_offset(SCHIZO_SERR_INO) + 4));
1249
1250 /* Enable UE and CE interrupts for controller. */
1251 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL,
1252 (SCHIZO_ECCCTRL_EE |
1253 SCHIZO_ECCCTRL_UE |
1254 SCHIZO_ECCCTRL_CE));
1255
1256 schizo_write(p->pbm_B.controller_regs + SCHIZO_ECC_CTRL,
1257 (SCHIZO_ECCCTRL_EE |
1258 SCHIZO_ECCCTRL_UE |
1259 SCHIZO_ECCCTRL_CE));
1260
1261 /* Enable PCI Error interrupts and clear error
1262 * bits.
1263 */
1264 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1265 SCHIZO_PCICTRL_TTO_ERR |
1266 SCHIZO_PCICTRL_RTRY_ERR |
1267 SCHIZO_PCICTRL_SERR |
1268 SCHIZO_PCICTRL_EEN);
1269
1270 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
1271
1272 tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL);
1273 tmp |= err_mask;
1274 tmp &= ~err_no_mask;
1275 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1276
1277 tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL);
1278 tmp |= err_mask;
1279 tmp &= ~err_no_mask;
1280 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1281
1282 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1283 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1284 SCHIZO_PCIAFSR_PTTO |
1285 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1286 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1287 SCHIZO_PCIAFSR_STTO);
1288
1289 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1290 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1291
1292 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
1293 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
1294 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
1295 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
1296 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
1297 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
1298 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
1299 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
1300 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
1301
1302 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1303 (SCHIZO_SAFERRCTRL_EN | err_mask));
1304 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1305 (SCHIZO_SAFERRCTRL_EN | err_mask));
1306
1307 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1308 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1309 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1310 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1311}
1312
1313static void __init schizo_register_error_handlers(struct pci_controller_info *p)
1314{
1315 struct pci_pbm_info *pbm;
1316 unsigned int irq;
1317 struct ino_bucket *bucket;
1318 u64 tmp, err_mask, err_no_mask;
1319
1320 /* Build IRQs and register handlers. */
1321 pbm = pbm_for_ino(p, SCHIZO_UE_INO);
1322 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO);
1323 if (request_irq(irq, schizo_ue_intr,
1324 SA_SHIRQ, "SCHIZO UE", p) < 0) {
1325 prom_printf("%s: Cannot register UE interrupt.\n",
1326 pbm->name);
1327 prom_halt();
1328 }
1329 bucket = __bucket(irq);
1330 tmp = upa_readl(bucket->imap);
1331 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_UE_INO) + 4));
1332
1333 pbm = pbm_for_ino(p, SCHIZO_CE_INO);
1334 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO);
1335 if (request_irq(irq, schizo_ce_intr,
1336 SA_SHIRQ, "SCHIZO CE", p) < 0) {
1337 prom_printf("%s: Cannot register CE interrupt.\n",
1338 pbm->name);
1339 prom_halt();
1340 }
1341 bucket = __bucket(irq);
1342 tmp = upa_readl(bucket->imap);
1343 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_CE_INO) + 4));
1344
1345 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
1346 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO);
1347 if (request_irq(irq, schizo_pcierr_intr,
1348 SA_SHIRQ, "SCHIZO PCIERR", pbm) < 0) {
1349 prom_printf("%s: Cannot register PBM A PciERR interrupt.\n",
1350 pbm->name);
1351 prom_halt();
1352 }
1353 bucket = __bucket(irq);
1354 tmp = upa_readl(bucket->imap);
1355 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
1356
1357 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
1358 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO);
1359 if (request_irq(irq, schizo_pcierr_intr,
1360 SA_SHIRQ, "SCHIZO PCIERR", &p->pbm_B) < 0) {
1361 prom_printf("%s: Cannot register PBM B PciERR interrupt.\n",
1362 pbm->name);
1363 prom_halt();
1364 }
1365 bucket = __bucket(irq);
1366 tmp = upa_readl(bucket->imap);
1367 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
1368
1369 pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
1370 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO);
1371 if (request_irq(irq, schizo_safarierr_intr,
1372 SA_SHIRQ, "SCHIZO SERR", p) < 0) {
1373 prom_printf("%s: Cannot register SafariERR interrupt.\n",
1374 pbm->name);
1375 prom_halt();
1376 }
1377 bucket = __bucket(irq);
1378 tmp = upa_readl(bucket->imap);
1379 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_SERR_INO) + 4));
1380
1381 /* Enable UE and CE interrupts for controller. */
1382 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL,
1383 (SCHIZO_ECCCTRL_EE |
1384 SCHIZO_ECCCTRL_UE |
1385 SCHIZO_ECCCTRL_CE));
1386
1387 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1388 SCHIZO_PCICTRL_ESLCK |
1389 SCHIZO_PCICTRL_TTO_ERR |
1390 SCHIZO_PCICTRL_RTRY_ERR |
1391 SCHIZO_PCICTRL_SBH_ERR |
1392 SCHIZO_PCICTRL_SERR |
1393 SCHIZO_PCICTRL_EEN);
1394
1395 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1396 SCHIZO_PCICTRL_SBH_INT);
1397
1398 /* Enable PCI Error interrupts and clear error
1399 * bits for each PBM.
1400 */
1401 tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL);
1402 tmp |= err_mask;
1403 tmp &= ~err_no_mask;
1404 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1405
1406 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR,
1407 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1408 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1409 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1410 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1411 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1412 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1413
1414 tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL);
1415 tmp |= err_mask;
1416 tmp &= ~err_no_mask;
1417 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1418
1419 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR,
1420 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1421 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1422 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1423 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1424 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1425 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1426
1427 /* Make all Safari error conditions fatal except unmapped
1428 * errors which we make generate interrupts.
1429 */
1430 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1431 BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1432 BUS_ERROR_BADMC |
1433 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1434 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1435 BUS_ERROR_CIQTO |
1436 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1437 BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1438 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1439 BUS_ERROR_ILL);
1440#if 1
1441 /* XXX Something wrong with some Excalibur systems
1442 * XXX Sun is shipping. The behavior on a 2-cpu
1443 * XXX machine is that both CPU1 parity error bits
1444 * XXX are set and are immediately set again when
1445 * XXX their error status bits are cleared. Just
1446 * XXX ignore them for now. -DaveM
1447 */
1448 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1449 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1450#endif
1451
1452 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1453 (SCHIZO_SAFERRCTRL_EN | err_mask));
1454
1455 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1456 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1457}
1458
1459static void __init pbm_config_busmastering(struct pci_pbm_info *pbm)
1460{
1461 u8 *addr;
1462
1463 /* Set cache-line size to 64 bytes, this is actually
1464 * a nop but I do it for completeness.
1465 */
1466 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1467 0, PCI_CACHE_LINE_SIZE);
1468 pci_config_write8(addr, 64 / sizeof(u32));
1469
1470 /* Set PBM latency timer to 64 PCI clocks. */
1471 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1472 0, PCI_LATENCY_TIMER);
1473 pci_config_write8(addr, 64);
1474}
1475
1476static void __init pbm_scan_bus(struct pci_controller_info *p,
1477 struct pci_pbm_info *pbm)
1478{
1479 struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL);
1480
1481 if (!cookie) {
1482 prom_printf("%s: Critical allocation failure.\n", pbm->name);
1483 prom_halt();
1484 }
1485
1486 /* All we care about is the PBM. */
1487 memset(cookie, 0, sizeof(*cookie));
1488 cookie->pbm = pbm;
1489
1490 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
1491 p->pci_ops,
1492 pbm);
1493 pci_fixup_host_bridge_self(pbm->pci_bus);
1494 pbm->pci_bus->self->sysdata = cookie;
1495
1496 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
1497 pci_record_assignments(pbm, pbm->pci_bus);
1498 pci_assign_unassigned(pbm, pbm->pci_bus);
1499 pci_fixup_irq(pbm, pbm->pci_bus);
1500 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
1501 pci_setup_busmastering(pbm, pbm->pci_bus);
1502}
1503
1504static void __init __schizo_scan_bus(struct pci_controller_info *p,
1505 int chip_type)
1506{
1507 if (!p->pbm_B.prom_node || !p->pbm_A.prom_node) {
1508 printk("PCI: Only one PCI bus module of controller found.\n");
1509 printk("PCI: Ignoring entire controller.\n");
1510 return;
1511 }
1512
1513 pbm_config_busmastering(&p->pbm_B);
1514 p->pbm_B.is_66mhz_capable =
1515 prom_getbool(p->pbm_B.prom_node, "66mhz-capable");
1516 pbm_config_busmastering(&p->pbm_A);
1517 p->pbm_A.is_66mhz_capable =
1518 prom_getbool(p->pbm_A.prom_node, "66mhz-capable");
1519 pbm_scan_bus(p, &p->pbm_B);
1520 pbm_scan_bus(p, &p->pbm_A);
1521
1522 /* After the PCI bus scan is complete, we can register
1523 * the error interrupt handlers.
1524 */
1525 if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
1526 tomatillo_register_error_handlers(p);
1527 else
1528 schizo_register_error_handlers(p);
1529}
1530
1531static void __init schizo_scan_bus(struct pci_controller_info *p)
1532{
1533 __schizo_scan_bus(p, PBM_CHIP_TYPE_SCHIZO);
1534}
1535
1536static void __init tomatillo_scan_bus(struct pci_controller_info *p)
1537{
1538 __schizo_scan_bus(p, PBM_CHIP_TYPE_TOMATILLO);
1539}
1540
1541static void __init schizo_base_address_update(struct pci_dev *pdev, int resource)
1542{
1543 struct pcidev_cookie *pcp = pdev->sysdata;
1544 struct pci_pbm_info *pbm = pcp->pbm;
1545 struct resource *res, *root;
1546 u32 reg;
1547 int where, size, is_64bit;
1548
1549 res = &pdev->resource[resource];
1550 if (resource < 6) {
1551 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1552 } else if (resource == PCI_ROM_RESOURCE) {
1553 where = pdev->rom_base_reg;
1554 } else {
1555 /* Somebody might have asked allocation of a non-standard resource */
1556 return;
1557 }
1558
1559 is_64bit = 0;
1560 if (res->flags & IORESOURCE_IO)
1561 root = &pbm->io_space;
1562 else {
1563 root = &pbm->mem_space;
1564 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
1565 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1566 is_64bit = 1;
1567 }
1568
1569 size = res->end - res->start;
1570 pci_read_config_dword(pdev, where, &reg);
1571 reg = ((reg & size) |
1572 (((u32)(res->start - root->start)) & ~size));
1573 if (resource == PCI_ROM_RESOURCE) {
1574 reg |= PCI_ROM_ADDRESS_ENABLE;
1575 res->flags |= IORESOURCE_ROM_ENABLE;
1576 }
1577 pci_write_config_dword(pdev, where, reg);
1578
1579 /* This knows that the upper 32-bits of the address
1580 * must be zero. Our PCI common layer enforces this.
1581 */
1582 if (is_64bit)
1583 pci_write_config_dword(pdev, where + 4, 0);
1584}
1585
1586static void __init schizo_resource_adjust(struct pci_dev *pdev,
1587 struct resource *res,
1588 struct resource *root)
1589{
1590 res->start += root->start;
1591 res->end += root->start;
1592}
1593
1594/* Use ranges property to determine where PCI MEM, I/O, and Config
1595 * space are for this PCI bus module.
1596 */
1597static void schizo_determine_mem_io_space(struct pci_pbm_info *pbm)
1598{
1599 int i, saw_cfg, saw_mem, saw_io;
1600
1601 saw_cfg = saw_mem = saw_io = 0;
1602 for (i = 0; i < pbm->num_pbm_ranges; i++) {
1603 struct linux_prom_pci_ranges *pr = &pbm->pbm_ranges[i];
1604 unsigned long a;
1605 int type;
1606
1607 type = (pr->child_phys_hi >> 24) & 0x3;
1608 a = (((unsigned long)pr->parent_phys_hi << 32UL) |
1609 ((unsigned long)pr->parent_phys_lo << 0UL));
1610
1611 switch (type) {
1612 case 0:
1613 /* PCI config space, 16MB */
1614 pbm->config_space = a;
1615 saw_cfg = 1;
1616 break;
1617
1618 case 1:
1619 /* 16-bit IO space, 16MB */
1620 pbm->io_space.start = a;
1621 pbm->io_space.end = a + ((16UL*1024UL*1024UL) - 1UL);
1622 pbm->io_space.flags = IORESOURCE_IO;
1623 saw_io = 1;
1624 break;
1625
1626 case 2:
1627 /* 32-bit MEM space, 2GB */
1628 pbm->mem_space.start = a;
1629 pbm->mem_space.end = a + (0x80000000UL - 1UL);
1630 pbm->mem_space.flags = IORESOURCE_MEM;
1631 saw_mem = 1;
1632 break;
1633
1634 default:
1635 break;
1636 };
1637 }
1638
1639 if (!saw_cfg || !saw_io || !saw_mem) {
1640 prom_printf("%s: Fatal error, missing %s PBM range.\n",
1641 pbm->name,
1642 ((!saw_cfg ?
1643 "CFG" :
1644 (!saw_io ?
1645 "IO" : "MEM"))));
1646 prom_halt();
1647 }
1648
1649 printk("%s: PCI CFG[%lx] IO[%lx] MEM[%lx]\n",
1650 pbm->name,
1651 pbm->config_space,
1652 pbm->io_space.start,
1653 pbm->mem_space.start);
1654}
1655
1656static void __init pbm_register_toplevel_resources(struct pci_controller_info *p,
1657 struct pci_pbm_info *pbm)
1658{
1659 pbm->io_space.name = pbm->mem_space.name = pbm->name;
1660
1661 request_resource(&ioport_resource, &pbm->io_space);
1662 request_resource(&iomem_resource, &pbm->mem_space);
1663 pci_register_legacy_regions(&pbm->io_space,
1664 &pbm->mem_space);
1665}
1666
1667#define SCHIZO_STRBUF_CONTROL (0x02800UL)
1668#define SCHIZO_STRBUF_FLUSH (0x02808UL)
1669#define SCHIZO_STRBUF_FSYNC (0x02810UL)
1670#define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1671#define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1672
1673static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1674{
1675 unsigned long base = pbm->pbm_regs;
1676 u64 control;
1677
1678 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1679 /* TOMATILLO lacks streaming cache. */
1680 return;
1681 }
1682
1683 /* SCHIZO has context flushing. */
1684 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1685 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1686 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1687 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1688 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1689
1690 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1691 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1692 + 63UL)
1693 & ~63UL);
1694 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1695 __pa(pbm->stc.strbuf_flushflag);
1696
1697 /* Turn off LRU locking and diag mode, enable the
1698 * streaming buffer and leave the rerun-disable
1699 * setting however OBP set it.
1700 */
1701 control = schizo_read(pbm->stc.strbuf_control);
1702 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1703 SCHIZO_STRBUF_CTRL_LENAB |
1704 SCHIZO_STRBUF_CTRL_DENAB);
1705 control |= SCHIZO_STRBUF_CTRL_ENAB;
1706 schizo_write(pbm->stc.strbuf_control, control);
1707
1708 pbm->stc.strbuf_enabled = 1;
1709}
1710
1711#define SCHIZO_IOMMU_CONTROL (0x00200UL)
1712#define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1713#define SCHIZO_IOMMU_FLUSH (0x00210UL)
1714#define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1715
1716static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1717{
1718 struct pci_iommu *iommu = pbm->iommu;
1719 unsigned long tsbbase, i, tagbase, database, order;
1720 u32 vdma[2], dma_mask;
1721 u64 control;
1722 int err, tsbsize;
1723
1724 err = prom_getproperty(pbm->prom_node, "virtual-dma",
1725 (char *)&vdma[0], sizeof(vdma));
1726 if (err == 0 || err == -1) {
1727 /* No property, use default values. */
1728 vdma[0] = 0xc0000000;
1729 vdma[1] = 0x40000000;
1730 }
1731
1732 dma_mask = vdma[0];
1733 switch (vdma[1]) {
1734 case 0x20000000:
1735 dma_mask |= 0x1fffffff;
1736 tsbsize = 64;
1737 break;
1738
1739 case 0x40000000:
1740 dma_mask |= 0x3fffffff;
1741 tsbsize = 128;
1742 break;
1743
1744 case 0x80000000:
1745 dma_mask |= 0x7fffffff;
1746 tsbsize = 128;
1747 break;
1748
1749 default:
1750 prom_printf("SCHIZO: strange virtual-dma size.\n");
1751 prom_halt();
1752 };
1753
1754 /* Setup initial software IOMMU state. */
1755 spin_lock_init(&iommu->lock);
1756 iommu->iommu_cur_ctx = 0;
1757
1758 /* Register addresses, SCHIZO has iommu ctx flushing. */
1759 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1760 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1761 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
1762 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1763
1764 /* We use the main control/status register of SCHIZO as the write
1765 * completion register.
1766 */
1767 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1768
1769 /*
1770 * Invalidate TLB Entries.
1771 */
1772 control = schizo_read(iommu->iommu_control);
1773 control |= SCHIZO_IOMMU_CTRL_DENAB;
1774 schizo_write(iommu->iommu_control, control);
1775
1776 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1777
1778 for(i = 0; i < 16; i++) {
1779 schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0);
1780 schizo_write(pbm->pbm_regs + database + (i * 8UL), 0);
1781 }
1782
1783 /* Leave diag mode enabled for full-flushing done
1784 * in pci_iommu.c
1785 */
1786
1787 iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
1788 if (!iommu->dummy_page) {
1789 prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");
1790 prom_halt();
1791 }
1792 memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
1793 iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
1794
1795 /* Using assumed page size 8K with 128K entries we need 1MB iommu page
1796 * table (128K ioptes * 8 bytes per iopte). This is
1797 * page order 7 on UltraSparc.
1798 */
1799 order = get_order(tsbsize * 8 * 1024);
1800 tsbbase = __get_free_pages(GFP_KERNEL, order);
1801 if (!tsbbase) {
1802 prom_printf("%s: Error, gfp(tsb) failed.\n", pbm->name);
1803 prom_halt();
1804 }
1805
1806 iommu->page_table = (iopte_t *)tsbbase;
1807 iommu->page_table_map_base = vdma[0];
1808 iommu->dma_addr_mask = dma_mask;
1809 pci_iommu_table_init(iommu, PAGE_SIZE << order);
1810
1811 switch (tsbsize) {
1812 case 64:
1813 iommu->page_table_sz_bits = 16;
1814 break;
1815
1816 case 128:
1817 iommu->page_table_sz_bits = 17;
1818 break;
1819
1820 default:
1821 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
1822 prom_halt();
1823 break;
1824 };
1825
1826 /* We start with no consistent mappings. */
1827 iommu->lowest_consistent_map =
1828 1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
1829
1830 for (i = 0; i < PBM_NCLUSTERS; i++) {
1831 iommu->alloc_info[i].flush = 0;
1832 iommu->alloc_info[i].next = 0;
1833 }
1834
1835 schizo_write(iommu->iommu_tsbbase, __pa(tsbbase));
1836
1837 control = schizo_read(iommu->iommu_control);
1838 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1839 switch (tsbsize) {
1840 case 64:
1841 control |= SCHIZO_IOMMU_TSBSZ_64K;
1842 break;
1843 case 128:
1844 control |= SCHIZO_IOMMU_TSBSZ_128K;
1845 break;
1846 };
1847
1848 control |= SCHIZO_IOMMU_CTRL_ENAB;
1849 schizo_write(iommu->iommu_control, control);
1850}
1851
1852#define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1853#define SCHIZO_IRQ_RETRY_INF 0xffUL
1854
1855#define SCHIZO_PCI_DIAG (0x2020UL)
1856#define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1857#define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1858#define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1859#define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1860#define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1861#define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1862#define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1863#define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1864#define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1865
1866#define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1867#define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1868#define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1869#define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1870#define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1871#define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1872#define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1873#define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1874#define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1875#define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1876#define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1877#define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1878#define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1879#define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1880#define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1881#define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1882
1883#define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1884#define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1885
1886static void __init schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1887{
1888 u64 tmp;
1889
1890 /* Set IRQ retry to infinity. */
1891 schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY,
1892 SCHIZO_IRQ_RETRY_INF);
1893
1894 /* Enable arbiter for all PCI slots. Also, disable PCI interval
1895 * timer so that DTO (Discard TimeOuts) are not reported because
1896 * some Schizo revisions report them erroneously.
1897 */
1898 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1899 if (pbm->chip_type == PBM_CHIP_TYPE_SCHIZO_PLUS &&
1900 pbm->chip_version == 0x5 &&
1901 pbm->chip_revision == 0x1)
1902 tmp |= 0x0f;
1903 else
1904 tmp |= 0xff;
1905
1906 tmp &= ~SCHIZO_PCICTRL_PTO;
1907 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1908 pbm->chip_version >= 0x2)
1909 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1910 else
1911 tmp |= 0x1UL << SCHIZO_PCICTRL_PTO_SHIFT;
1912
1913 if (!prom_getbool(pbm->prom_node, "no-bus-parking"))
1914 tmp |= SCHIZO_PCICTRL_PARK;
1915
1916 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1917 pbm->chip_version <= 0x1)
1918 tmp |= (1UL << 61);
1919 else
1920 tmp &= ~(1UL << 61);
1921
1922 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1923 tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1924 SCHIZO_PCICTRL_RDO_PREF |
1925 SCHIZO_PCICTRL_RDL_PREF);
1926
1927 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1928
1929 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1930 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1931 SCHIZO_PCIDIAG_D_RETRY |
1932 SCHIZO_PCIDIAG_D_INTSYNC);
1933 schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp);
1934
1935 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1936 /* Clear prefetch lengths to workaround a bug in
1937 * Jalapeno...
1938 */
1939 tmp = (TOMATILLO_IOC_PART_WPENAB |
1940 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1941 TOMATILLO_IOC_RDMULT_CPENAB |
1942 TOMATILLO_IOC_RDONE_CPENAB |
1943 TOMATILLO_IOC_RDLINE_CPENAB);
1944
1945 schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR,
1946 tmp);
1947 }
1948}
1949
1950static void __init schizo_pbm_init(struct pci_controller_info *p,
1951 int prom_node, u32 portid,
1952 int chip_type)
1953{
1954 struct linux_prom64_registers pr_regs[4];
1955 unsigned int busrange[2];
1956 struct pci_pbm_info *pbm;
1957 const char *chipset_name;
1958 u32 ino_bitmap[2];
1959 int is_pbm_a;
1960 int err;
1961
1962 switch (chip_type) {
1963 case PBM_CHIP_TYPE_TOMATILLO:
1964 chipset_name = "TOMATILLO";
1965 break;
1966
1967 case PBM_CHIP_TYPE_SCHIZO_PLUS:
1968 chipset_name = "SCHIZO+";
1969 break;
1970
1971 case PBM_CHIP_TYPE_SCHIZO:
1972 default:
1973 chipset_name = "SCHIZO";
1974 break;
1975 };
1976
1977 /* For SCHIZO, three OBP regs:
1978 * 1) PBM controller regs
1979 * 2) Schizo front-end controller regs (same for both PBMs)
1980 * 3) PBM PCI config space
1981 *
1982 * For TOMATILLO, four OBP regs:
1983 * 1) PBM controller regs
1984 * 2) Tomatillo front-end controller regs
1985 * 3) PBM PCI config space
1986 * 4) Ichip regs
1987 */
1988 err = prom_getproperty(prom_node, "reg",
1989 (char *)&pr_regs[0],
1990 sizeof(pr_regs));
1991 if (err == 0 || err == -1) {
1992 prom_printf("%s: Fatal error, no reg property.\n",
1993 chipset_name);
1994 prom_halt();
1995 }
1996
1997 is_pbm_a = ((pr_regs[0].phys_addr & 0x00700000) == 0x00600000);
1998
1999 if (is_pbm_a)
2000 pbm = &p->pbm_A;
2001 else
2002 pbm = &p->pbm_B;
2003
2004 pbm->portid = portid;
2005 pbm->parent = p;
2006 pbm->prom_node = prom_node;
2007 pbm->pci_first_slot = 1;
2008
2009 pbm->chip_type = chip_type;
2010 pbm->chip_version =
2011 prom_getintdefault(prom_node, "version#", 0);
2012 pbm->chip_revision =
2013 prom_getintdefault(prom_node, "module-revision#", 0);
2014
2015 pbm->pbm_regs = pr_regs[0].phys_addr;
2016 pbm->controller_regs = pr_regs[1].phys_addr - 0x10000UL;
2017
2018 sprintf(pbm->name,
2019 (chip_type == PBM_CHIP_TYPE_TOMATILLO ?
2020 "TOMATILLO%d PBM%c" :
2021 "SCHIZO%d PBM%c"),
2022 p->index,
2023 (pbm == &p->pbm_A ? 'A' : 'B'));
2024
2025 printk("%s: ver[%x:%x], portid %x, "
2026 "cregs[%lx] pregs[%lx]\n",
2027 pbm->name,
2028 pbm->chip_version, pbm->chip_revision,
2029 pbm->portid,
2030 pbm->controller_regs,
2031 pbm->pbm_regs);
2032
2033 schizo_pbm_hw_init(pbm);
2034
2035 prom_getstring(prom_node, "name",
2036 pbm->prom_name,
2037 sizeof(pbm->prom_name));
2038
2039 err = prom_getproperty(prom_node, "ranges",
2040 (char *) pbm->pbm_ranges,
2041 sizeof(pbm->pbm_ranges));
2042 if (err == 0 || err == -1) {
2043 prom_printf("%s: Fatal error, no ranges property.\n",
2044 pbm->name);
2045 prom_halt();
2046 }
2047
2048 pbm->num_pbm_ranges =
2049 (err / sizeof(struct linux_prom_pci_ranges));
2050
2051 schizo_determine_mem_io_space(pbm);
2052 pbm_register_toplevel_resources(p, pbm);
2053
2054 err = prom_getproperty(prom_node, "interrupt-map",
2055 (char *)pbm->pbm_intmap,
2056 sizeof(pbm->pbm_intmap));
2057 if (err != -1) {
2058 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
2059 err = prom_getproperty(prom_node, "interrupt-map-mask",
2060 (char *)&pbm->pbm_intmask,
2061 sizeof(pbm->pbm_intmask));
2062 if (err == -1) {
2063 prom_printf("%s: Fatal error, no "
2064 "interrupt-map-mask.\n", pbm->name);
2065 prom_halt();
2066 }
2067 } else {
2068 pbm->num_pbm_intmap = 0;
2069 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
2070 }
2071
2072 err = prom_getproperty(prom_node, "ino-bitmap",
2073 (char *) &ino_bitmap[0],
2074 sizeof(ino_bitmap));
2075 if (err == 0 || err == -1) {
2076 prom_printf("%s: Fatal error, no ino-bitmap.\n", pbm->name);
2077 prom_halt();
2078 }
2079 pbm->ino_bitmap = (((u64)ino_bitmap[1] << 32UL) |
2080 ((u64)ino_bitmap[0] << 0UL));
2081
2082 err = prom_getproperty(prom_node, "bus-range",
2083 (char *)&busrange[0],
2084 sizeof(busrange));
2085 if (err == 0 || err == -1) {
2086 prom_printf("%s: Fatal error, no bus-range.\n", pbm->name);
2087 prom_halt();
2088 }
2089 pbm->pci_first_busno = busrange[0];
2090 pbm->pci_last_busno = busrange[1];
2091
2092 schizo_pbm_iommu_init(pbm);
2093 schizo_pbm_strbuf_init(pbm);
2094}
2095
2096static inline int portid_compare(u32 x, u32 y, int chip_type)
2097{
2098 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
2099 if (x == (y ^ 1))
2100 return 1;
2101 return 0;
2102 }
2103 return (x == y);
2104}
2105
2106static void __init __schizo_init(int node, char *model_name, int chip_type)
2107{
2108 struct pci_controller_info *p;
2109 struct pci_iommu *iommu;
2110 int is_pbm_a;
2111 u32 portid;
2112
2113 portid = prom_getintdefault(node, "portid", 0xff);
2114
2115 for(p = pci_controller_root; p; p = p->next) {
2116 struct pci_pbm_info *pbm;
2117
2118 if (p->pbm_A.prom_node && p->pbm_B.prom_node)
2119 continue;
2120
2121 pbm = (p->pbm_A.prom_node ?
2122 &p->pbm_A :
2123 &p->pbm_B);
2124
2125 if (portid_compare(pbm->portid, portid, chip_type)) {
2126 is_pbm_a = (p->pbm_A.prom_node == 0);
2127 schizo_pbm_init(p, node, portid, chip_type);
2128 return;
2129 }
2130 }
2131
2132 p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
2133 if (!p) {
2134 prom_printf("SCHIZO: Fatal memory allocation error.\n");
2135 prom_halt();
2136 }
2137 memset(p, 0, sizeof(*p));
2138
2139 iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
2140 if (!iommu) {
2141 prom_printf("SCHIZO: Fatal memory allocation error.\n");
2142 prom_halt();
2143 }
2144 memset(iommu, 0, sizeof(*iommu));
2145 p->pbm_A.iommu = iommu;
2146
2147 iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
2148 if (!iommu) {
2149 prom_printf("SCHIZO: Fatal memory allocation error.\n");
2150 prom_halt();
2151 }
2152 memset(iommu, 0, sizeof(*iommu));
2153 p->pbm_B.iommu = iommu;
2154
2155 p->next = pci_controller_root;
2156 pci_controller_root = p;
2157
2158 p->index = pci_num_controllers++;
2159 p->pbms_same_domain = 0;
2160 p->scan_bus = (chip_type == PBM_CHIP_TYPE_TOMATILLO ?
2161 tomatillo_scan_bus :
2162 schizo_scan_bus);
2163 p->irq_build = schizo_irq_build;
2164 p->base_address_update = schizo_base_address_update;
2165 p->resource_adjust = schizo_resource_adjust;
2166 p->pci_ops = &schizo_ops;
2167
2168 /* Like PSYCHO we have a 2GB aligned area for memory space. */
2169 pci_memspace_mask = 0x7fffffffUL;
2170
2171 schizo_pbm_init(p, node, portid, chip_type);
2172}
2173
2174void __init schizo_init(int node, char *model_name)
2175{
2176 __schizo_init(node, model_name, PBM_CHIP_TYPE_SCHIZO);
2177}
2178
2179void __init schizo_plus_init(int node, char *model_name)
2180{
2181 __schizo_init(node, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS);
2182}
2183
2184void __init tomatillo_init(int node, char *model_name)
2185{
2186 __schizo_init(node, model_name, PBM_CHIP_TYPE_TOMATILLO);
2187}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 11:28:58 -0500