diff options
Diffstat (limited to 'arch/sparc64/kernel/pci_schizo.c')
-rw-r--r-- | arch/sparc64/kernel/pci_schizo.c | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c index ba9206eb9516..99912db4e7e8 100644 --- a/arch/sparc64/kernel/pci_schizo.c +++ b/arch/sparc64/kernel/pci_schizo.c | |||
@@ -1251,50 +1251,6 @@ static void schizo_scan_bus(struct pci_controller_info *p) | |||
1251 | schizo_register_error_handlers(p); | 1251 | schizo_register_error_handlers(p); |
1252 | } | 1252 | } |
1253 | 1253 | ||
1254 | static void schizo_base_address_update(struct pci_dev *pdev, int resource) | ||
1255 | { | ||
1256 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; | ||
1257 | struct resource *res, *root; | ||
1258 | u32 reg; | ||
1259 | int where, size, is_64bit; | ||
1260 | |||
1261 | res = &pdev->resource[resource]; | ||
1262 | if (resource < 6) { | ||
1263 | where = PCI_BASE_ADDRESS_0 + (resource * 4); | ||
1264 | } else if (resource == PCI_ROM_RESOURCE) { | ||
1265 | where = pdev->rom_base_reg; | ||
1266 | } else { | ||
1267 | /* Somebody might have asked allocation of a non-standard resource */ | ||
1268 | return; | ||
1269 | } | ||
1270 | |||
1271 | is_64bit = 0; | ||
1272 | if (res->flags & IORESOURCE_IO) | ||
1273 | root = &pbm->io_space; | ||
1274 | else { | ||
1275 | root = &pbm->mem_space; | ||
1276 | if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) | ||
1277 | == PCI_BASE_ADDRESS_MEM_TYPE_64) | ||
1278 | is_64bit = 1; | ||
1279 | } | ||
1280 | |||
1281 | size = res->end - res->start; | ||
1282 | pci_read_config_dword(pdev, where, ®); | ||
1283 | reg = ((reg & size) | | ||
1284 | (((u32)(res->start - root->start)) & ~size)); | ||
1285 | if (resource == PCI_ROM_RESOURCE) { | ||
1286 | reg |= PCI_ROM_ADDRESS_ENABLE; | ||
1287 | res->flags |= IORESOURCE_ROM_ENABLE; | ||
1288 | } | ||
1289 | pci_write_config_dword(pdev, where, reg); | ||
1290 | |||
1291 | /* This knows that the upper 32-bits of the address | ||
1292 | * must be zero. Our PCI common layer enforces this. | ||
1293 | */ | ||
1294 | if (is_64bit) | ||
1295 | pci_write_config_dword(pdev, where + 4, 0); | ||
1296 | } | ||
1297 | |||
1298 | #define SCHIZO_STRBUF_CONTROL (0x02800UL) | 1254 | #define SCHIZO_STRBUF_CONTROL (0x02800UL) |
1299 | #define SCHIZO_STRBUF_FLUSH (0x02808UL) | 1255 | #define SCHIZO_STRBUF_FLUSH (0x02808UL) |
1300 | #define SCHIZO_STRBUF_FSYNC (0x02810UL) | 1256 | #define SCHIZO_STRBUF_FSYNC (0x02810UL) |
@@ -1661,7 +1617,6 @@ static void __schizo_init(struct device_node *dp, char *model_name, int chip_typ | |||
1661 | 1617 | ||
1662 | p->index = pci_num_controllers++; | 1618 | p->index = pci_num_controllers++; |
1663 | p->scan_bus = schizo_scan_bus; | 1619 | p->scan_bus = schizo_scan_bus; |
1664 | p->base_address_update = schizo_base_address_update; | ||
1665 | p->pci_ops = &schizo_ops; | 1620 | p->pci_ops = &schizo_ops; |
1666 | 1621 | ||
1667 | /* Like PSYCHO we have a 2GB aligned area for memory space. */ | 1622 | /* Like PSYCHO we have a 2GB aligned area for memory space. */ |