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Diffstat (limited to 'arch/sparc64/kernel/pci_schizo.c')
-rw-r--r--arch/sparc64/kernel/pci_schizo.c122
1 files changed, 2 insertions, 120 deletions
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index e375d72b8eed..ae76898bbe2b 100644
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -104,125 +104,6 @@ static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
104 SCHIZO_CONFIG_ENCODE(bus, devfn, where)); 104 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
105} 105}
106 106
107/* Just make sure the bus number is in range. */
108static int schizo_out_of_range(struct pci_pbm_info *pbm,
109 unsigned char bus,
110 unsigned char devfn)
111{
112 if (bus < pbm->pci_first_busno ||
113 bus > pbm->pci_last_busno)
114 return 1;
115 return 0;
116}
117
118/* SCHIZO PCI configuration space accessors. */
119
120static int schizo_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
121 int where, int size, u32 *value)
122{
123 struct pci_pbm_info *pbm = bus_dev->sysdata;
124 unsigned char bus = bus_dev->number;
125 u32 *addr;
126 u16 tmp16;
127 u8 tmp8;
128
129 if (bus_dev == pbm->pci_bus && devfn == 0x00)
130 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
131 size, value);
132 switch (size) {
133 case 1:
134 *value = 0xff;
135 break;
136 case 2:
137 *value = 0xffff;
138 break;
139 case 4:
140 *value = 0xffffffff;
141 break;
142 }
143
144 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
145 if (!addr)
146 return PCIBIOS_SUCCESSFUL;
147
148 if (schizo_out_of_range(pbm, bus, devfn))
149 return PCIBIOS_SUCCESSFUL;
150 switch (size) {
151 case 1:
152 pci_config_read8((u8 *)addr, &tmp8);
153 *value = tmp8;
154 break;
155
156 case 2:
157 if (where & 0x01) {
158 printk("pci_read_config_word: misaligned reg [%x]\n",
159 where);
160 return PCIBIOS_SUCCESSFUL;
161 }
162 pci_config_read16((u16 *)addr, &tmp16);
163 *value = tmp16;
164 break;
165
166 case 4:
167 if (where & 0x03) {
168 printk("pci_read_config_dword: misaligned reg [%x]\n",
169 where);
170 return PCIBIOS_SUCCESSFUL;
171 }
172 pci_config_read32(addr, value);
173 break;
174 }
175 return PCIBIOS_SUCCESSFUL;
176}
177
178static int schizo_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
179 int where, int size, u32 value)
180{
181 struct pci_pbm_info *pbm = bus_dev->sysdata;
182 unsigned char bus = bus_dev->number;
183 u32 *addr;
184
185 if (bus_dev == pbm->pci_bus && devfn == 0x00)
186 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
187 size, value);
188 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
189 if (!addr)
190 return PCIBIOS_SUCCESSFUL;
191
192 if (schizo_out_of_range(pbm, bus, devfn))
193 return PCIBIOS_SUCCESSFUL;
194
195 switch (size) {
196 case 1:
197 pci_config_write8((u8 *)addr, value);
198 break;
199
200 case 2:
201 if (where & 0x01) {
202 printk("pci_write_config_word: misaligned reg [%x]\n",
203 where);
204 return PCIBIOS_SUCCESSFUL;
205 }
206 pci_config_write16((u16 *)addr, value);
207 break;
208
209 case 4:
210 if (where & 0x03) {
211 printk("pci_write_config_dword: misaligned reg [%x]\n",
212 where);
213 return PCIBIOS_SUCCESSFUL;
214 }
215
216 pci_config_write32(addr, value);
217 }
218 return PCIBIOS_SUCCESSFUL;
219}
220
221static struct pci_ops schizo_ops = {
222 .read = schizo_read_pci_cfg,
223 .write = schizo_write_pci_cfg,
224};
225
226/* SCHIZO error handling support. */ 107/* SCHIZO error handling support. */
227enum schizo_error_type { 108enum schizo_error_type {
228 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR 109 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
@@ -1494,7 +1375,8 @@ static void schizo_pbm_init(struct pci_controller_info *p,
1494 pci_pbm_root = pbm; 1375 pci_pbm_root = pbm;
1495 1376
1496 pbm->scan_bus = schizo_scan_bus; 1377 pbm->scan_bus = schizo_scan_bus;
1497 pbm->pci_ops = &schizo_ops; 1378 pbm->pci_ops = &sun4u_pci_ops;
1379 pbm->config_space_reg_bits = 8;
1498 1380
1499 pbm->index = pci_num_pbms++; 1381 pbm->index = pci_num_pbms++;
1500 1382