1 files changed, 2 insertions, 133 deletions
diff --git a/arch/sparc64/kernel/pci_fire.c b/arch/sparc64/kernel/pci_fire.c
index 2e0eb4ee8f71..9198c1a0f7a5 100644
--- a/arch/sparc64/kernel/pci_fire.c
+++ b/arch/sparc64/kernel/pci_fire.c
@@ -27,138 +27,6 @@
                               "i" (ASI_PHYS_BYPASS_EC_E) \
                             : "memory")
-/* Fire config space address format is nearly identical to
- * that of SCHIZO and PSYCHO, except that in order to accomodate
- * PCI-E extended config space the encoding can handle 12 bits
- * of register address:
- *
- *  32     28 27 20 19    15 14      12 11  2  1 0
- * -------------------------------------------------
- * |0 0 0 0 0| bus | device | function | reg | 0 0 |
- * -------------------------------------------------
- */
-#define FIRE_CONFIG_BASE(PBM)   ((PBM)->config_space)
-#define FIRE_CONFIG_ENCODE(BUS, DEVFN, REG)     \
-        (((unsigned long)(BUS)   << 20) |       \
-         ((unsigned long)(DEVFN) << 12)  |      \
-         ((unsigned long)(REG)))
-static void *fire_pci_config_mkaddr(struct pci_pbm_info *pbm,
-                                      unsigned char bus,
-                                      unsigned int devfn,
-                                      int where)
-{
-        if (!pbm)
-                return NULL;
-        return (void *)
-                (FIRE_CONFIG_BASE(pbm) |
-                 FIRE_CONFIG_ENCODE(bus, devfn, where));
-}
-/* FIRE PCI configuration space accessors. */
-static int fire_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
-                             int where, int size, u32 *value)
-{
-        struct pci_pbm_info *pbm = bus_dev->sysdata;
-        unsigned char bus = bus_dev->number;
-        u32 *addr;
-        u16 tmp16;
-        u8 tmp8;
-        if (bus_dev == pbm->pci_bus && devfn == 0x00)
-                return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
-                                                    size, value);
-        switch (size) {
-        case 1:
-                *value = 0xff;
-                break;
-        case 2:
-                *value = 0xffff;
-                break;
-        case 4:
-                *value = 0xffffffff;
-                break;
-        }
-        addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
-        if (!addr)
-                return PCIBIOS_SUCCESSFUL;
-        switch (size) {
-        case 1:
-                pci_config_read8((u8 *)addr, &tmp8);
-                *value = tmp8;
-                break;
-        case 2:
-                if (where & 0x01) {
-                        printk("pci_read_config_word: misaligned reg [%x]\n",
-                               where);
-                        return PCIBIOS_SUCCESSFUL;
-                }
-                pci_config_read16((u16 *)addr, &tmp16);
-                *value = tmp16;
-                break;
-        case 4:
-                if (where & 0x03) {
-                        printk("pci_read_config_dword: misaligned reg [%x]\n",
-                               where);
-                        return PCIBIOS_SUCCESSFUL;
-                }
-                pci_config_read32(addr, value);
-                break;
-        }
-        return PCIBIOS_SUCCESSFUL;
-}
-static int fire_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
-                              int where, int size, u32 value)
-{
-        struct pci_pbm_info *pbm = bus_dev->sysdata;
-        unsigned char bus = bus_dev->number;
-        u32 *addr;
-        if (bus_dev == pbm->pci_bus && devfn == 0x00)
-                return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
-                                                     size, value);
-        addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
-        if (!addr)
-                return PCIBIOS_SUCCESSFUL;
-        switch (size) {
-        case 1:
-                pci_config_write8((u8 *)addr, value);
-                break;
-        case 2:
-                if (where & 0x01) {
-                        printk("pci_write_config_word: misaligned reg [%x]\n",
-                               where);
-                        return PCIBIOS_SUCCESSFUL;
-                }
-                pci_config_write16((u16 *)addr, value);
-                break;
-        case 4:
-                if (where & 0x03) {
-                        printk("pci_write_config_dword: misaligned reg [%x]\n",
-                               where);
-                        return PCIBIOS_SUCCESSFUL;
-                }
-                pci_config_write32(addr, value);
-        }
-        return PCIBIOS_SUCCESSFUL;
-}
-static struct pci_ops pci_fire_ops = {
-        .read   =       fire_read_pci_cfg,
-        .write  =       fire_write_pci_cfg,
-};
 static void pci_fire_scan_bus(struct pci_pbm_info *pbm)
 {
        pbm->pci_bus = pci_scan_one_pbm(pbm);
@@ -314,7 +182,8 @@ static void pci_fire_pbm_init(struct pci_controller_info *p,
        pci_pbm_root = pbm;
        pbm->scan_bus = pci_fire_scan_bus;
-        pbm->pci_ops = &pci_fire_ops;
+        pbm->pci_ops = &sun4u_pci_ops;
+        pbm->config_space_reg_bits = 12;
        pbm->index = pci_num_pbms++;

diff --git a/arch/sparc64/kernel/pci_fire.c b/arch/sparc64/kernel/pci_fire.c index 2e0eb4ee8f71..9198c1a0f7a5 100644 --- a/arch/sparc64/kernel/pci_fire.c +++ b/arch/sparc64/kernel/pci_fire.c
@@ -27,138 +27,6 @@
27	"i" (ASI_PHYS_BYPASS_EC_E) \	27	"i" (ASI_PHYS_BYPASS_EC_E) \
28	: "memory")	28	: "memory")
29		29
30	/* Fire config space address format is nearly identical to
31	* that of SCHIZO and PSYCHO, except that in order to accomodate
32	* PCI-E extended config space the encoding can handle 12 bits
33	* of register address:
34	*
35	* 32 28 27 20 19 15 14 12 11 2 1 0
36	* -------------------------------------------------
37	* \|0 0 0 0 0\| bus \| device \| function \| reg \| 0 0 \|
38	* -------------------------------------------------
39	*/
40	#define FIRE_CONFIG_BASE(PBM) ((PBM)->config_space)
41	#define FIRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
42	(((unsigned long)(BUS) << 20) \| \
43	((unsigned long)(DEVFN) << 12) \| \
44	((unsigned long)(REG)))
45
46	static void fire_pci_config_mkaddr(struct pci_pbm_info pbm,
47	unsigned char bus,
48	unsigned int devfn,
49	int where)
50	{
51	if (!pbm)
52	return NULL;
53	return (void *)
54	(FIRE_CONFIG_BASE(pbm) \|
55	FIRE_CONFIG_ENCODE(bus, devfn, where));
56	}
57
58	/* FIRE PCI configuration space accessors. */
59
60	static int fire_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
61	int where, int size, u32 *value)
62	{
63	struct pci_pbm_info *pbm = bus_dev->sysdata;
64	unsigned char bus = bus_dev->number;
65	u32 *addr;
66	u16 tmp16;
67	u8 tmp8;
68
69	if (bus_dev == pbm->pci_bus && devfn == 0x00)
70	return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
71	size, value);
72	switch (size) {
73	case 1:
74	*value = 0xff;
75	break;
76	case 2:
77	*value = 0xffff;
78	break;
79	case 4:
80	*value = 0xffffffff;
81	break;
82	}
83
84	addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
85	if (!addr)
86	return PCIBIOS_SUCCESSFUL;
87
88	switch (size) {
89	case 1:
90	pci_config_read8((u8 *)addr, &tmp8);
91	*value = tmp8;
92	break;
93
94	case 2:
95	if (where & 0x01) {
96	printk("pci_read_config_word: misaligned reg [%x]\n",
97	where);
98	return PCIBIOS_SUCCESSFUL;
99	}
100	pci_config_read16((u16 *)addr, &tmp16);
101	*value = tmp16;
102	break;
103
104	case 4:
105	if (where & 0x03) {
106	printk("pci_read_config_dword: misaligned reg [%x]\n",
107	where);
108	return PCIBIOS_SUCCESSFUL;
109	}
110
111	pci_config_read32(addr, value);
112	break;
113	}
114	return PCIBIOS_SUCCESSFUL;
115	}
116
117	static int fire_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
118	int where, int size, u32 value)
119	{
120	struct pci_pbm_info *pbm = bus_dev->sysdata;
121	unsigned char bus = bus_dev->number;
122	u32 *addr;
123
124	if (bus_dev == pbm->pci_bus && devfn == 0x00)
125	return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
126	size, value);
127	addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
128	if (!addr)
129	return PCIBIOS_SUCCESSFUL;
130
131	switch (size) {
132	case 1:
133	pci_config_write8((u8 *)addr, value);
134	break;
135
136	case 2:
137	if (where & 0x01) {
138	printk("pci_write_config_word: misaligned reg [%x]\n",
139	where);
140	return PCIBIOS_SUCCESSFUL;
141	}
142	pci_config_write16((u16 *)addr, value);
143	break;
144
145	case 4:
146	if (where & 0x03) {
147	printk("pci_write_config_dword: misaligned reg [%x]\n",
148	where);
149	return PCIBIOS_SUCCESSFUL;
150	}
151
152	pci_config_write32(addr, value);
153	}
154	return PCIBIOS_SUCCESSFUL;
155	}
156
157	static struct pci_ops pci_fire_ops = {
158	.read = fire_read_pci_cfg,
159	.write = fire_write_pci_cfg,
160	};
161
162	static void pci_fire_scan_bus(struct pci_pbm_info *pbm)	30	static void pci_fire_scan_bus(struct pci_pbm_info *pbm)
163	{	31	{
164	pbm->pci_bus = pci_scan_one_pbm(pbm);	32	pbm->pci_bus = pci_scan_one_pbm(pbm);
@@ -314,7 +182,8 @@ static void pci_fire_pbm_init(struct pci_controller_info *p,
314	pci_pbm_root = pbm;	182	pci_pbm_root = pbm;
315		183
316	pbm->scan_bus = pci_fire_scan_bus;	184	pbm->scan_bus = pci_fire_scan_bus;
317	pbm->pci_ops = &pci_fire_ops;	185	pbm->pci_ops = &sun4u_pci_ops;
		186	pbm->config_space_reg_bits = 12;
318		187
319	pbm->index = pci_num_pbms++;	188	pbm->index = pci_num_pbms++;
320		189