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Diffstat (limited to 'arch/sparc64/kernel/itlb_miss.S')
-rw-r--r--arch/sparc64/kernel/itlb_miss.S12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/sparc64/kernel/itlb_miss.S b/arch/sparc64/kernel/itlb_miss.S
index 730caa4a1506..6dfe3968c379 100644
--- a/arch/sparc64/kernel/itlb_miss.S
+++ b/arch/sparc64/kernel/itlb_miss.S
@@ -2,25 +2,25 @@
2 ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer 2 ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
3 ldxa [%g0] ASI_IMMU, %g6 ! Get TAG TARGET 3 ldxa [%g0] ASI_IMMU, %g6 ! Get TAG TARGET
4 srlx %g6, 48, %g5 ! Get context 4 srlx %g6, 48, %g5 ! Get context
5 sllx %g6, 22, %g6 ! Zero out context
5 brz,pn %g5, kvmap_itlb ! Context 0 processing 6 brz,pn %g5, kvmap_itlb ! Context 0 processing
6 nop ! Delay slot (fill me) 7 srlx %g6, 22, %g6 ! Delay slot
7 TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry 8 TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
8 cmp %g4, %g6 ! Compare TAG 9 cmp %g4, %g6 ! Compare TAG
9 sethi %hi(PAGE_EXEC), %g4 ! Setup exec check
10 10
11/* ITLB ** ICACHE line 2: TSB compare and TLB load */ 11/* ITLB ** ICACHE line 2: TSB compare and TLB load */
12 sethi %hi(PAGE_EXEC), %g4 ! Setup exec check
12 ldx [%g4 + %lo(PAGE_EXEC)], %g4 13 ldx [%g4 + %lo(PAGE_EXEC)], %g4
13 bne,pn %xcc, tsb_miss_itlb ! Miss 14 bne,pn %xcc, tsb_miss_itlb ! Miss
14 mov FAULT_CODE_ITLB, %g3 15 mov FAULT_CODE_ITLB, %g3
15 andcc %g5, %g4, %g0 ! Executable? 16 andcc %g5, %g4, %g0 ! Executable?
16 be,pn %xcc, tsb_do_fault 17 be,pn %xcc, tsb_do_fault
17 nop ! Delay slot, fill me 18 nop ! Delay slot, fill me
18 stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB 19 nop
19 retry ! Trap done
20 20
21/* ITLB ** ICACHE line 3: */ 21/* ITLB ** ICACHE line 3: */
22 nop 22 stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB
23 nop 23 retry ! Trap done
24 nop 24 nop
25 nop 25 nop
26 nop 26 nop