diff options
Diffstat (limited to 'arch/sparc64/kernel/etrap.S')
| -rw-r--r-- | arch/sparc64/kernel/etrap.S | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/arch/sparc64/kernel/etrap.S b/arch/sparc64/kernel/etrap.S index 567dbb765c34..8b3b6d720ed5 100644 --- a/arch/sparc64/kernel/etrap.S +++ b/arch/sparc64/kernel/etrap.S | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | .globl etrap, etrap_irq, etraptl1 | 31 | .globl etrap, etrap_irq, etraptl1 |
| 32 | etrap: rdpr %pil, %g2 | 32 | etrap: rdpr %pil, %g2 |
| 33 | etrap_irq: | 33 | etrap_irq: |
| 34 | TRAP_LOAD_THREAD_REG | ||
| 34 | rdpr %tstate, %g1 | 35 | rdpr %tstate, %g1 |
| 35 | sllx %g2, 20, %g3 | 36 | sllx %g2, 20, %g3 |
| 36 | andcc %g1, TSTATE_PRIV, %g0 | 37 | andcc %g1, TSTATE_PRIV, %g0 |
| @@ -98,11 +99,7 @@ etrap_irq: | |||
| 98 | stx %i7, [%sp + PTREGS_OFF + PT_V9_I7] | 99 | stx %i7, [%sp + PTREGS_OFF + PT_V9_I7] |
| 99 | wrpr %g0, ETRAP_PSTATE2, %pstate | 100 | wrpr %g0, ETRAP_PSTATE2, %pstate |
| 100 | mov %l6, %g6 | 101 | mov %l6, %g6 |
| 101 | #ifdef CONFIG_SMP | 102 | LOAD_PER_CPU_BASE(%g4, %g3) |
| 102 | #error IMMU TSB usage must be fixed | ||
| 103 | mov TSB_REG, %g3 | ||
| 104 | ldxa [%g3] ASI_IMMU, %g5 | ||
| 105 | #endif | ||
| 106 | jmpl %l2 + 0x4, %g0 | 103 | jmpl %l2 + 0x4, %g0 |
| 107 | ldx [%g6 + TI_TASK], %g4 | 104 | ldx [%g6 + TI_TASK], %g4 |
| 108 | 105 | ||
| @@ -126,6 +123,7 @@ etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself. | |||
| 126 | * 0x58 TL4's TT | 123 | * 0x58 TL4's TT |
| 127 | * 0x60 TL | 124 | * 0x60 TL |
| 128 | */ | 125 | */ |
| 126 | TRAP_LOAD_THREAD_REG | ||
| 129 | sub %sp, ((4 * 8) * 4) + 8, %g2 | 127 | sub %sp, ((4 * 8) * 4) + 8, %g2 |
| 130 | rdpr %tl, %g1 | 128 | rdpr %tl, %g1 |
| 131 | 129 | ||
| @@ -179,7 +177,9 @@ etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself. | |||
| 179 | 177 | ||
| 180 | .align 64 | 178 | .align 64 |
| 181 | .globl scetrap | 179 | .globl scetrap |
| 182 | scetrap: rdpr %pil, %g2 | 180 | scetrap: |
| 181 | TRAP_LOAD_THREAD_REG | ||
| 182 | rdpr %pil, %g2 | ||
| 183 | rdpr %tstate, %g1 | 183 | rdpr %tstate, %g1 |
| 184 | sllx %g2, 20, %g3 | 184 | sllx %g2, 20, %g3 |
| 185 | andcc %g1, TSTATE_PRIV, %g0 | 185 | andcc %g1, TSTATE_PRIV, %g0 |
| @@ -248,11 +248,7 @@ scetrap: rdpr %pil, %g2 | |||
| 248 | stx %i6, [%sp + PTREGS_OFF + PT_V9_I6] | 248 | stx %i6, [%sp + PTREGS_OFF + PT_V9_I6] |
| 249 | mov %l6, %g6 | 249 | mov %l6, %g6 |
| 250 | stx %i7, [%sp + PTREGS_OFF + PT_V9_I7] | 250 | stx %i7, [%sp + PTREGS_OFF + PT_V9_I7] |
| 251 | #ifdef CONFIG_SMP | 251 | LOAD_PER_CPU_BASE(%g4, %g3) |
| 252 | #error IMMU TSB usage must be fixed | ||
| 253 | mov TSB_REG, %g3 | ||
| 254 | ldxa [%g3] ASI_IMMU, %g5 | ||
| 255 | #endif | ||
| 256 | ldx [%g6 + TI_TASK], %g4 | 252 | ldx [%g6 + TI_TASK], %g4 |
| 257 | done | 253 | done |
| 258 | 254 | ||