1 files changed, 18 insertions, 162 deletions
diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index b48349527853..2879b1072921 100644
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -30,159 +30,6 @@
        .text
        .align          32
-        .globl          sparc64_vpte_patchme1
-        .globl          sparc64_vpte_patchme2
-/*
- * On a second level vpte miss, check whether the original fault is to the OBP 
- * range (note that this is only possible for instruction miss, data misses to
- * obp range do not use vpte). If so, go back directly to the faulting address.
- * This is because we want to read the tpc, otherwise we have no way of knowing
- * the 8k aligned faulting address if we are using >8k kernel pagesize. This
- * also ensures no vpte range addresses are dropped into tlb while obp is
- * executing (see inherit_locked_prom_mappings() rant).
- */
-sparc64_vpte_nucleus:
-        /* Note that kvmap below has verified that the address is
-         * in the range MODULES_VADDR --> VMALLOC_END already.  So
-         * here we need only check if it is an OBP address or not.
-         */
-        sethi           %hi(LOW_OBP_ADDRESS), %g5
-        cmp             %g4, %g5
-        blu,pn          %xcc, sparc64_vpte_patchme1
-         mov            0x1, %g5
-        sllx            %g5, 32, %g5
-        cmp             %g4, %g5
-        blu,pn          %xcc, obp_iaddr_patch
-         nop
-        /* These two instructions are patched by paginig_init().  */
-sparc64_vpte_patchme1:
-        sethi           %hi(0), %g5
-sparc64_vpte_patchme2:
-        or              %g5, %lo(0), %g5
-        /* With kernel PGD in %g5, branch back into dtlb_backend.  */
-        ba,pt           %xcc, sparc64_kpte_continue
-         andn           %g1, 0x3, %g1   /* Finish PMD offset adjustment.  */
-vpte_noent:
-        /* Restore previous TAG_ACCESS, %g5 is zero, and we will
-         * skip over the trap instruction so that the top level
-         * TLB miss handler will thing this %g5 value is just an
-         * invalid PTE, thus branching to full fault processing.
-         */
-        mov             TLB_SFSR, %g1
-        stxa            %g4, [%g1 + %g1] ASI_DMMU
-        done
-        .globl          obp_iaddr_patch
-obp_iaddr_patch:
-        /* These two instructions patched by inherit_prom_mappings().  */
-        sethi           %hi(0), %g5
-        or              %g5, %lo(0), %g5
-        /* Behave as if we are at TL0.  */
-        wrpr            %g0, 1, %tl
-        rdpr            %tpc, %g4       /* Find original faulting iaddr */
-        srlx            %g4, 13, %g4    /* Throw out context bits */
-        sllx            %g4, 13, %g4    /* g4 has vpn + ctx0 now */
-        /* Restore previous TAG_ACCESS.  */
-        mov             TLB_SFSR, %g1
-        stxa            %g4, [%g1 + %g1] ASI_IMMU
-        /* Get PMD offset.  */
-        srlx            %g4, 23, %g6
-        and             %g6, 0x7ff, %g6
-        sllx            %g6, 2, %g6
-        /* Load PMD, is it valid?  */
-        lduwa           [%g5 + %g6] ASI_PHYS_USE_EC, %g5
-        brz,pn          %g5, longpath
-         sllx           %g5, 11, %g5
-        /* Get PTE offset.  */
-        srlx            %g4, 13, %g6
-        and             %g6, 0x3ff, %g6
-        sllx            %g6, 3, %g6
-        /* Load PTE.  */
-        ldxa            [%g5 + %g6] ASI_PHYS_USE_EC, %g5
-        brgez,pn        %g5, longpath
-         nop
-        /* TLB load and return from trap.  */
-        stxa            %g5, [%g0] ASI_ITLB_DATA_IN
-        retry
-        .globl          obp_daddr_patch
-obp_daddr_patch:
-        /* These two instructions patched by inherit_prom_mappings().  */
-        sethi           %hi(0), %g5
-        or              %g5, %lo(0), %g5
-        /* Get PMD offset.  */
-        srlx            %g4, 23, %g6
-        and             %g6, 0x7ff, %g6
-        sllx            %g6, 2, %g6
-        /* Load PMD, is it valid?  */
-        lduwa           [%g5 + %g6] ASI_PHYS_USE_EC, %g5
-        brz,pn          %g5, longpath
-         sllx           %g5, 11, %g5
-        /* Get PTE offset.  */
-        srlx            %g4, 13, %g6
-        and             %g6, 0x3ff, %g6
-        sllx            %g6, 3, %g6
-        /* Load PTE.  */
-        ldxa            [%g5 + %g6] ASI_PHYS_USE_EC, %g5
-        brgez,pn        %g5, longpath
-         nop
-        /* TLB load and return from trap.  */
-        stxa            %g5, [%g0] ASI_DTLB_DATA_IN
-        retry
-/*
- * On a first level data miss, check whether this is to the OBP range (note
- * that such accesses can be made by prom, as well as by kernel using
- * prom_getproperty on "address"), and if so, do not use vpte access ...
- * rather, use information saved during inherit_prom_mappings() using 8k
- * pagesize.
- */
-        .align          32
-kvmap:
-        sethi           %hi(MODULES_VADDR), %g5
-        cmp             %g4, %g5
-        blu,pn          %xcc, longpath
-         mov            (VMALLOC_END >> 24), %g5
-        sllx            %g5, 24, %g5
-        cmp             %g4, %g5
-        bgeu,pn         %xcc, longpath
-         nop
-kvmap_check_obp:
-        sethi           %hi(LOW_OBP_ADDRESS), %g5
-        cmp             %g4, %g5
-        blu,pn          %xcc, kvmap_vmalloc_addr
-         mov            0x1, %g5
-        sllx            %g5, 32, %g5
-        cmp             %g4, %g5
-        blu,pn          %xcc, obp_daddr_patch
-         nop
-kvmap_vmalloc_addr:
-        /* If we get here, a vmalloc addr was accessed, load kernel VPTE.  */
-        ldxa            [%g3 + %g6] ASI_N, %g5
-        brgez,pn        %g5, longpath
-         nop
-        /* PTE is valid, load into TLB and return from trap.  */
-        stxa            %g5, [%g0] ASI_DTLB_DATA_IN     ! Reload TLB
-        retry
        /* This is trivial with the new code... */
        .globl          do_fpdis
 do_fpdis:
@@ -525,14 +372,13 @@ cheetah_plus_patch_fpdis:
         *
         * DATA 0: [low 32-bits]  Address of function to call, jmp to this
         *         [high 32-bits] MMU Context Argument 0, place in %g5
-         * DATA 1: Address Argument 1, place in %g6
+         * DATA 1: Address Argument 1, place in %g1
         * DATA 2: Address Argument 2, place in %g7
         *
         * With this method we can do most of the cross-call tlb/cache
         * flushing very quickly.
         *
-         * Current CPU's IRQ worklist table is locked into %g1,
+         * Current CPU's IRQ worklist table is locked into %g6, don't touch.
-         * don't touch.
         */
        .text
        .align          32
@@ -1006,13 +852,14 @@ cheetah_plus_dcpe_trap_vector:
        nop
 do_cheetah_plus_data_parity:
-        ba,pt           %xcc, etrap
+        rdpr            %pil, %g2
+        wrpr            %g0, 15, %pil
+        ba,pt           %xcc, etrap_irq
         rd             %pc, %g7
        mov             0x0, %o0
        call            cheetah_plus_parity_error
         add            %sp, PTREGS_OFF, %o1
-        ba,pt           %xcc, rtrap
+        ba,a,pt         %xcc, rtrap_irq
-         clr            %l6
 cheetah_plus_dcpe_trap_vector_tl1:
        membar          #Sync
@@ -1036,13 +883,14 @@ cheetah_plus_icpe_trap_vector:
        nop
 do_cheetah_plus_insn_parity:
-        ba,pt           %xcc, etrap
+        rdpr            %pil, %g2
+        wrpr            %g0, 15, %pil
+        ba,pt           %xcc, etrap_irq
         rd             %pc, %g7
        mov             0x1, %o0
        call            cheetah_plus_parity_error
         add            %sp, PTREGS_OFF, %o1
-        ba,pt           %xcc, rtrap
+        ba,a,pt         %xcc, rtrap_irq
-         clr            %l6
 cheetah_plus_icpe_trap_vector_tl1:
        membar          #Sync
@@ -1075,6 +923,10 @@ do_dcpe_tl1:
         nop
        wrpr            %g1, %tl                ! Restore original trap level
 do_dcpe_tl1_nonfatal:   /* Ok we may use interrupt globals safely. */
+        sethi           %hi(dcache_parity_tl1_occurred), %g2
+        lduw            [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
+        add             %g1, 1, %g1
+        stw             %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
        /* Reset D-cache parity */
        sethi           %hi(1 << 16), %g1       ! D-cache size
        mov             (1 << 5), %g2           ! D-cache line size
@@ -1121,6 +973,10 @@ do_icpe_tl1:
         nop
        wrpr            %g1, %tl                ! Restore original trap level
 do_icpe_tl1_nonfatal:   /* Ok we may use interrupt globals safely. */
+        sethi           %hi(icache_parity_tl1_occurred), %g2
+        lduw            [%g2 + %lo(icache_parity_tl1_occurred)], %g1
+        add             %g1, 1, %g1
+        stw             %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
        /* Flush I-cache */
        sethi           %hi(1 << 15), %g1       ! I-cache size
        mov             (1 << 5), %g2           ! I-cache line size

diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S index b48349527853..2879b1072921 100644 --- a/arch/sparc64/kernel/entry.S +++ b/arch/sparc64/kernel/entry.S
@@ -30,159 +30,6 @@
30	.text	30	.text
31	.align 32	31	.align 32
32		32
33	.globl sparc64_vpte_patchme1
34	.globl sparc64_vpte_patchme2
35	/*
36	* On a second level vpte miss, check whether the original fault is to the OBP
37	* range (note that this is only possible for instruction miss, data misses to
38	* obp range do not use vpte). If so, go back directly to the faulting address.
39	* This is because we want to read the tpc, otherwise we have no way of knowing
40	* the 8k aligned faulting address if we are using >8k kernel pagesize. This
41	* also ensures no vpte range addresses are dropped into tlb while obp is
42	* executing (see inherit_locked_prom_mappings() rant).
43	*/
44	sparc64_vpte_nucleus:
45	/* Note that kvmap below has verified that the address is
46	* in the range MODULES_VADDR --> VMALLOC_END already. So
47	* here we need only check if it is an OBP address or not.
48	*/
49	sethi %hi(LOW_OBP_ADDRESS), %g5
50	cmp %g4, %g5
51	blu,pn %xcc, sparc64_vpte_patchme1
52	mov 0x1, %g5
53	sllx %g5, 32, %g5
54	cmp %g4, %g5
55	blu,pn %xcc, obp_iaddr_patch
56	nop
57
58	/* These two instructions are patched by paginig_init(). */
59	sparc64_vpte_patchme1:
60	sethi %hi(0), %g5
61	sparc64_vpte_patchme2:
62	or %g5, %lo(0), %g5
63
64	/* With kernel PGD in %g5, branch back into dtlb_backend. */
65	ba,pt %xcc, sparc64_kpte_continue
66	andn %g1, 0x3, %g1 /* Finish PMD offset adjustment. */
67
68	vpte_noent:
69	/* Restore previous TAG_ACCESS, %g5 is zero, and we will
70	* skip over the trap instruction so that the top level
71	* TLB miss handler will thing this %g5 value is just an
72	* invalid PTE, thus branching to full fault processing.
73	*/
74	mov TLB_SFSR, %g1
75	stxa %g4, [%g1 + %g1] ASI_DMMU
76	done
77
78	.globl obp_iaddr_patch
79	obp_iaddr_patch:
80	/* These two instructions patched by inherit_prom_mappings(). */
81	sethi %hi(0), %g5
82	or %g5, %lo(0), %g5
83
84	/* Behave as if we are at TL0. */
85	wrpr %g0, 1, %tl
86	rdpr %tpc, %g4 /* Find original faulting iaddr */
87	srlx %g4, 13, %g4 /* Throw out context bits */
88	sllx %g4, 13, %g4 /* g4 has vpn + ctx0 now */
89
90	/* Restore previous TAG_ACCESS. */
91	mov TLB_SFSR, %g1
92	stxa %g4, [%g1 + %g1] ASI_IMMU
93
94	/* Get PMD offset. */
95	srlx %g4, 23, %g6
96	and %g6, 0x7ff, %g6
97	sllx %g6, 2, %g6
98
99	/* Load PMD, is it valid? */
100	lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
101	brz,pn %g5, longpath
102	sllx %g5, 11, %g5
103
104	/* Get PTE offset. */
105	srlx %g4, 13, %g6
106	and %g6, 0x3ff, %g6
107	sllx %g6, 3, %g6
108
109	/* Load PTE. */
110	ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
111	brgez,pn %g5, longpath
112	nop
113
114	/* TLB load and return from trap. */
115	stxa %g5, [%g0] ASI_ITLB_DATA_IN
116	retry
117
118	.globl obp_daddr_patch
119	obp_daddr_patch:
120	/* These two instructions patched by inherit_prom_mappings(). */
121	sethi %hi(0), %g5
122	or %g5, %lo(0), %g5
123
124	/* Get PMD offset. */
125	srlx %g4, 23, %g6
126	and %g6, 0x7ff, %g6
127	sllx %g6, 2, %g6
128
129	/* Load PMD, is it valid? */
130	lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
131	brz,pn %g5, longpath
132	sllx %g5, 11, %g5
133
134	/* Get PTE offset. */
135	srlx %g4, 13, %g6
136	and %g6, 0x3ff, %g6
137	sllx %g6, 3, %g6
138
139	/* Load PTE. */
140	ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
141	brgez,pn %g5, longpath
142	nop
143
144	/* TLB load and return from trap. */
145	stxa %g5, [%g0] ASI_DTLB_DATA_IN
146	retry
147
148	/*
149	* On a first level data miss, check whether this is to the OBP range (note
150	* that such accesses can be made by prom, as well as by kernel using
151	* prom_getproperty on "address"), and if so, do not use vpte access ...
152	* rather, use information saved during inherit_prom_mappings() using 8k
153	* pagesize.
154	*/
155	.align 32
156	kvmap:
157	sethi %hi(MODULES_VADDR), %g5
158	cmp %g4, %g5
159	blu,pn %xcc, longpath
160	mov (VMALLOC_END >> 24), %g5
161	sllx %g5, 24, %g5
162	cmp %g4, %g5
163	bgeu,pn %xcc, longpath
164	nop
165
166	kvmap_check_obp:
167	sethi %hi(LOW_OBP_ADDRESS), %g5
168	cmp %g4, %g5
169	blu,pn %xcc, kvmap_vmalloc_addr
170	mov 0x1, %g5
171	sllx %g5, 32, %g5
172	cmp %g4, %g5
173	blu,pn %xcc, obp_daddr_patch
174	nop
175
176	kvmap_vmalloc_addr:
177	/* If we get here, a vmalloc addr was accessed, load kernel VPTE. */
178	ldxa [%g3 + %g6] ASI_N, %g5
179	brgez,pn %g5, longpath
180	nop
181
182	/* PTE is valid, load into TLB and return from trap. */
183	stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
184	retry
185
186	/* This is trivial with the new code... */	33	/* This is trivial with the new code... */
187	.globl do_fpdis	34	.globl do_fpdis
188	do_fpdis:	35	do_fpdis:
@@ -525,14 +372,13 @@ cheetah_plus_patch_fpdis:
525	*	372	*
526	* DATA 0: [low 32-bits] Address of function to call, jmp to this	373	* DATA 0: [low 32-bits] Address of function to call, jmp to this
527	* [high 32-bits] MMU Context Argument 0, place in %g5	374	* [high 32-bits] MMU Context Argument 0, place in %g5
528	* DATA 1: Address Argument 1, place in %g6	375	* DATA 1: Address Argument 1, place in %g1
529	* DATA 2: Address Argument 2, place in %g7	376	* DATA 2: Address Argument 2, place in %g7
530	*	377	*
531	* With this method we can do most of the cross-call tlb/cache	378	* With this method we can do most of the cross-call tlb/cache
532	* flushing very quickly.	379	* flushing very quickly.
533	*	380	*
534	* Current CPU's IRQ worklist table is locked into %g1,	381	* Current CPU's IRQ worklist table is locked into %g6, don't touch.
535	* don't touch.
536	*/	382	*/
537	.text	383	.text
538	.align 32	384	.align 32
@@ -1006,13 +852,14 @@ cheetah_plus_dcpe_trap_vector:
1006	nop	852	nop
1007		853
1008	do_cheetah_plus_data_parity:	854	do_cheetah_plus_data_parity:
1009	ba,pt %xcc, etrap	855	rdpr %pil, %g2
		856	wrpr %g0, 15, %pil
		857	ba,pt %xcc, etrap_irq
1010	rd %pc, %g7	858	rd %pc, %g7
1011	mov 0x0, %o0	859	mov 0x0, %o0
1012	call cheetah_plus_parity_error	860	call cheetah_plus_parity_error
1013	add %sp, PTREGS_OFF, %o1	861	add %sp, PTREGS_OFF, %o1
1014	ba,pt %xcc, rtrap	862	ba,a,pt %xcc, rtrap_irq
1015	clr %l6
1016		863
1017	cheetah_plus_dcpe_trap_vector_tl1:	864	cheetah_plus_dcpe_trap_vector_tl1:
1018	membar #Sync	865	membar #Sync
@@ -1036,13 +883,14 @@ cheetah_plus_icpe_trap_vector:
1036	nop	883	nop
1037		884
1038	do_cheetah_plus_insn_parity:	885	do_cheetah_plus_insn_parity:
1039	ba,pt %xcc, etrap	886	rdpr %pil, %g2
		887	wrpr %g0, 15, %pil
		888	ba,pt %xcc, etrap_irq
1040	rd %pc, %g7	889	rd %pc, %g7
1041	mov 0x1, %o0	890	mov 0x1, %o0
1042	call cheetah_plus_parity_error	891	call cheetah_plus_parity_error
1043	add %sp, PTREGS_OFF, %o1	892	add %sp, PTREGS_OFF, %o1
1044	ba,pt %xcc, rtrap	893	ba,a,pt %xcc, rtrap_irq
1045	clr %l6
1046		894
1047	cheetah_plus_icpe_trap_vector_tl1:	895	cheetah_plus_icpe_trap_vector_tl1:
1048	membar #Sync	896	membar #Sync
@@ -1075,6 +923,10 @@ do_dcpe_tl1:
1075	nop	923	nop
1076	wrpr %g1, %tl ! Restore original trap level	924	wrpr %g1, %tl ! Restore original trap level
1077	do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */	925	do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
		926	sethi %hi(dcache_parity_tl1_occurred), %g2
		927	lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
		928	add %g1, 1, %g1
		929	stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
1078	/* Reset D-cache parity */	930	/* Reset D-cache parity */
1079	sethi %hi(1 << 16), %g1 ! D-cache size	931	sethi %hi(1 << 16), %g1 ! D-cache size
1080	mov (1 << 5), %g2 ! D-cache line size	932	mov (1 << 5), %g2 ! D-cache line size
@@ -1121,6 +973,10 @@ do_icpe_tl1:
1121	nop	973	nop
1122	wrpr %g1, %tl ! Restore original trap level	974	wrpr %g1, %tl ! Restore original trap level
1123	do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */	975	do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
		976	sethi %hi(icache_parity_tl1_occurred), %g2
		977	lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
		978	add %g1, 1, %g1
		979	stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
1124	/* Flush I-cache */	980	/* Flush I-cache */
1125	sethi %hi(1 << 15), %g1 ! I-cache size	981	sethi %hi(1 << 15), %g1 ! I-cache size
1126	mov (1 << 5), %g2 ! I-cache line size	982	mov (1 << 5), %g2 ! I-cache line size