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-rw-r--r--arch/sparc64/kernel/entry.S43
1 files changed, 8 insertions, 35 deletions
diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index 2879b1072921..f685035dbdb8 100644
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -97,8 +97,8 @@ do_fpdis:
97 faddd %f0, %f2, %f4 97 faddd %f0, %f2, %f4
98 fmuld %f0, %f2, %f6 98 fmuld %f0, %f2, %f6
99 ldxa [%g3] ASI_DMMU, %g5 99 ldxa [%g3] ASI_DMMU, %g5
100cplus_fptrap_insn_1: 100 sethi %hi(sparc64_kern_sec_context), %g2
101 sethi %hi(0), %g2 101 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
102 stxa %g2, [%g3] ASI_DMMU 102 stxa %g2, [%g3] ASI_DMMU
103 membar #Sync 103 membar #Sync
104 add %g6, TI_FPREGS + 0xc0, %g2 104 add %g6, TI_FPREGS + 0xc0, %g2
@@ -126,8 +126,8 @@ cplus_fptrap_insn_1:
126 fzero %f34 126 fzero %f34
127 ldxa [%g3] ASI_DMMU, %g5 127 ldxa [%g3] ASI_DMMU, %g5
128 add %g6, TI_FPREGS, %g1 128 add %g6, TI_FPREGS, %g1
129cplus_fptrap_insn_2: 129 sethi %hi(sparc64_kern_sec_context), %g2
130 sethi %hi(0), %g2 130 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
131 stxa %g2, [%g3] ASI_DMMU 131 stxa %g2, [%g3] ASI_DMMU
132 membar #Sync 132 membar #Sync
133 add %g6, TI_FPREGS + 0x40, %g2 133 add %g6, TI_FPREGS + 0x40, %g2
@@ -153,8 +153,8 @@ cplus_fptrap_insn_2:
1533: mov SECONDARY_CONTEXT, %g3 1533: mov SECONDARY_CONTEXT, %g3
154 add %g6, TI_FPREGS, %g1 154 add %g6, TI_FPREGS, %g1
155 ldxa [%g3] ASI_DMMU, %g5 155 ldxa [%g3] ASI_DMMU, %g5
156cplus_fptrap_insn_3: 156 sethi %hi(sparc64_kern_sec_context), %g2
157 sethi %hi(0), %g2 157 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
158 stxa %g2, [%g3] ASI_DMMU 158 stxa %g2, [%g3] ASI_DMMU
159 membar #Sync 159 membar #Sync
160 mov 0x40, %g2 160 mov 0x40, %g2
@@ -319,8 +319,8 @@ do_fptrap_after_fsr:
319 stx %g3, [%g6 + TI_GSR] 319 stx %g3, [%g6 + TI_GSR]
320 mov SECONDARY_CONTEXT, %g3 320 mov SECONDARY_CONTEXT, %g3
321 ldxa [%g3] ASI_DMMU, %g5 321 ldxa [%g3] ASI_DMMU, %g5
322cplus_fptrap_insn_4: 322 sethi %hi(sparc64_kern_sec_context), %g2
323 sethi %hi(0), %g2 323 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
324 stxa %g2, [%g3] ASI_DMMU 324 stxa %g2, [%g3] ASI_DMMU
325 membar #Sync 325 membar #Sync
326 add %g6, TI_FPREGS, %g2 326 add %g6, TI_FPREGS, %g2
@@ -341,33 +341,6 @@ cplus_fptrap_insn_4:
341 ba,pt %xcc, etrap 341 ba,pt %xcc, etrap
342 wr %g0, 0, %fprs 342 wr %g0, 0, %fprs
343 343
344cplus_fptrap_1:
345 sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2
346
347 .globl cheetah_plus_patch_fpdis
348cheetah_plus_patch_fpdis:
349 /* We configure the dTLB512_0 for 4MB pages and the
350 * dTLB512_1 for 8K pages when in context zero.
351 */
352 sethi %hi(cplus_fptrap_1), %o0
353 lduw [%o0 + %lo(cplus_fptrap_1)], %o1
354
355 set cplus_fptrap_insn_1, %o2
356 stw %o1, [%o2]
357 flush %o2
358 set cplus_fptrap_insn_2, %o2
359 stw %o1, [%o2]
360 flush %o2
361 set cplus_fptrap_insn_3, %o2
362 stw %o1, [%o2]
363 flush %o2
364 set cplus_fptrap_insn_4, %o2
365 stw %o1, [%o2]
366 flush %o2
367
368 retl
369 nop
370
371 /* The registers for cross calls will be: 344 /* The registers for cross calls will be:
372 * 345 *
373 * DATA 0: [low 32-bits] Address of function to call, jmp to this 346 * DATA 0: [low 32-bits] Address of function to call, jmp to this