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-rw-r--r--arch/sparc/oprofile/init.c110
1 files changed, 3 insertions, 107 deletions
diff --git a/arch/sparc/oprofile/init.c b/arch/sparc/oprofile/init.c
index d6e170c074fc..c8877a5202b0 100644
--- a/arch/sparc/oprofile/init.c
+++ b/arch/sparc/oprofile/init.c
@@ -17,47 +17,10 @@
17#include <asm/spitfire.h> 17#include <asm/spitfire.h>
18#include <asm/cpudata.h> 18#include <asm/cpudata.h>
19#include <asm/irq.h> 19#include <asm/irq.h>
20#include <asm/pcr.h>
20 21
21static int nmi_enabled; 22static int nmi_enabled;
22 23
23struct pcr_ops {
24 u64 (*read)(void);
25 void (*write)(u64);
26};
27static const struct pcr_ops *pcr_ops;
28
29static u64 direct_pcr_read(void)
30{
31 u64 val;
32
33 read_pcr(val);
34 return val;
35}
36
37static void direct_pcr_write(u64 val)
38{
39 write_pcr(val);
40}
41
42static const struct pcr_ops direct_pcr_ops = {
43 .read = direct_pcr_read,
44 .write = direct_pcr_write,
45};
46
47static void n2_pcr_write(u64 val)
48{
49 unsigned long ret;
50
51 ret = sun4v_niagara2_setperf(HV_N2_PERF_SPARC_CTL, val);
52 if (val != HV_EOK)
53 write_pcr(val);
54}
55
56static const struct pcr_ops n2_pcr_ops = {
57 .read = direct_pcr_read,
58 .write = n2_pcr_write,
59};
60
61/* In order to commonize as much of the implementation as 24/* In order to commonize as much of the implementation as
62 * possible, we use PICH as our counter. Mostly this is 25 * possible, we use PICH as our counter. Mostly this is
63 * to accomodate Niagara-1 which can only count insn cycles 26 * to accomodate Niagara-1 which can only count insn cycles
@@ -70,30 +33,13 @@ static u64 picl_value(void)
70 return ((u64)((0 - delta) & 0xffffffff)) << 32; 33 return ((u64)((0 - delta) & 0xffffffff)) << 32;
71} 34}
72 35
73#define PCR_PIC_PRIV 0x00000001 /* PIC access is privileged */
74#define PCR_STRACE 0x00000002 /* Trace supervisor events */
75#define PCR_UTRACE 0x00000004 /* Trace user events */
76#define PCR_N2_HTRACE 0x00000008 /* Trace hypervisor events */
77#define PCR_N2_TOE_OV0 0x00000010 /* Trap if PIC 0 overflows */
78#define PCR_N2_TOE_OV1 0x00000020 /* Trap if PIC 1 overflows */
79#define PCR_N2_MASK0 0x00003fc0
80#define PCR_N2_MASK0_SHIFT 6
81#define PCR_N2_SL0 0x0003c000
82#define PCR_N2_SL0_SHIFT 14
83#define PCR_N2_OV0 0x00040000
84#define PCR_N2_MASK1 0x07f80000
85#define PCR_N2_MASK1_SHIFT 19
86#define PCR_N2_SL1 0x78000000
87#define PCR_N2_SL1_SHIFT 27
88#define PCR_N2_OV1 0x80000000
89
90#define PCR_SUN4U_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE) 36#define PCR_SUN4U_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE)
91#define PCR_N2_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE | \ 37#define PCR_N2_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE | \
92 PCR_N2_TOE_OV1 | \ 38 PCR_N2_TOE_OV1 | \
93 (2 << PCR_N2_SL1_SHIFT) | \ 39 (2 << PCR_N2_SL1_SHIFT) | \
94 (0xff << PCR_N2_MASK1_SHIFT)) 40 (0xff << PCR_N2_MASK1_SHIFT))
95 41
96static u64 pcr_enable = PCR_SUN4U_ENABLE; 42static u64 pcr_enable;
97 43
98static void nmi_handler(struct pt_regs *regs) 44static void nmi_handler(struct pt_regs *regs)
99{ 45{
@@ -153,62 +99,16 @@ static void nmi_stop(void)
153 synchronize_sched(); 99 synchronize_sched();
154} 100}
155 101
156static unsigned long perf_hsvc_group;
157static unsigned long perf_hsvc_major;
158static unsigned long perf_hsvc_minor;
159
160static int __init register_perf_hsvc(void)
161{
162 if (tlb_type == hypervisor) {
163 switch (sun4v_chip_type) {
164 case SUN4V_CHIP_NIAGARA1:
165 perf_hsvc_group = HV_GRP_NIAG_PERF;
166 break;
167
168 case SUN4V_CHIP_NIAGARA2:
169 perf_hsvc_group = HV_GRP_N2_CPU;
170 break;
171
172 default:
173 return -ENODEV;
174 }
175
176
177 perf_hsvc_major = 1;
178 perf_hsvc_minor = 0;
179 if (sun4v_hvapi_register(perf_hsvc_group,
180 perf_hsvc_major,
181 &perf_hsvc_minor)) {
182 printk("perfmon: Could not register N2 hvapi.\n");
183 return -ENODEV;
184 }
185 }
186 return 0;
187}
188
189static void unregister_perf_hsvc(void)
190{
191 if (tlb_type != hypervisor)
192 return;
193 sun4v_hvapi_unregister(perf_hsvc_group);
194}
195
196static int oprofile_nmi_init(struct oprofile_operations *ops) 102static int oprofile_nmi_init(struct oprofile_operations *ops)
197{ 103{
198 int err = register_perf_hsvc();
199
200 if (err)
201 return err;
202
203 switch (tlb_type) { 104 switch (tlb_type) {
204 case hypervisor: 105 case hypervisor:
205 pcr_ops = &n2_pcr_ops;
206 pcr_enable = PCR_N2_ENABLE; 106 pcr_enable = PCR_N2_ENABLE;
207 break; 107 break;
208 108
209 case cheetah: 109 case cheetah:
210 case cheetah_plus: 110 case cheetah_plus:
211 pcr_ops = &direct_pcr_ops; 111 pcr_enable = PCR_SUN4U_ENABLE;
212 break; 112 break;
213 113
214 default: 114 default:
@@ -241,10 +141,6 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
241 return ret; 141 return ret;
242} 142}
243 143
244
245void oprofile_arch_exit(void) 144void oprofile_arch_exit(void)
246{ 145{
247#ifdef CONFIG_SPARC64
248 unregister_perf_hsvc();
249#endif
250} 146}