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-rw-r--r--arch/sparc/kernel/sun4m_irq.c74
1 files changed, 74 insertions, 0 deletions
diff --git a/arch/sparc/kernel/sun4m_irq.c b/arch/sparc/kernel/sun4m_irq.c
index 91a803ea88be..b92d6d2d5b04 100644
--- a/arch/sparc/kernel/sun4m_irq.c
+++ b/arch/sparc/kernel/sun4m_irq.c
@@ -38,11 +38,85 @@
38#include <asm/sbus.h> 38#include <asm/sbus.h>
39#include <asm/cacheflush.h> 39#include <asm/cacheflush.h>
40 40
41#include "irq.h"
42
43/* On the sun4m, just like the timers, we have both per-cpu and master
44 * interrupt registers.
45 */
46
47/* These registers are used for sending/receiving irqs from/to
48 * different cpu's.
49 */
50struct sun4m_intreg_percpu {
51 unsigned int tbt; /* Interrupts still pending for this cpu. */
52
53 /* These next two registers are WRITE-ONLY and are only
54 * "on bit" sensitive, "off bits" written have NO affect.
55 */
56 unsigned int clear; /* Clear this cpus irqs here. */
57 unsigned int set; /* Set this cpus irqs here. */
58 unsigned char space[PAGE_SIZE - 12];
59};
60
61/*
62 * djhr
63 * Actually the clear and set fields in this struct are misleading..
64 * according to the SLAVIO manual (and the same applies for the SEC)
65 * the clear field clears bits in the mask which will ENABLE that IRQ
66 * the set field sets bits in the mask to DISABLE the IRQ.
67 *
68 * Also the undirected_xx address in the SLAVIO is defined as
69 * RESERVED and write only..
70 *
71 * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
72 * sun4m machines, for MP the layout makes more sense.
73 */
74struct sun4m_intregs {
75 struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
76 unsigned int tbt; /* IRQ's that are still pending. */
77 unsigned int irqs; /* Master IRQ bits. */
78
79 /* Again, like the above, two these registers are WRITE-ONLY. */
80 unsigned int clear; /* Clear master IRQ's by setting bits here. */
81 unsigned int set; /* Set master IRQ's by setting bits here. */
82
83 /* This register is both READ and WRITE. */
84 unsigned int undirected_target; /* Which cpu gets undirected irqs. */
85};
86
41static unsigned long dummy; 87static unsigned long dummy;
42 88
43struct sun4m_intregs *sun4m_interrupts; 89struct sun4m_intregs *sun4m_interrupts;
44unsigned long *irq_rcvreg = &dummy; 90unsigned long *irq_rcvreg = &dummy;
45 91
92/* Dave Redman (djhr@tadpole.co.uk)
93 * The sun4m interrupt registers.
94 */
95#define SUN4M_INT_ENABLE 0x80000000
96#define SUN4M_INT_E14 0x00000080
97#define SUN4M_INT_E10 0x00080000
98
99#define SUN4M_HARD_INT(x) (0x000000001 << (x))
100#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
101
102#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
103#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
104#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
105#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
106#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
107#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
108#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
109#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
110#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
111#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
112#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
113#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
114#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
115#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
116
117#define SUN4M_INT_SBUS(x) (1 << (x+7))
118#define SUN4M_INT_VME(x) (1 << (x))
119
46/* These tables only apply for interrupts greater than 15.. 120/* These tables only apply for interrupts greater than 15..
47 * 121 *
48 * any intr value below 0x10 is considered to be a soft-int 122 * any intr value below 0x10 is considered to be a soft-int