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Diffstat (limited to 'arch/sparc/kernel/sun4m_irq.c')
-rw-r--r--arch/sparc/kernel/sun4m_irq.c22
1 files changed, 15 insertions, 7 deletions
diff --git a/arch/sparc/kernel/sun4m_irq.c b/arch/sparc/kernel/sun4m_irq.c
index 0d3a2d8cb266..87908a5b1223 100644
--- a/arch/sparc/kernel/sun4m_irq.c
+++ b/arch/sparc/kernel/sun4m_irq.c
@@ -318,9 +318,6 @@ struct sun4m_timer_global {
318 318
319static struct sun4m_timer_global __iomem *timers_global; 319static struct sun4m_timer_global __iomem *timers_global;
320 320
321
322unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
323
324static void sun4m_clear_clock_irq(void) 321static void sun4m_clear_clock_irq(void)
325{ 322{
326 sbus_readl(&timers_global->l10_limit); 323 sbus_readl(&timers_global->l10_limit);
@@ -369,10 +366,11 @@ void sun4m_clear_profile_irq(int cpu)
369 366
370static void sun4m_load_profile_irq(int cpu, unsigned int limit) 367static void sun4m_load_profile_irq(int cpu, unsigned int limit)
371{ 368{
372 sbus_writel(limit, &timers_percpu[cpu]->l14_limit); 369 unsigned int value = limit ? timer_value(limit) : 0;
370 sbus_writel(value, &timers_percpu[cpu]->l14_limit);
373} 371}
374 372
375static void __init sun4m_init_timers(irq_handler_t counter_fn) 373static void __init sun4m_init_timers(void)
376{ 374{
377 struct device_node *dp = of_find_node_by_name(NULL, "counter"); 375 struct device_node *dp = of_find_node_by_name(NULL, "counter");
378 int i, err, len, num_cpu_timers; 376 int i, err, len, num_cpu_timers;
@@ -402,13 +400,22 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn)
402 /* Every per-cpu timer works in timer mode */ 400 /* Every per-cpu timer works in timer mode */
403 sbus_writel(0x00000000, &timers_global->timer_config); 401 sbus_writel(0x00000000, &timers_global->timer_config);
404 402
405 sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit); 403#ifdef CONFIG_SMP
404 sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
405 sparc_config.features |= FEAT_L14_ONESHOT;
406#else
407 sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
408 sparc_config.features |= FEAT_L10_CLOCKEVENT;
409#endif
410 sparc_config.features |= FEAT_L10_CLOCKSOURCE;
411 sbus_writel(timer_value(sparc_config.cs_period),
412 &timers_global->l10_limit);
406 413
407 master_l10_counter = &timers_global->l10_count; 414 master_l10_counter = &timers_global->l10_count;
408 415
409 irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ); 416 irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ);
410 417
411 err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL); 418 err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
412 if (err) { 419 if (err) {
413 printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n", 420 printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
414 err); 421 err);
@@ -480,6 +487,7 @@ void __init sun4m_init_IRQ(void)
480 487
481 sparc_config.init_timers = sun4m_init_timers; 488 sparc_config.init_timers = sun4m_init_timers;
482 sparc_config.build_device_irq = sun4m_build_device_irq; 489 sparc_config.build_device_irq = sun4m_build_device_irq;
490 sparc_config.clock_rate = SBUS_CLOCK_RATE;
483 491
484#ifdef CONFIG_SMP 492#ifdef CONFIG_SMP
485 BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM); 493 BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);