diff options
Diffstat (limited to 'arch/sparc/kernel/pcr.c')
| -rw-r--r-- | arch/sparc/kernel/pcr.c | 83 |
1 files changed, 82 insertions, 1 deletions
diff --git a/arch/sparc/kernel/pcr.c b/arch/sparc/kernel/pcr.c index e408fc5d0c18..269af58497aa 100644 --- a/arch/sparc/kernel/pcr.c +++ b/arch/sparc/kernel/pcr.c | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | #include <asm/pil.h> | 13 | #include <asm/pil.h> |
| 14 | #include <asm/pcr.h> | 14 | #include <asm/pcr.h> |
| 15 | #include <asm/nmi.h> | 15 | #include <asm/nmi.h> |
| 16 | #include <asm/asi.h> | ||
| 16 | #include <asm/spitfire.h> | 17 | #include <asm/spitfire.h> |
| 17 | 18 | ||
| 18 | /* This code is shared between various users of the performance | 19 | /* This code is shared between various users of the performance |
| @@ -139,6 +140,57 @@ static const struct pcr_ops n2_pcr_ops = { | |||
| 139 | .pcr_nmi_disable = PCR_PIC_PRIV, | 140 | .pcr_nmi_disable = PCR_PIC_PRIV, |
| 140 | }; | 141 | }; |
| 141 | 142 | ||
| 143 | static u64 n4_pcr_read(unsigned long reg_num) | ||
| 144 | { | ||
| 145 | unsigned long val; | ||
| 146 | |||
| 147 | (void) sun4v_vt_get_perfreg(reg_num, &val); | ||
| 148 | |||
| 149 | return val; | ||
| 150 | } | ||
| 151 | |||
| 152 | static void n4_pcr_write(unsigned long reg_num, u64 val) | ||
| 153 | { | ||
| 154 | (void) sun4v_vt_set_perfreg(reg_num, val); | ||
| 155 | } | ||
| 156 | |||
| 157 | static u64 n4_pic_read(unsigned long reg_num) | ||
| 158 | { | ||
| 159 | unsigned long val; | ||
| 160 | |||
| 161 | __asm__ __volatile__("ldxa [%1] %2, %0" | ||
| 162 | : "=r" (val) | ||
| 163 | : "r" (reg_num * 0x8UL), "i" (ASI_PIC)); | ||
| 164 | |||
| 165 | return val; | ||
| 166 | } | ||
| 167 | |||
| 168 | static void n4_pic_write(unsigned long reg_num, u64 val) | ||
| 169 | { | ||
| 170 | __asm__ __volatile__("stxa %0, [%1] %2" | ||
| 171 | : /* no outputs */ | ||
| 172 | : "r" (val), "r" (reg_num * 0x8UL), "i" (ASI_PIC)); | ||
| 173 | } | ||
| 174 | |||
| 175 | static u64 n4_picl_value(unsigned int nmi_hz) | ||
| 176 | { | ||
| 177 | u32 delta = local_cpu_data().clock_tick / (nmi_hz << 2); | ||
| 178 | |||
| 179 | return ((u64)((0 - delta) & 0xffffffff)); | ||
| 180 | } | ||
| 181 | |||
| 182 | static const struct pcr_ops n4_pcr_ops = { | ||
| 183 | .read_pcr = n4_pcr_read, | ||
| 184 | .write_pcr = n4_pcr_write, | ||
| 185 | .read_pic = n4_pic_read, | ||
| 186 | .write_pic = n4_pic_write, | ||
| 187 | .nmi_picl_value = n4_picl_value, | ||
| 188 | .pcr_nmi_enable = (PCR_N4_PICNPT | PCR_N4_STRACE | | ||
| 189 | PCR_N4_UTRACE | PCR_N4_TOE | | ||
| 190 | (26 << PCR_N4_SL_SHIFT)), | ||
| 191 | .pcr_nmi_disable = PCR_N4_PICNPT, | ||
| 192 | }; | ||
| 193 | |||
| 142 | static unsigned long perf_hsvc_group; | 194 | static unsigned long perf_hsvc_group; |
| 143 | static unsigned long perf_hsvc_major; | 195 | static unsigned long perf_hsvc_major; |
| 144 | static unsigned long perf_hsvc_minor; | 196 | static unsigned long perf_hsvc_minor; |
| @@ -159,6 +211,10 @@ static int __init register_perf_hsvc(void) | |||
| 159 | perf_hsvc_group = HV_GRP_KT_CPU; | 211 | perf_hsvc_group = HV_GRP_KT_CPU; |
| 160 | break; | 212 | break; |
| 161 | 213 | ||
| 214 | case SUN4V_CHIP_NIAGARA4: | ||
| 215 | perf_hsvc_group = HV_GRP_VT_CPU; | ||
| 216 | break; | ||
| 217 | |||
| 162 | default: | 218 | default: |
| 163 | return -ENODEV; | 219 | return -ENODEV; |
| 164 | } | 220 | } |
| @@ -183,6 +239,29 @@ static void __init unregister_perf_hsvc(void) | |||
| 183 | sun4v_hvapi_unregister(perf_hsvc_group); | 239 | sun4v_hvapi_unregister(perf_hsvc_group); |
| 184 | } | 240 | } |
| 185 | 241 | ||
| 242 | static int __init setup_sun4v_pcr_ops(void) | ||
| 243 | { | ||
| 244 | int ret = 0; | ||
| 245 | |||
| 246 | switch (sun4v_chip_type) { | ||
| 247 | case SUN4V_CHIP_NIAGARA1: | ||
| 248 | case SUN4V_CHIP_NIAGARA2: | ||
| 249 | case SUN4V_CHIP_NIAGARA3: | ||
| 250 | pcr_ops = &n2_pcr_ops; | ||
| 251 | break; | ||
| 252 | |||
| 253 | case SUN4V_CHIP_NIAGARA4: | ||
| 254 | pcr_ops = &n4_pcr_ops; | ||
| 255 | break; | ||
| 256 | |||
| 257 | default: | ||
| 258 | ret = -ENODEV; | ||
| 259 | break; | ||
| 260 | } | ||
| 261 | |||
| 262 | return ret; | ||
| 263 | } | ||
| 264 | |||
| 186 | int __init pcr_arch_init(void) | 265 | int __init pcr_arch_init(void) |
| 187 | { | 266 | { |
| 188 | int err = register_perf_hsvc(); | 267 | int err = register_perf_hsvc(); |
| @@ -192,7 +271,9 @@ int __init pcr_arch_init(void) | |||
| 192 | 271 | ||
| 193 | switch (tlb_type) { | 272 | switch (tlb_type) { |
| 194 | case hypervisor: | 273 | case hypervisor: |
| 195 | pcr_ops = &n2_pcr_ops; | 274 | err = setup_sun4v_pcr_ops(); |
| 275 | if (err) | ||
| 276 | goto out_unregister; | ||
| 196 | break; | 277 | break; |
| 197 | 278 | ||
| 198 | case cheetah: | 279 | case cheetah: |
