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-rw-r--r--arch/sparc/include/asm/Kbuild2
-rw-r--r--arch/sparc/include/asm/asmmacro.h5
-rw-r--r--arch/sparc/include/asm/bpp.h73
-rw-r--r--arch/sparc/include/asm/bugs.h7
-rw-r--r--arch/sparc/include/asm/cpudata_64.h1
-rw-r--r--arch/sparc/include/asm/dma-mapping_32.h59
-rw-r--r--arch/sparc/include/asm/dma.h141
-rw-r--r--arch/sparc/include/asm/dma_32.h288
-rw-r--r--arch/sparc/include/asm/dma_64.h205
-rw-r--r--arch/sparc/include/asm/ebus.h8
-rw-r--r--arch/sparc/include/asm/ebus_32.h99
-rw-r--r--arch/sparc/include/asm/ebus_64.h95
-rw-r--r--arch/sparc/include/asm/ebus_dma.h35
-rw-r--r--arch/sparc/include/asm/elf_32.h7
-rw-r--r--arch/sparc/include/asm/fhc.h43
-rw-r--r--arch/sparc/include/asm/floppy_32.h16
-rw-r--r--arch/sparc/include/asm/floppy_64.h130
-rw-r--r--arch/sparc/include/asm/gpio.h36
-rw-r--r--arch/sparc/include/asm/io-unit.h4
-rw-r--r--arch/sparc/include/asm/io_32.h19
-rw-r--r--arch/sparc/include/asm/io_64.h22
-rw-r--r--arch/sparc/include/asm/iommu_64.h3
-rw-r--r--arch/sparc/include/asm/irq_64.h1
-rw-r--r--arch/sparc/include/asm/mc146818rtc_64.h10
-rw-r--r--arch/sparc/include/asm/memctrl.h9
-rw-r--r--arch/sparc/include/asm/mostek.h8
-rw-r--r--arch/sparc/include/asm/mostek_32.h171
-rw-r--r--arch/sparc/include/asm/mostek_64.h143
-rw-r--r--arch/sparc/include/asm/obio.h11
-rw-r--r--arch/sparc/include/asm/of_device.h2
-rw-r--r--arch/sparc/include/asm/of_platform.h3
-rw-r--r--arch/sparc/include/asm/oplib_32.h1
-rw-r--r--arch/sparc/include/asm/page_32.h5
-rw-r--r--arch/sparc/include/asm/page_64.h2
-rw-r--r--arch/sparc/include/asm/parport.h4
-rw-r--r--arch/sparc/include/asm/pci_32.h2
-rw-r--r--arch/sparc/include/asm/pgtable_32.h4
-rw-r--r--arch/sparc/include/asm/pgtable_64.h2
-rw-r--r--arch/sparc/include/asm/prom.h12
-rw-r--r--arch/sparc/include/asm/ptrace_64.h3
-rw-r--r--arch/sparc/include/asm/reboot.h6
-rw-r--r--arch/sparc/include/asm/rtc.h26
-rw-r--r--arch/sparc/include/asm/sbus.h8
-rw-r--r--arch/sparc/include/asm/sbus_32.h153
-rw-r--r--arch/sparc/include/asm/sbus_64.h190
-rw-r--r--arch/sparc/include/asm/spinlock_32.h2
-rw-r--r--arch/sparc/include/asm/spinlock_64.h2
-rw-r--r--arch/sparc/include/asm/sstate.h13
-rw-r--r--arch/sparc/include/asm/starfire.h1
-rw-r--r--arch/sparc/include/asm/sun4paddr.h56
-rw-r--r--arch/sparc/include/asm/sun4prom.h83
-rw-r--r--arch/sparc/include/asm/system_32.h9
-rw-r--r--arch/sparc/include/asm/system_64.h6
-rw-r--r--arch/sparc/include/asm/thread_info_32.h4
-rw-r--r--arch/sparc/include/asm/timer_32.h87
-rw-r--r--arch/sparc/include/asm/vac-ops.h7
-rw-r--r--arch/sparc/include/asm/vfc_ioctls.h58
-rw-r--r--arch/sparc/include/asm/visasm.h1
58 files changed, 409 insertions, 1994 deletions
diff --git a/arch/sparc/include/asm/Kbuild b/arch/sparc/include/asm/Kbuild
index 3f1cb7ad0d67..2d2769d766ec 100644
--- a/arch/sparc/include/asm/Kbuild
+++ b/arch/sparc/include/asm/Kbuild
@@ -20,7 +20,6 @@ header-y += unistd_64.h
20 20
21header-y += apc.h 21header-y += apc.h
22header-y += asi.h 22header-y += asi.h
23header-y += bpp.h
24header-y += display7seg.h 23header-y += display7seg.h
25header-y += envctrl.h 24header-y += envctrl.h
26header-y += fbio.h 25header-y += fbio.h
@@ -39,5 +38,4 @@ header-y += reg_64.h
39header-y += traps.h 38header-y += traps.h
40header-y += uctx.h 39header-y += uctx.h
41header-y += utrap.h 40header-y += utrap.h
42header-y += vfc_ioctls.h
43header-y += watchdog.h 41header-y += watchdog.h
diff --git a/arch/sparc/include/asm/asmmacro.h b/arch/sparc/include/asm/asmmacro.h
index a619a4d97aae..a995bf8aba3f 100644
--- a/arch/sparc/include/asm/asmmacro.h
+++ b/arch/sparc/include/asm/asmmacro.h
@@ -34,12 +34,7 @@
34/* sun4 probably wants half word accesses to ASI_SEGMAP, while sun4c+ 34/* sun4 probably wants half word accesses to ASI_SEGMAP, while sun4c+
35 likes byte accesses. These are to avoid ifdef mania. */ 35 likes byte accesses. These are to avoid ifdef mania. */
36 36
37#ifdef CONFIG_SUN4
38#define lduXa lduha
39#define stXa stha
40#else
41#define lduXa lduba 37#define lduXa lduba
42#define stXa stba 38#define stXa stba
43#endif
44 39
45#endif /* !(_SPARC_ASMMACRO_H) */ 40#endif /* !(_SPARC_ASMMACRO_H) */
diff --git a/arch/sparc/include/asm/bpp.h b/arch/sparc/include/asm/bpp.h
deleted file mode 100644
index 31f515e499a7..000000000000
--- a/arch/sparc/include/asm/bpp.h
+++ /dev/null
@@ -1,73 +0,0 @@
1#ifndef _SPARC_BPP_H
2#define _SPARC_BPP_H
3
4/*
5 * Copyright (c) 1995 Picture Elements
6 * Stephen Williams
7 * Gus Baldauf
8 *
9 * Linux/SPARC port by Peter Zaitcev.
10 * Integration into SPARC tree by Tom Dyas.
11 */
12
13#include <linux/ioctl.h>
14
15/*
16 * This is a driver that supports IEEE Std 1284-1994 communications
17 * with compliant or compatible devices. It will use whatever features
18 * the device supports, prefering those that are typically faster.
19 *
20 * When the device is opened, it is left in COMPATIBILITY mode, and
21 * writes work like any printer device. The driver only attempt to
22 * negotiate 1284 modes when needed so that plugs can be pulled,
23 * switch boxes switched, etc., without disrupting things. It will
24 * also leave the device in compatibility mode when closed.
25 */
26
27
28
29/*
30 * This driver also supplies ioctls to manually manipulate the
31 * pins. This is great for testing devices, or writing code to deal
32 * with bizzarro-mode of the ACME Special TurboThingy Plus.
33 *
34 * NOTE: These ioctl currently do not interact well with
35 * read/write. Caveat emptor.
36 *
37 * PUT_PINS allows us to assign the sense of all the pins, including
38 * the data pins if being driven by the host. The GET_PINS returns the
39 * pins that the peripheral drives, including data if appropriate.
40 */
41
42# define BPP_PUT_PINS _IOW('B', 1, int)
43# define BPP_GET_PINS _IOR('B', 2, char) /* that's bogus - should've been _IO */
44# define BPP_PUT_DATA _IOW('B', 3, int)
45# define BPP_GET_DATA _IOR('B', 4, char) /* ditto */
46
47/*
48 * Set the data bus to input mode. Disengage the data bin driver and
49 * be prepared to read values from the peripheral. If the arg is 0,
50 * then revert the bus to output mode.
51 */
52# define BPP_SET_INPUT _IOW('B', 5, int)
53
54/*
55 * These bits apply to the PUT operation...
56 */
57# define BPP_PP_nStrobe 0x0001
58# define BPP_PP_nAutoFd 0x0002
59# define BPP_PP_nInit 0x0004
60# define BPP_PP_nSelectIn 0x0008
61
62/*
63 * These apply to the GET operation, which also reads the current value
64 * of the previously put values. A bit mask of these will be returned
65 * as a bit mask in the return code of the ioctl().
66 */
67# define BPP_GP_nAck 0x0100
68# define BPP_GP_Busy 0x0200
69# define BPP_GP_PError 0x0400
70# define BPP_GP_Select 0x0800
71# define BPP_GP_nFault 0x1000
72
73#endif
diff --git a/arch/sparc/include/asm/bugs.h b/arch/sparc/include/asm/bugs.h
index e179bc12f64a..61d86bbbe2b2 100644
--- a/arch/sparc/include/asm/bugs.h
+++ b/arch/sparc/include/asm/bugs.h
@@ -7,10 +7,6 @@
7#include <asm/cpudata.h> 7#include <asm/cpudata.h>
8#endif 8#endif
9 9
10#ifdef CONFIG_SPARC64
11#include <asm/sstate.h>
12#endif
13
14extern unsigned long loops_per_jiffy; 10extern unsigned long loops_per_jiffy;
15 11
16static void __init check_bugs(void) 12static void __init check_bugs(void)
@@ -18,7 +14,4 @@ static void __init check_bugs(void)
18#if defined(CONFIG_SPARC32) && !defined(CONFIG_SMP) 14#if defined(CONFIG_SPARC32) && !defined(CONFIG_SMP)
19 cpu_data(0).udelay_val = loops_per_jiffy; 15 cpu_data(0).udelay_val = loops_per_jiffy;
20#endif 16#endif
21#ifdef CONFIG_SPARC64
22 sstate_running();
23#endif
24} 17}
diff --git a/arch/sparc/include/asm/cpudata_64.h b/arch/sparc/include/asm/cpudata_64.h
index 532975ecfe10..7da7c13d23c4 100644
--- a/arch/sparc/include/asm/cpudata_64.h
+++ b/arch/sparc/include/asm/cpudata_64.h
@@ -86,7 +86,6 @@ extern struct trap_per_cpu trap_block[NR_CPUS];
86extern void init_cur_cpu_trap(struct thread_info *); 86extern void init_cur_cpu_trap(struct thread_info *);
87extern void setup_tba(void); 87extern void setup_tba(void);
88extern int ncpus_probed; 88extern int ncpus_probed;
89extern void __init cpu_probe(void);
90extern const struct seq_operations cpuinfo_op; 89extern const struct seq_operations cpuinfo_op;
91 90
92extern unsigned long real_hard_smp_processor_id(void); 91extern unsigned long real_hard_smp_processor_id(void);
diff --git a/arch/sparc/include/asm/dma-mapping_32.h b/arch/sparc/include/asm/dma-mapping_32.h
index f3a641e6b2c8..8a57ea0573e6 100644
--- a/arch/sparc/include/asm/dma-mapping_32.h
+++ b/arch/sparc/include/asm/dma-mapping_32.h
@@ -1,11 +1,60 @@
1#ifndef _ASM_SPARC_DMA_MAPPING_H 1#ifndef _ASM_SPARC_DMA_MAPPING_H
2#define _ASM_SPARC_DMA_MAPPING_H 2#define _ASM_SPARC_DMA_MAPPING_H
3 3
4#include <linux/types.h>
4 5
5#ifdef CONFIG_PCI 6struct device;
6#include <asm-generic/dma-mapping.h> 7struct scatterlist;
7#else 8struct page;
8#include <asm-generic/dma-mapping-broken.h> 9
9#endif /* PCI */ 10#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
11
12extern int dma_supported(struct device *dev, u64 mask);
13extern int dma_set_mask(struct device *dev, u64 dma_mask);
14extern void *dma_alloc_coherent(struct device *dev, size_t size,
15 dma_addr_t *dma_handle, gfp_t flag);
16extern void dma_free_coherent(struct device *dev, size_t size,
17 void *cpu_addr, dma_addr_t dma_handle);
18extern dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
19 size_t size,
20 enum dma_data_direction direction);
21extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
22 size_t size,
23 enum dma_data_direction direction);
24extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
25 unsigned long offset, size_t size,
26 enum dma_data_direction direction);
27extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
28 size_t size, enum dma_data_direction direction);
29extern int dma_map_sg(struct device *dev, struct scatterlist *sg,
30 int nents, enum dma_data_direction direction);
31extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
32 int nents, enum dma_data_direction direction);
33extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
34 size_t size,
35 enum dma_data_direction direction);
36extern void dma_sync_single_for_device(struct device *dev,
37 dma_addr_t dma_handle,
38 size_t size,
39 enum dma_data_direction direction);
40extern void dma_sync_single_range_for_cpu(struct device *dev,
41 dma_addr_t dma_handle,
42 unsigned long offset,
43 size_t size,
44 enum dma_data_direction direction);
45extern void dma_sync_single_range_for_device(struct device *dev,
46 dma_addr_t dma_handle,
47 unsigned long offset, size_t size,
48 enum dma_data_direction direction);
49extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
50 int nelems, enum dma_data_direction direction);
51extern void dma_sync_sg_for_device(struct device *dev,
52 struct scatterlist *sg, int nelems,
53 enum dma_data_direction direction);
54extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
55extern int dma_get_cache_alignment(void);
56
57#define dma_alloc_noncoherent dma_alloc_coherent
58#define dma_free_noncoherent dma_free_coherent
10 59
11#endif /* _ASM_SPARC_DMA_MAPPING_H */ 60#endif /* _ASM_SPARC_DMA_MAPPING_H */
diff --git a/arch/sparc/include/asm/dma.h b/arch/sparc/include/asm/dma.h
index aa1d90ac04c5..b554927bbaf6 100644
--- a/arch/sparc/include/asm/dma.h
+++ b/arch/sparc/include/asm/dma.h
@@ -1,8 +1,139 @@
1#ifndef ___ASM_SPARC_DMA_H 1#ifndef _ASM_SPARC_DMA_H
2#define ___ASM_SPARC_DMA_H 2#define _ASM_SPARC_DMA_H
3#if defined(__sparc__) && defined(__arch64__) 3
4#include <asm/dma_64.h> 4/* These are irrelevant for Sparc DMA, but we leave it in so that
5 * things can compile.
6 */
7#define MAX_DMA_CHANNELS 8
8#define DMA_MODE_READ 1
9#define DMA_MODE_WRITE 2
10#define MAX_DMA_ADDRESS (~0UL)
11
12/* Useful constants */
13#define SIZE_16MB (16*1024*1024)
14#define SIZE_64K (64*1024)
15
16/* SBUS DMA controller reg offsets */
17#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
18#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
19#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
20#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
21
22/* Fields in the cond_reg register */
23/* First, the version identification bits */
24#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
25#define DMA_VERS0 0x00000000 /* Sunray DMA version */
26#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
27#define DMA_VERS1 0x80000000 /* DMA rev 1 */
28#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
29#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
30#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
31
32#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
33#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
34#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
35#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
36#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
37#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
38#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
39#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
40#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
41#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
42#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
43#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
44#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
45#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
46#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
47#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
48#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
49#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
50#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
51#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
52#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
53#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
54#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
55#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
56#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
57#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
58#define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
59#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
60#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
61#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
62#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
63#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
64#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
65#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
66#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
67#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
68#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
69#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
70#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
71#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
72#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
73
74/* Values describing the burst-size property from the PROM */
75#define DMA_BURST1 0x01
76#define DMA_BURST2 0x02
77#define DMA_BURST4 0x04
78#define DMA_BURST8 0x08
79#define DMA_BURST16 0x10
80#define DMA_BURST32 0x20
81#define DMA_BURST64 0x40
82#define DMA_BURSTBITS 0x7f
83
84/* From PCI */
85
86#ifdef CONFIG_PCI
87extern int isa_dma_bridge_buggy;
5#else 88#else
6#include <asm/dma_32.h> 89#define isa_dma_bridge_buggy (0)
7#endif 90#endif
91
92#ifdef CONFIG_SPARC32
93
94/* Routines for data transfer buffers. */
95BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
96BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long)
97
98#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
99#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
100
101struct page;
102struct device;
103struct scatterlist;
104
105/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */
106BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, struct device *, char *, unsigned long)
107BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct device *, struct scatterlist *, int)
108BTFIXUPDEF_CALL(void, mmu_release_scsi_one, struct device *, __u32, unsigned long)
109BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct device *, struct scatterlist *, int)
110
111#define mmu_get_scsi_one(dev,vaddr,len) BTFIXUP_CALL(mmu_get_scsi_one)(dev,vaddr,len)
112#define mmu_get_scsi_sgl(dev,sg,sz) BTFIXUP_CALL(mmu_get_scsi_sgl)(dev,sg,sz)
113#define mmu_release_scsi_one(dev,vaddr,len) BTFIXUP_CALL(mmu_release_scsi_one)(dev,vaddr,len)
114#define mmu_release_scsi_sgl(dev,sg,sz) BTFIXUP_CALL(mmu_release_scsi_sgl)(dev,sg,sz)
115
116/*
117 * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
118 *
119 * The mmu_map_dma_area establishes two mappings in one go.
120 * These mappings point to pages normally mapped at 'va' (linear address).
121 * First mapping is for CPU visible address at 'a', uncached.
122 * This is an alias, but it works because it is an uncached mapping.
123 * Second mapping is for device visible address, or "bus" address.
124 * The bus address is returned at '*pba'.
125 *
126 * These functions seem distinct, but are hard to split. On sun4c,
127 * at least for now, 'a' is equal to bus address, and retured in *pba.
128 * On sun4m, page attributes depend on the CPU type, so we have to
129 * know if we are mapping RAM or I/O, so it has to be an additional argument
130 * to a separate mapping function for CPU visible mappings.
131 */
132BTFIXUPDEF_CALL(int, mmu_map_dma_area, struct device *, dma_addr_t *, unsigned long, unsigned long, int len)
133BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, struct device *, unsigned long busa, int len)
134
135#define mmu_map_dma_area(dev,pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(dev,pba,va,a,len)
136#define mmu_unmap_dma_area(dev,ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(dev,ba,len)
8#endif 137#endif
138
139#endif /* !(_ASM_SPARC_DMA_H) */
diff --git a/arch/sparc/include/asm/dma_32.h b/arch/sparc/include/asm/dma_32.h
deleted file mode 100644
index cf7189c0079b..000000000000
--- a/arch/sparc/include/asm/dma_32.h
+++ /dev/null
@@ -1,288 +0,0 @@
1/* include/asm/dma.h
2 *
3 * Copyright 1995 (C) David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _ASM_SPARC_DMA_H
7#define _ASM_SPARC_DMA_H
8
9#include <linux/kernel.h>
10#include <linux/types.h>
11
12#include <asm/vac-ops.h> /* for invalidate's, etc. */
13#include <asm/sbus.h>
14#include <asm/delay.h>
15#include <asm/oplib.h>
16#include <asm/system.h>
17#include <asm/io.h>
18#include <linux/spinlock.h>
19
20struct page;
21extern spinlock_t dma_spin_lock;
22
23static inline unsigned long claim_dma_lock(void)
24{
25 unsigned long flags;
26 spin_lock_irqsave(&dma_spin_lock, flags);
27 return flags;
28}
29
30static inline void release_dma_lock(unsigned long flags)
31{
32 spin_unlock_irqrestore(&dma_spin_lock, flags);
33}
34
35/* These are irrelevant for Sparc DMA, but we leave it in so that
36 * things can compile.
37 */
38#define MAX_DMA_CHANNELS 8
39#define MAX_DMA_ADDRESS (~0UL)
40#define DMA_MODE_READ 1
41#define DMA_MODE_WRITE 2
42
43/* Useful constants */
44#define SIZE_16MB (16*1024*1024)
45#define SIZE_64K (64*1024)
46
47/* SBUS DMA controller reg offsets */
48#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
49#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
50#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
51#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
52
53/* DVMA chip revisions */
54enum dvma_rev {
55 dvmarev0,
56 dvmaesc1,
57 dvmarev1,
58 dvmarev2,
59 dvmarev3,
60 dvmarevplus,
61 dvmahme
62};
63
64#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
65
66/* Linux DMA information structure, filled during probe. */
67struct sbus_dma {
68 struct sbus_dma *next;
69 struct sbus_dev *sdev;
70 void __iomem *regs;
71
72 /* Status, misc info */
73 int node; /* Prom node for this DMA device */
74 int running; /* Are we doing DMA now? */
75 int allocated; /* Are we "owned" by anyone yet? */
76
77 /* Transfer information. */
78 unsigned long addr; /* Start address of current transfer */
79 int nbytes; /* Size of current transfer */
80 int realbytes; /* For splitting up large transfers, etc. */
81
82 /* DMA revision */
83 enum dvma_rev revision;
84};
85
86extern struct sbus_dma *dma_chain;
87
88/* Broken hardware... */
89#ifdef CONFIG_SUN4
90/* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken?
91 * Or is rev0 present only on sun4 boxes? -jj */
92#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1)
93#else
94#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
95#endif
96#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
97
98/* Main routines in dma.c */
99extern void dvma_init(struct sbus_bus *);
100
101/* Fields in the cond_reg register */
102/* First, the version identification bits */
103#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
104#define DMA_VERS0 0x00000000 /* Sunray DMA version */
105#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
106#define DMA_VERS1 0x80000000 /* DMA rev 1 */
107#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
108#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
109#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
110
111#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
112#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
113#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
114#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
115#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
116#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
117#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
118#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
119#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
120#define DMA_RST_BPP DMA_RST_SCSI /* Reset the BPP controller */
121#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
122#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
123#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
124#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
125#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
126#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
127#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
128#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
129#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
130#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
131#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
132#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
133#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
134#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
135#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
136#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
137#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
138#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
139#define DMA_BRST32 0x00040000 /* SCSI/BPP: 32byte bursts */
140#define DMA_BRST16 0x00000000 /* SCSI/BPP: 16byte bursts */
141#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
142#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
143#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
144#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
145#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
146#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
147#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
148#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
149#define DMA_BPP_ON DMA_SCSI_ON /* Enable BPP dma */
150#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
151#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
152#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
153#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
154
155/* Values describing the burst-size property from the PROM */
156#define DMA_BURST1 0x01
157#define DMA_BURST2 0x02
158#define DMA_BURST4 0x04
159#define DMA_BURST8 0x08
160#define DMA_BURST16 0x10
161#define DMA_BURST32 0x20
162#define DMA_BURST64 0x40
163#define DMA_BURSTBITS 0x7f
164
165/* Determine highest possible final transfer address given a base */
166#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
167
168/* Yes, I hack a lot of elisp in my spare time... */
169#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
170#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
171#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
172#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
173#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
174#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
175#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
176#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
177#define DMA_BEGINDMA_W(regs) \
178 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
179#define DMA_BEGINDMA_R(regs) \
180 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
181
182/* For certain DMA chips, we need to disable ints upon irq entry
183 * and turn them back on when we are done. So in any ESP interrupt
184 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
185 * when leaving the handler. You have been warned...
186 */
187#define DMA_IRQ_ENTRY(dma, dregs) do { \
188 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
189 } while (0)
190
191#define DMA_IRQ_EXIT(dma, dregs) do { \
192 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
193 } while(0)
194
195#if 0 /* P3 this stuff is inline in ledma.c:init_restart_ledma() */
196/* Pause until counter runs out or BIT isn't set in the DMA condition
197 * register.
198 */
199static inline void sparc_dma_pause(struct sparc_dma_registers *regs,
200 unsigned long bit)
201{
202 int ctr = 50000; /* Let's find some bugs ;) */
203
204 /* Busy wait until the bit is not set any more */
205 while((regs->cond_reg&bit) && (ctr>0)) {
206 ctr--;
207 __delay(5);
208 }
209
210 /* Check for bogus outcome. */
211 if(!ctr)
212 panic("DMA timeout");
213}
214
215/* Reset the friggin' thing... */
216#define DMA_RESET(dma) do { \
217 struct sparc_dma_registers *regs = dma->regs; \
218 /* Let the current FIFO drain itself */ \
219 sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
220 /* Reset the logic */ \
221 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
222 __delay(400); /* let the bits set ;) */ \
223 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
224 sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
225 /* Enable FAST transfers if available */ \
226 if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
227 dma->running = 0; \
228} while(0)
229#endif
230
231#define for_each_dvma(dma) \
232 for((dma) = dma_chain; (dma); (dma) = (dma)->next)
233
234extern int get_dma_list(char *);
235extern int request_dma(unsigned int, __const__ char *);
236extern void free_dma(unsigned int);
237
238/* From PCI */
239
240#ifdef CONFIG_PCI
241extern int isa_dma_bridge_buggy;
242#else
243#define isa_dma_bridge_buggy (0)
244#endif
245
246/* Routines for data transfer buffers. */
247BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
248BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long)
249
250#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
251#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
252
253/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */
254BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, char *, unsigned long, struct sbus_bus *sbus)
255BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
256BTFIXUPDEF_CALL(void, mmu_release_scsi_one, __u32, unsigned long, struct sbus_bus *sbus)
257BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
258
259#define mmu_get_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_get_scsi_one)(vaddr,len,sbus)
260#define mmu_get_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_get_scsi_sgl)(sg,sz,sbus)
261#define mmu_release_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_release_scsi_one)(vaddr,len,sbus)
262#define mmu_release_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_release_scsi_sgl)(sg,sz,sbus)
263
264/*
265 * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
266 *
267 * The mmu_map_dma_area establishes two mappings in one go.
268 * These mappings point to pages normally mapped at 'va' (linear address).
269 * First mapping is for CPU visible address at 'a', uncached.
270 * This is an alias, but it works because it is an uncached mapping.
271 * Second mapping is for device visible address, or "bus" address.
272 * The bus address is returned at '*pba'.
273 *
274 * These functions seem distinct, but are hard to split. On sun4c,
275 * at least for now, 'a' is equal to bus address, and retured in *pba.
276 * On sun4m, page attributes depend on the CPU type, so we have to
277 * know if we are mapping RAM or I/O, so it has to be an additional argument
278 * to a separate mapping function for CPU visible mappings.
279 */
280BTFIXUPDEF_CALL(int, mmu_map_dma_area, dma_addr_t *, unsigned long, unsigned long, int len)
281BTFIXUPDEF_CALL(struct page *, mmu_translate_dvma, unsigned long busa)
282BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, unsigned long busa, int len)
283
284#define mmu_map_dma_area(pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(pba,va,a,len)
285#define mmu_unmap_dma_area(ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(ba,len)
286#define mmu_translate_dvma(ba) BTFIXUP_CALL(mmu_translate_dvma)(ba)
287
288#endif /* !(_ASM_SPARC_DMA_H) */
diff --git a/arch/sparc/include/asm/dma_64.h b/arch/sparc/include/asm/dma_64.h
deleted file mode 100644
index 46a8aecffc02..000000000000
--- a/arch/sparc/include/asm/dma_64.h
+++ /dev/null
@@ -1,205 +0,0 @@
1/*
2 * include/asm/dma.h
3 *
4 * Copyright 1996 (C) David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _ASM_SPARC64_DMA_H
8#define _ASM_SPARC64_DMA_H
9
10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/spinlock.h>
13
14#include <asm/sbus.h>
15#include <asm/delay.h>
16#include <asm/oplib.h>
17
18/* These are irrelevant for Sparc DMA, but we leave it in so that
19 * things can compile.
20 */
21#define MAX_DMA_CHANNELS 8
22#define DMA_MODE_READ 1
23#define DMA_MODE_WRITE 2
24#define MAX_DMA_ADDRESS (~0UL)
25
26/* Useful constants */
27#define SIZE_16MB (16*1024*1024)
28#define SIZE_64K (64*1024)
29
30/* SBUS DMA controller reg offsets */
31#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
32#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
33#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
34#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
35
36/* DVMA chip revisions */
37enum dvma_rev {
38 dvmarev0,
39 dvmaesc1,
40 dvmarev1,
41 dvmarev2,
42 dvmarev3,
43 dvmarevplus,
44 dvmahme
45};
46
47#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
48
49/* Linux DMA information structure, filled during probe. */
50struct sbus_dma {
51 struct sbus_dma *next;
52 struct sbus_dev *sdev;
53 void __iomem *regs;
54
55 /* Status, misc info */
56 int node; /* Prom node for this DMA device */
57 int running; /* Are we doing DMA now? */
58 int allocated; /* Are we "owned" by anyone yet? */
59
60 /* Transfer information. */
61 u32 addr; /* Start address of current transfer */
62 int nbytes; /* Size of current transfer */
63 int realbytes; /* For splitting up large transfers, etc. */
64
65 /* DMA revision */
66 enum dvma_rev revision;
67};
68
69extern struct sbus_dma *dma_chain;
70
71/* Broken hardware... */
72#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
73#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
74
75/* Main routines in dma.c */
76extern void dvma_init(struct sbus_bus *);
77
78/* Fields in the cond_reg register */
79/* First, the version identification bits */
80#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
81#define DMA_VERS0 0x00000000 /* Sunray DMA version */
82#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
83#define DMA_VERS1 0x80000000 /* DMA rev 1 */
84#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
85#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
86#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
87
88#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
89#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
90#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
91#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
92#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
93#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
94#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
95#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
96#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
97#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
98#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
99#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
100#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
101#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
102#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
103#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
104#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
105#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
106#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
107#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
108#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
109#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
110#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
111#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
112#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
113#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
114#define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
115#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
116#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
117#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
118#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
119#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
120#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
121#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
122#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
123#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
124#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
125#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
126#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
127#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
128#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
129
130/* Values describing the burst-size property from the PROM */
131#define DMA_BURST1 0x01
132#define DMA_BURST2 0x02
133#define DMA_BURST4 0x04
134#define DMA_BURST8 0x08
135#define DMA_BURST16 0x10
136#define DMA_BURST32 0x20
137#define DMA_BURST64 0x40
138#define DMA_BURSTBITS 0x7f
139
140/* Determine highest possible final transfer address given a base */
141#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
142
143/* Yes, I hack a lot of elisp in my spare time... */
144#define DMA_ERROR_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_HNDL_ERROR))
145#define DMA_IRQ_P(regs) ((sbus_readl((regs) + DMA_CSR)) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
146#define DMA_WRITE_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_ST_WRITE))
147#define DMA_OFF(__regs) \
148do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
149 tmp &= ~DMA_ENABLE; \
150 sbus_writel(tmp, (__regs) + DMA_CSR); \
151} while(0)
152#define DMA_INTSOFF(__regs) \
153do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
154 tmp &= ~DMA_INT_ENAB; \
155 sbus_writel(tmp, (__regs) + DMA_CSR); \
156} while(0)
157#define DMA_INTSON(__regs) \
158do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
159 tmp |= DMA_INT_ENAB; \
160 sbus_writel(tmp, (__regs) + DMA_CSR); \
161} while(0)
162#define DMA_PUNTFIFO(__regs) \
163do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
164 tmp |= DMA_FIFO_INV; \
165 sbus_writel(tmp, (__regs) + DMA_CSR); \
166} while(0)
167#define DMA_SETSTART(__regs, __addr) \
168 sbus_writel((u32)(__addr), (__regs) + DMA_ADDR);
169#define DMA_BEGINDMA_W(__regs) \
170do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
171 tmp |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB); \
172 sbus_writel(tmp, (__regs) + DMA_CSR); \
173} while(0)
174#define DMA_BEGINDMA_R(__regs) \
175do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
176 tmp |= (DMA_ENABLE|DMA_INT_ENAB); \
177 tmp &= ~DMA_ST_WRITE; \
178 sbus_writel(tmp, (__regs) + DMA_CSR); \
179} while(0)
180
181/* For certain DMA chips, we need to disable ints upon irq entry
182 * and turn them back on when we are done. So in any ESP interrupt
183 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
184 * when leaving the handler. You have been warned...
185 */
186#define DMA_IRQ_ENTRY(dma, dregs) do { \
187 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
188 } while (0)
189
190#define DMA_IRQ_EXIT(dma, dregs) do { \
191 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
192 } while(0)
193
194#define for_each_dvma(dma) \
195 for((dma) = dma_chain; (dma); (dma) = (dma)->next)
196
197/* From PCI */
198
199#ifdef CONFIG_PCI
200extern int isa_dma_bridge_buggy;
201#else
202#define isa_dma_bridge_buggy (0)
203#endif
204
205#endif /* !(_ASM_SPARC64_DMA_H) */
diff --git a/arch/sparc/include/asm/ebus.h b/arch/sparc/include/asm/ebus.h
deleted file mode 100644
index 83a6d16c22e6..000000000000
--- a/arch/sparc/include/asm/ebus.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_EBUS_H
2#define ___ASM_SPARC_EBUS_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm/ebus_64.h>
5#else
6#include <asm/ebus_32.h>
7#endif
8#endif
diff --git a/arch/sparc/include/asm/ebus_32.h b/arch/sparc/include/asm/ebus_32.h
deleted file mode 100644
index f91f0b267ce1..000000000000
--- a/arch/sparc/include/asm/ebus_32.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * ebus.h: PCI to Ebus pseudo driver software state.
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 *
6 * Adopted for sparc by V. Roganov and G. Raiko.
7 */
8
9#ifndef __SPARC_EBUS_H
10#define __SPARC_EBUS_H
11
12#ifndef _LINUX_IOPORT_H
13#include <linux/ioport.h>
14#endif
15#include <linux/of_device.h>
16#include <asm/oplib.h>
17#include <asm/prom.h>
18
19struct linux_ebus_child {
20 struct linux_ebus_child *next;
21 struct linux_ebus_device *parent;
22 struct linux_ebus *bus;
23 struct device_node *prom_node;
24 struct resource resource[PROMREG_MAX];
25 int num_addrs;
26 unsigned int irqs[PROMINTR_MAX];
27 int num_irqs;
28};
29
30struct linux_ebus_device {
31 struct of_device ofdev;
32 struct linux_ebus_device *next;
33 struct linux_ebus_child *children;
34 struct linux_ebus *bus;
35 struct device_node *prom_node;
36 struct resource resource[PROMREG_MAX];
37 int num_addrs;
38 unsigned int irqs[PROMINTR_MAX];
39 int num_irqs;
40};
41#define to_ebus_device(d) container_of(d, struct linux_ebus_device, ofdev.dev)
42
43struct linux_ebus {
44 struct of_device ofdev;
45 struct linux_ebus *next;
46 struct linux_ebus_device *devices;
47 struct linux_pbm_info *parent;
48 struct pci_dev *self;
49 struct device_node *prom_node;
50};
51#define to_ebus(d) container_of(d, struct linux_ebus, ofdev.dev)
52
53struct linux_ebus_dma {
54 unsigned int dcsr;
55 unsigned int dacr;
56 unsigned int dbcr;
57};
58
59#define EBUS_DCSR_INT_PEND 0x00000001
60#define EBUS_DCSR_ERR_PEND 0x00000002
61#define EBUS_DCSR_DRAIN 0x00000004
62#define EBUS_DCSR_INT_EN 0x00000010
63#define EBUS_DCSR_RESET 0x00000080
64#define EBUS_DCSR_WRITE 0x00000100
65#define EBUS_DCSR_EN_DMA 0x00000200
66#define EBUS_DCSR_CYC_PEND 0x00000400
67#define EBUS_DCSR_DIAG_RD_DONE 0x00000800
68#define EBUS_DCSR_DIAG_WR_DONE 0x00001000
69#define EBUS_DCSR_EN_CNT 0x00002000
70#define EBUS_DCSR_TC 0x00004000
71#define EBUS_DCSR_DIS_CSR_DRN 0x00010000
72#define EBUS_DCSR_BURST_SZ_MASK 0x000c0000
73#define EBUS_DCSR_BURST_SZ_1 0x00080000
74#define EBUS_DCSR_BURST_SZ_4 0x00000000
75#define EBUS_DCSR_BURST_SZ_8 0x00040000
76#define EBUS_DCSR_BURST_SZ_16 0x000c0000
77#define EBUS_DCSR_DIAG_EN 0x00100000
78#define EBUS_DCSR_DIS_ERR_PEND 0x00400000
79#define EBUS_DCSR_TCI_DIS 0x00800000
80#define EBUS_DCSR_EN_NEXT 0x01000000
81#define EBUS_DCSR_DMA_ON 0x02000000
82#define EBUS_DCSR_A_LOADED 0x04000000
83#define EBUS_DCSR_NA_LOADED 0x08000000
84#define EBUS_DCSR_DEV_ID_MASK 0xf0000000
85
86extern struct linux_ebus *ebus_chain;
87
88extern void ebus_init(void);
89
90#define for_each_ebus(bus) \
91 for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
92
93#define for_each_ebusdev(dev, bus) \
94 for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
95
96#define for_each_edevchild(dev, child) \
97 for((child) = (dev)->children; (child); (child) = (child)->next)
98
99#endif /* !(__SPARC_EBUS_H) */
diff --git a/arch/sparc/include/asm/ebus_64.h b/arch/sparc/include/asm/ebus_64.h
deleted file mode 100644
index 14c6a111f60c..000000000000
--- a/arch/sparc/include/asm/ebus_64.h
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * ebus.h: PCI to Ebus pseudo driver software state.
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
6 */
7
8#ifndef __SPARC64_EBUS_H
9#define __SPARC64_EBUS_H
10
11#include <linux/of_device.h>
12
13#include <asm/oplib.h>
14#include <asm/prom.h>
15
16struct linux_ebus_child {
17 struct linux_ebus_child *next;
18 struct linux_ebus_device *parent;
19 struct linux_ebus *bus;
20 struct device_node *prom_node;
21 struct resource resource[PROMREG_MAX];
22 int num_addrs;
23 unsigned int irqs[PROMINTR_MAX];
24 int num_irqs;
25};
26
27struct linux_ebus_device {
28 struct of_device ofdev;
29 struct linux_ebus_device *next;
30 struct linux_ebus_child *children;
31 struct linux_ebus *bus;
32 struct device_node *prom_node;
33 struct resource resource[PROMREG_MAX];
34 int num_addrs;
35 unsigned int irqs[PROMINTR_MAX];
36 int num_irqs;
37};
38#define to_ebus_device(d) container_of(d, struct linux_ebus_device, ofdev.dev)
39
40struct linux_ebus {
41 struct of_device ofdev;
42 struct linux_ebus *next;
43 struct linux_ebus_device *devices;
44 struct pci_dev *self;
45 int index;
46 int is_rio;
47 struct device_node *prom_node;
48};
49#define to_ebus(d) container_of(d, struct linux_ebus, ofdev.dev)
50
51struct ebus_dma_info {
52 spinlock_t lock;
53 void __iomem *regs;
54
55 unsigned int flags;
56#define EBUS_DMA_FLAG_USE_EBDMA_HANDLER 0x00000001
57#define EBUS_DMA_FLAG_TCI_DISABLE 0x00000002
58
59 /* These are only valid is EBUS_DMA_FLAG_USE_EBDMA_HANDLER is
60 * set.
61 */
62 void (*callback)(struct ebus_dma_info *p, int event, void *cookie);
63 void *client_cookie;
64 unsigned int irq;
65#define EBUS_DMA_EVENT_ERROR 1
66#define EBUS_DMA_EVENT_DMA 2
67#define EBUS_DMA_EVENT_DEVICE 4
68
69 unsigned char name[64];
70};
71
72extern int ebus_dma_register(struct ebus_dma_info *p);
73extern int ebus_dma_irq_enable(struct ebus_dma_info *p, int on);
74extern void ebus_dma_unregister(struct ebus_dma_info *p);
75extern int ebus_dma_request(struct ebus_dma_info *p, dma_addr_t bus_addr,
76 size_t len);
77extern void ebus_dma_prepare(struct ebus_dma_info *p, int write);
78extern unsigned int ebus_dma_residue(struct ebus_dma_info *p);
79extern unsigned int ebus_dma_addr(struct ebus_dma_info *p);
80extern void ebus_dma_enable(struct ebus_dma_info *p, int on);
81
82extern struct linux_ebus *ebus_chain;
83
84extern void ebus_init(void);
85
86#define for_each_ebus(bus) \
87 for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
88
89#define for_each_ebusdev(dev, bus) \
90 for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
91
92#define for_each_edevchild(dev, child) \
93 for((child) = (dev)->children; (child); (child) = (child)->next)
94
95#endif /* !(__SPARC64_EBUS_H) */
diff --git a/arch/sparc/include/asm/ebus_dma.h b/arch/sparc/include/asm/ebus_dma.h
new file mode 100644
index 000000000000..f07a5b541c98
--- /dev/null
+++ b/arch/sparc/include/asm/ebus_dma.h
@@ -0,0 +1,35 @@
1#ifndef __ASM_SPARC_EBUS_DMA_H
2#define __ASM_SPARC_EBUS_DMA_H
3
4struct ebus_dma_info {
5 spinlock_t lock;
6 void __iomem *regs;
7
8 unsigned int flags;
9#define EBUS_DMA_FLAG_USE_EBDMA_HANDLER 0x00000001
10#define EBUS_DMA_FLAG_TCI_DISABLE 0x00000002
11
12 /* These are only valid is EBUS_DMA_FLAG_USE_EBDMA_HANDLER is
13 * set.
14 */
15 void (*callback)(struct ebus_dma_info *p, int event, void *cookie);
16 void *client_cookie;
17 unsigned int irq;
18#define EBUS_DMA_EVENT_ERROR 1
19#define EBUS_DMA_EVENT_DMA 2
20#define EBUS_DMA_EVENT_DEVICE 4
21
22 unsigned char name[64];
23};
24
25extern int ebus_dma_register(struct ebus_dma_info *p);
26extern int ebus_dma_irq_enable(struct ebus_dma_info *p, int on);
27extern void ebus_dma_unregister(struct ebus_dma_info *p);
28extern int ebus_dma_request(struct ebus_dma_info *p, dma_addr_t bus_addr,
29 size_t len);
30extern void ebus_dma_prepare(struct ebus_dma_info *p, int write);
31extern unsigned int ebus_dma_residue(struct ebus_dma_info *p);
32extern unsigned int ebus_dma_addr(struct ebus_dma_info *p);
33extern void ebus_dma_enable(struct ebus_dma_info *p, int on);
34
35#endif /* __ASM_SPARC_EBUS_DMA_H */
diff --git a/arch/sparc/include/asm/elf_32.h b/arch/sparc/include/asm/elf_32.h
index d043f80bc2fd..b7ab60547827 100644
--- a/arch/sparc/include/asm/elf_32.h
+++ b/arch/sparc/include/asm/elf_32.h
@@ -105,11 +105,8 @@ typedef struct {
105#define ELF_DATA ELFDATA2MSB 105#define ELF_DATA ELFDATA2MSB
106 106
107#define USE_ELF_CORE_DUMP 107#define USE_ELF_CORE_DUMP
108#ifndef CONFIG_SUN4 108
109#define ELF_EXEC_PAGESIZE 4096 109#define ELF_EXEC_PAGESIZE 4096
110#else
111#define ELF_EXEC_PAGESIZE 8192
112#endif
113 110
114 111
115/* This is the location that an ET_DYN program is loaded if exec'ed. Typical 112/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
@@ -126,7 +123,7 @@ typedef struct {
126/* Sun4c has none of the capabilities, most sun4m's have them all. 123/* Sun4c has none of the capabilities, most sun4m's have them all.
127 * XXX This is gross, set some global variable at boot time. -DaveM 124 * XXX This is gross, set some global variable at boot time. -DaveM
128 */ 125 */
129#define ELF_HWCAP ((ARCH_SUN4C_SUN4) ? 0 : \ 126#define ELF_HWCAP ((ARCH_SUN4C) ? 0 : \
130 (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \ 127 (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \
131 HWCAP_SPARC_SWAP | \ 128 HWCAP_SPARC_SWAP | \
132 ((srmmu_modtype != Cypress && \ 129 ((srmmu_modtype != Cypress && \
diff --git a/arch/sparc/include/asm/fhc.h b/arch/sparc/include/asm/fhc.h
index 788cbc46a116..57f1b303ad54 100644
--- a/arch/sparc/include/asm/fhc.h
+++ b/arch/sparc/include/asm/fhc.h
@@ -1,5 +1,4 @@
1/* 1/* fhc.h: FHC and Clock board register definitions.
2 * fhc.h: Structures for central/fhc pseudo driver on Sunfire/Starfire/Wildfire.
3 * 2 *
4 * Copyright (C) 1997, 1999 David S. Miller (davem@redhat.com) 3 * Copyright (C) 1997, 1999 David S. Miller (davem@redhat.com)
5 */ 4 */
@@ -7,14 +6,6 @@
7#ifndef _SPARC64_FHC_H 6#ifndef _SPARC64_FHC_H
8#define _SPARC64_FHC_H 7#define _SPARC64_FHC_H
9 8
10#include <linux/timer.h>
11
12#include <asm/oplib.h>
13#include <asm/prom.h>
14#include <asm/upa.h>
15
16struct linux_fhc;
17
18/* Clock board register offsets. */ 9/* Clock board register offsets. */
19#define CLOCK_CTRL 0x00UL /* Main control */ 10#define CLOCK_CTRL 0x00UL /* Main control */
20#define CLOCK_STAT1 0x10UL /* Status one */ 11#define CLOCK_STAT1 0x10UL /* Status one */
@@ -29,21 +20,7 @@ struct linux_fhc;
29#define CLOCK_CTRL_MLED 0x02 /* Mid LED, 1 == on */ 20#define CLOCK_CTRL_MLED 0x02 /* Mid LED, 1 == on */
30#define CLOCK_CTRL_RLED 0x01 /* RIght LED, 1 == on */ 21#define CLOCK_CTRL_RLED 0x01 /* RIght LED, 1 == on */
31 22
32struct linux_central {
33 struct linux_fhc *child;
34 unsigned long cfreg;
35 unsigned long clkregs;
36 unsigned long clkver;
37 int slots;
38 struct device_node *prom_node;
39
40 struct linux_prom_ranges central_ranges[PROMREG_MAX];
41 int num_central_ranges;
42};
43
44/* Firehose controller register offsets */ 23/* Firehose controller register offsets */
45struct fhc_regs {
46 unsigned long pregs; /* FHC internal regs */
47#define FHC_PREGS_ID 0x00UL /* FHC ID */ 24#define FHC_PREGS_ID 0x00UL /* FHC ID */
48#define FHC_ID_VERS 0xf0000000 /* Version of this FHC */ 25#define FHC_ID_VERS 0xf0000000 /* Version of this FHC */
49#define FHC_ID_PARTID 0x0ffff000 /* Part ID code (0x0f9f == FHC) */ 26#define FHC_ID_PARTID 0x0ffff000 /* Part ID code (0x0f9f == FHC) */
@@ -90,32 +67,14 @@ struct fhc_regs {
90#define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */ 67#define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */
91#define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */ 68#define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */
92#define FHC_PREGS_JCMD 0x100UL /* FHC JTAG Command Register */ 69#define FHC_PREGS_JCMD 0x100UL /* FHC JTAG Command Register */
93 unsigned long ireg; /* FHC IGN reg */
94#define FHC_IREG_IGN 0x00UL /* This FHC's IGN */ 70#define FHC_IREG_IGN 0x00UL /* This FHC's IGN */
95 unsigned long ffregs; /* FHC fanfail regs */
96#define FHC_FFREGS_IMAP 0x00UL /* FHC Fanfail IMAP */ 71#define FHC_FFREGS_IMAP 0x00UL /* FHC Fanfail IMAP */
97#define FHC_FFREGS_ICLR 0x10UL /* FHC Fanfail ICLR */ 72#define FHC_FFREGS_ICLR 0x10UL /* FHC Fanfail ICLR */
98 unsigned long sregs; /* FHC system regs */
99#define FHC_SREGS_IMAP 0x00UL /* FHC System IMAP */ 73#define FHC_SREGS_IMAP 0x00UL /* FHC System IMAP */
100#define FHC_SREGS_ICLR 0x10UL /* FHC System ICLR */ 74#define FHC_SREGS_ICLR 0x10UL /* FHC System ICLR */
101 unsigned long uregs; /* FHC uart regs */
102#define FHC_UREGS_IMAP 0x00UL /* FHC Uart IMAP */ 75#define FHC_UREGS_IMAP 0x00UL /* FHC Uart IMAP */
103#define FHC_UREGS_ICLR 0x10UL /* FHC Uart ICLR */ 76#define FHC_UREGS_ICLR 0x10UL /* FHC Uart ICLR */
104 unsigned long tregs; /* FHC TOD regs */
105#define FHC_TREGS_IMAP 0x00UL /* FHC TOD IMAP */ 77#define FHC_TREGS_IMAP 0x00UL /* FHC TOD IMAP */
106#define FHC_TREGS_ICLR 0x10UL /* FHC TOD ICLR */ 78#define FHC_TREGS_ICLR 0x10UL /* FHC TOD ICLR */
107};
108
109struct linux_fhc {
110 struct linux_fhc *next;
111 struct linux_central *parent; /* NULL if not central FHC */
112 struct fhc_regs fhc_regs;
113 int board;
114 int jtag_master;
115 struct device_node *prom_node;
116
117 struct linux_prom_ranges fhc_ranges[PROMREG_MAX];
118 int num_fhc_ranges;
119};
120 79
121#endif /* !(_SPARC64_FHC_H) */ 80#endif /* !(_SPARC64_FHC_H) */
diff --git a/arch/sparc/include/asm/floppy_32.h b/arch/sparc/include/asm/floppy_32.h
index ae3f00bf22ff..c792830636de 100644
--- a/arch/sparc/include/asm/floppy_32.h
+++ b/arch/sparc/include/asm/floppy_32.h
@@ -6,6 +6,9 @@
6#ifndef __ASM_SPARC_FLOPPY_H 6#ifndef __ASM_SPARC_FLOPPY_H
7#define __ASM_SPARC_FLOPPY_H 7#define __ASM_SPARC_FLOPPY_H
8 8
9#include <linux/of.h>
10#include <linux/of_device.h>
11
9#include <asm/page.h> 12#include <asm/page.h>
10#include <asm/pgtable.h> 13#include <asm/pgtable.h>
11#include <asm/system.h> 14#include <asm/system.h>
@@ -343,7 +346,7 @@ static int sun_floppy_init(void)
343 r.flags = fd_regs[0].which_io; 346 r.flags = fd_regs[0].which_io;
344 r.start = fd_regs[0].phys_addr; 347 r.start = fd_regs[0].phys_addr;
345 sun_fdc = (struct sun_flpy_controller *) 348 sun_fdc = (struct sun_flpy_controller *)
346 sbus_ioremap(&r, 0, fd_regs[0].reg_size, "floppy"); 349 of_ioremap(&r, 0, fd_regs[0].reg_size, "floppy");
347 350
348 /* Last minute sanity check... */ 351 /* Last minute sanity check... */
349 if(sun_fdc->status_82072 == 0xff) { 352 if(sun_fdc->status_82072 == 0xff) {
@@ -385,4 +388,15 @@ static int sparc_eject(void)
385 388
386#define EXTRA_FLOPPY_PARAMS 389#define EXTRA_FLOPPY_PARAMS
387 390
391static DEFINE_SPINLOCK(dma_spin_lock);
392
393#define claim_dma_lock() \
394({ unsigned long flags; \
395 spin_lock_irqsave(&dma_spin_lock, flags); \
396 flags; \
397})
398
399#define release_dma_lock(__flags) \
400 spin_unlock_irqrestore(&dma_spin_lock, __flags);
401
388#endif /* !(__ASM_SPARC_FLOPPY_H) */ 402#endif /* !(__ASM_SPARC_FLOPPY_H) */
diff --git a/arch/sparc/include/asm/floppy_64.h b/arch/sparc/include/asm/floppy_64.h
index c39db1060bc7..36439d67ad71 100644
--- a/arch/sparc/include/asm/floppy_64.h
+++ b/arch/sparc/include/asm/floppy_64.h
@@ -1,6 +1,6 @@
1/* floppy.h: Sparc specific parts of the Floppy driver. 1/* floppy.h: Sparc specific parts of the Floppy driver.
2 * 2 *
3 * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net) 3 * Copyright (C) 1996, 2007, 2008 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 4 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * 5 *
6 * Ultra/PCI support added: Sep 1997 Eddie C. Dost (ecd@skynet.be) 6 * Ultra/PCI support added: Sep 1997 Eddie C. Dost (ecd@skynet.be)
@@ -9,18 +9,11 @@
9#ifndef __ASM_SPARC64_FLOPPY_H 9#ifndef __ASM_SPARC64_FLOPPY_H
10#define __ASM_SPARC64_FLOPPY_H 10#define __ASM_SPARC64_FLOPPY_H
11 11
12#include <linux/init.h> 12#include <linux/of.h>
13#include <linux/pci.h> 13#include <linux/of_device.h>
14#include <linux/dma-mapping.h>
14 15
15#include <asm/page.h>
16#include <asm/pgtable.h>
17#include <asm/system.h>
18#include <asm/idprom.h>
19#include <asm/oplib.h>
20#include <asm/auxio.h> 16#include <asm/auxio.h>
21#include <asm/sbus.h>
22#include <asm/irq.h>
23
24 17
25/* 18/*
26 * Define this to enable exchanging drive 0 and 1 if only drive 1 is 19 * Define this to enable exchanging drive 0 and 1 if only drive 1 is
@@ -50,7 +43,7 @@ struct sun_flpy_controller {
50/* You'll only ever find one controller on an Ultra anyways. */ 43/* You'll only ever find one controller on an Ultra anyways. */
51static struct sun_flpy_controller *sun_fdc = (struct sun_flpy_controller *)-1; 44static struct sun_flpy_controller *sun_fdc = (struct sun_flpy_controller *)-1;
52unsigned long fdc_status; 45unsigned long fdc_status;
53static struct sbus_dev *floppy_sdev = NULL; 46static struct of_device *floppy_op = NULL;
54 47
55struct sun_floppy_ops { 48struct sun_floppy_ops {
56 unsigned char (*fd_inb) (unsigned long port); 49 unsigned char (*fd_inb) (unsigned long port);
@@ -291,12 +284,11 @@ static int sun_fd_eject(int drive)
291 return 0; 284 return 0;
292} 285}
293 286
294#ifdef CONFIG_PCI 287#include <asm/ebus_dma.h>
295#include <asm/ebus.h>
296#include <asm/ns87303.h> 288#include <asm/ns87303.h>
297 289
298static struct ebus_dma_info sun_pci_fd_ebus_dma; 290static struct ebus_dma_info sun_pci_fd_ebus_dma;
299static struct pci_dev *sun_pci_ebus_dev; 291static struct device *sun_floppy_dev;
300static int sun_pci_broken_drive = -1; 292static int sun_pci_broken_drive = -1;
301 293
302struct sun_pci_dma_op { 294struct sun_pci_dma_op {
@@ -377,7 +369,7 @@ static void sun_pci_fd_enable_dma(void)
377 sun_pci_dma_pending.addr = -1U; 369 sun_pci_dma_pending.addr = -1U;
378 370
379 sun_pci_dma_current.addr = 371 sun_pci_dma_current.addr =
380 pci_map_single(sun_pci_ebus_dev, 372 dma_map_single(sun_floppy_dev,
381 sun_pci_dma_current.buf, 373 sun_pci_dma_current.buf,
382 sun_pci_dma_current.len, 374 sun_pci_dma_current.len,
383 sun_pci_dma_current.direction); 375 sun_pci_dma_current.direction);
@@ -394,7 +386,7 @@ static void sun_pci_fd_disable_dma(void)
394{ 386{
395 ebus_dma_enable(&sun_pci_fd_ebus_dma, 0); 387 ebus_dma_enable(&sun_pci_fd_ebus_dma, 0);
396 if (sun_pci_dma_current.addr != -1U) 388 if (sun_pci_dma_current.addr != -1U)
397 pci_unmap_single(sun_pci_ebus_dev, 389 dma_unmap_single(sun_floppy_dev,
398 sun_pci_dma_current.addr, 390 sun_pci_dma_current.addr,
399 sun_pci_dma_current.len, 391 sun_pci_dma_current.len,
400 sun_pci_dma_current.direction); 392 sun_pci_dma_current.direction);
@@ -404,9 +396,9 @@ static void sun_pci_fd_disable_dma(void)
404static void sun_pci_fd_set_dma_mode(int mode) 396static void sun_pci_fd_set_dma_mode(int mode)
405{ 397{
406 if (mode == DMA_MODE_WRITE) 398 if (mode == DMA_MODE_WRITE)
407 sun_pci_dma_pending.direction = PCI_DMA_TODEVICE; 399 sun_pci_dma_pending.direction = DMA_TO_DEVICE;
408 else 400 else
409 sun_pci_dma_pending.direction = PCI_DMA_FROMDEVICE; 401 sun_pci_dma_pending.direction = DMA_FROM_DEVICE;
410 402
411 ebus_dma_prepare(&sun_pci_fd_ebus_dma, mode != DMA_MODE_WRITE); 403 ebus_dma_prepare(&sun_pci_fd_ebus_dma, mode != DMA_MODE_WRITE);
412} 404}
@@ -538,80 +530,84 @@ static int sun_pci_fd_test_drive(unsigned long port, int drive)
538#undef MSR 530#undef MSR
539#undef DOR 531#undef DOR
540 532
541#endif /* CONFIG_PCI */ 533static int __init ebus_fdthree_p(struct device_node *dp)
542
543#ifdef CONFIG_PCI
544static int __init ebus_fdthree_p(struct linux_ebus_device *edev)
545{ 534{
546 if (!strcmp(edev->prom_node->name, "fdthree")) 535 if (!strcmp(dp->name, "fdthree"))
547 return 1; 536 return 1;
548 if (!strcmp(edev->prom_node->name, "floppy")) { 537 if (!strcmp(dp->name, "floppy")) {
549 const char *compat; 538 const char *compat;
550 539
551 compat = of_get_property(edev->prom_node, 540 compat = of_get_property(dp, "compatible", NULL);
552 "compatible", NULL);
553 if (compat && !strcmp(compat, "fdthree")) 541 if (compat && !strcmp(compat, "fdthree"))
554 return 1; 542 return 1;
555 } 543 }
556 return 0; 544 return 0;
557} 545}
558#endif
559 546
560static unsigned long __init sun_floppy_init(void) 547static unsigned long __init sun_floppy_init(void)
561{ 548{
562 char state[128];
563 struct sbus_bus *bus;
564 struct sbus_dev *sdev = NULL;
565 static int initialized = 0; 549 static int initialized = 0;
550 struct device_node *dp;
551 struct of_device *op;
552 const char *prop;
553 char state[128];
566 554
567 if (initialized) 555 if (initialized)
568 return sun_floppy_types[0]; 556 return sun_floppy_types[0];
569 initialized = 1; 557 initialized = 1;
570 558
571 for_all_sbusdev (sdev, bus) { 559 op = NULL;
572 if (!strcmp(sdev->prom_name, "SUNW,fdtwo")) 560
561 for_each_node_by_name(dp, "SUNW,fdtwo") {
562 if (strcmp(dp->parent->name, "sbus"))
563 continue;
564 op = of_find_device_by_node(dp);
565 if (op)
573 break; 566 break;
574 } 567 }
575 if(sdev) { 568 if (op) {
576 floppy_sdev = sdev; 569 floppy_op = op;
577 FLOPPY_IRQ = sdev->irqs[0]; 570 FLOPPY_IRQ = op->irqs[0];
578 } else { 571 } else {
579#ifdef CONFIG_PCI 572 struct device_node *ebus_dp;
580 struct linux_ebus *ebus;
581 struct linux_ebus_device *edev = NULL;
582 unsigned long config = 0;
583 void __iomem *auxio_reg; 573 void __iomem *auxio_reg;
584 const char *state_prop; 574 const char *state_prop;
575 unsigned long config;
585 576
586 for_each_ebus(ebus) { 577 dp = NULL;
587 for_each_ebusdev(edev, ebus) { 578 for_each_node_by_name(ebus_dp, "ebus") {
588 if (ebus_fdthree_p(edev)) 579 for (dp = ebus_dp->child; dp; dp = dp->sibling) {
589 goto ebus_done; 580 if (ebus_fdthree_p(dp))
581 goto found_fdthree;
590 } 582 }
591 } 583 }
592 ebus_done: 584 found_fdthree:
593 if (!edev) 585 if (!dp)
586 return 0;
587
588 op = of_find_device_by_node(dp);
589 if (!op)
594 return 0; 590 return 0;
595 591
596 state_prop = of_get_property(edev->prom_node, "status", NULL); 592 state_prop = of_get_property(op->node, "status", NULL);
597 if (state_prop && !strncmp(state_prop, "disabled", 8)) 593 if (state_prop && !strncmp(state_prop, "disabled", 8))
598 return 0; 594 return 0;
599 595
600 FLOPPY_IRQ = edev->irqs[0]; 596 FLOPPY_IRQ = op->irqs[0];
601 597
602 /* Make sure the high density bit is set, some systems 598 /* Make sure the high density bit is set, some systems
603 * (most notably Ultra5/Ultra10) come up with it clear. 599 * (most notably Ultra5/Ultra10) come up with it clear.
604 */ 600 */
605 auxio_reg = (void __iomem *) edev->resource[2].start; 601 auxio_reg = (void __iomem *) op->resource[2].start;
606 writel(readl(auxio_reg)|0x2, auxio_reg); 602 writel(readl(auxio_reg)|0x2, auxio_reg);
607 603
608 sun_pci_ebus_dev = ebus->self; 604 sun_floppy_dev = &op->dev;
609 605
610 spin_lock_init(&sun_pci_fd_ebus_dma.lock); 606 spin_lock_init(&sun_pci_fd_ebus_dma.lock);
611 607
612 /* XXX ioremap */ 608 /* XXX ioremap */
613 sun_pci_fd_ebus_dma.regs = (void __iomem *) 609 sun_pci_fd_ebus_dma.regs = (void __iomem *)
614 edev->resource[1].start; 610 op->resource[1].start;
615 if (!sun_pci_fd_ebus_dma.regs) 611 if (!sun_pci_fd_ebus_dma.regs)
616 return 0; 612 return 0;
617 613
@@ -625,7 +621,7 @@ static unsigned long __init sun_floppy_init(void)
625 return 0; 621 return 0;
626 622
627 /* XXX ioremap */ 623 /* XXX ioremap */
628 sun_fdc = (struct sun_flpy_controller *)edev->resource[0].start; 624 sun_fdc = (struct sun_flpy_controller *) op->resource[0].start;
629 625
630 sun_fdops.fd_inb = sun_pci_fd_inb; 626 sun_fdops.fd_inb = sun_pci_fd_inb;
631 sun_fdops.fd_outb = sun_pci_fd_outb; 627 sun_fdops.fd_outb = sun_pci_fd_outb;
@@ -662,12 +658,15 @@ static unsigned long __init sun_floppy_init(void)
662 /* 658 /*
663 * Find NS87303 SuperIO config registers (through ecpp). 659 * Find NS87303 SuperIO config registers (through ecpp).
664 */ 660 */
665 for_each_ebus(ebus) { 661 config = 0;
666 for_each_ebusdev(edev, ebus) { 662 for (dp = ebus_dp->child; dp; dp = dp->sibling) {
667 if (!strcmp(edev->prom_node->name, "ecpp")) { 663 if (!strcmp(dp->name, "ecpp")) {
668 config = edev->resource[1].start; 664 struct of_device *ecpp_op;
669 goto config_done; 665
670 } 666 ecpp_op = of_find_device_by_node(dp);
667 if (ecpp_op)
668 config = ecpp_op->resource[1].start;
669 goto config_done;
671 } 670 }
672 } 671 }
673 config_done: 672 config_done:
@@ -716,26 +715,23 @@ static unsigned long __init sun_floppy_init(void)
716#endif /* PCI_FDC_SWAP_DRIVES */ 715#endif /* PCI_FDC_SWAP_DRIVES */
717 716
718 return sun_floppy_types[0]; 717 return sun_floppy_types[0];
719#else
720 return 0;
721#endif
722 } 718 }
723 prom_getproperty(sdev->prom_node, "status", state, sizeof(state)); 719 prop = of_get_property(op->node, "status", NULL);
724 if(!strncmp(state, "disabled", 8)) 720 if (prop && !strncmp(state, "disabled", 8))
725 return 0; 721 return 0;
726 722
727 /* 723 /*
728 * We cannot do sbus_ioremap here: it does request_region, 724 * We cannot do of_ioremap here: it does request_region,
729 * which the generic floppy driver tries to do once again. 725 * which the generic floppy driver tries to do once again.
730 * But we must use the sdev resource values as they have 726 * But we must use the sdev resource values as they have
731 * had parent ranges applied. 727 * had parent ranges applied.
732 */ 728 */
733 sun_fdc = (struct sun_flpy_controller *) 729 sun_fdc = (struct sun_flpy_controller *)
734 (sdev->resource[0].start + 730 (op->resource[0].start +
735 ((sdev->resource[0].flags & 0x1ffUL) << 32UL)); 731 ((op->resource[0].flags & 0x1ffUL) << 32UL));
736 732
737 /* Last minute sanity check... */ 733 /* Last minute sanity check... */
738 if(sbus_readb(&sun_fdc->status1_82077) == 0xff) { 734 if (sbus_readb(&sun_fdc->status1_82077) == 0xff) {
739 sun_fdc = (struct sun_flpy_controller *)-1; 735 sun_fdc = (struct sun_flpy_controller *)-1;
740 return 0; 736 return 0;
741 } 737 }
diff --git a/arch/sparc/include/asm/gpio.h b/arch/sparc/include/asm/gpio.h
new file mode 100644
index 000000000000..a0e3ac0af599
--- /dev/null
+++ b/arch/sparc/include/asm/gpio.h
@@ -0,0 +1,36 @@
1#ifndef __ASM_SPARC_GPIO_H
2#define __ASM_SPARC_GPIO_H
3
4#include <linux/errno.h>
5#include <asm-generic/gpio.h>
6
7#ifdef CONFIG_GPIOLIB
8
9static inline int gpio_get_value(unsigned int gpio)
10{
11 return __gpio_get_value(gpio);
12}
13
14static inline void gpio_set_value(unsigned int gpio, int value)
15{
16 __gpio_set_value(gpio, value);
17}
18
19static inline int gpio_cansleep(unsigned int gpio)
20{
21 return __gpio_cansleep(gpio);
22}
23
24static inline int gpio_to_irq(unsigned int gpio)
25{
26 return -ENOSYS;
27}
28
29static inline int irq_to_gpio(unsigned int irq)
30{
31 return -EINVAL;
32}
33
34#endif /* CONFIG_GPIOLIB */
35
36#endif /* __ASM_SPARC_GPIO_H */
diff --git a/arch/sparc/include/asm/io-unit.h b/arch/sparc/include/asm/io-unit.h
index 96823b47fd45..01ab2f613e91 100644
--- a/arch/sparc/include/asm/io-unit.h
+++ b/arch/sparc/include/asm/io-unit.h
@@ -55,8 +55,4 @@ struct iounit_struct {
55#define IOUNIT_BMAPM_START IOUNIT_BMAP2_END 55#define IOUNIT_BMAPM_START IOUNIT_BMAP2_END
56#define IOUNIT_BMAPM_END ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT) 56#define IOUNIT_BMAPM_END ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT)
57 57
58extern __u32 iounit_map_dma_init(struct sbus_bus *, int);
59#define iounit_map_dma_finish(sbus, addr, len) mmu_release_scsi_one(addr, len, sbus)
60extern __u32 iounit_map_dma_page(__u32, void *, struct sbus_bus *);
61
62#endif /* !(_SPARC_IO_UNIT_H) */ 58#endif /* !(_SPARC_IO_UNIT_H) */
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index 10d7da450070..93fe21e02c86 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -293,14 +293,6 @@ extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
293extern void pci_iounmap(struct pci_dev *dev, void __iomem *); 293extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
294 294
295/* 295/*
296 * Bus number may be in res->flags... somewhere.
297 */
298extern void __iomem *sbus_ioremap(struct resource *res, unsigned long offset,
299 unsigned long size, char *name);
300extern void sbus_iounmap(volatile void __iomem *vaddr, unsigned long size);
301
302
303/*
304 * At the moment, we do not use CMOS_READ anywhere outside of rtc.c, 296 * At the moment, we do not use CMOS_READ anywhere outside of rtc.c,
305 * so rtc_port is static in it. This should not change unless a new 297 * so rtc_port is static in it. This should not change unless a new
306 * hardware pops up. 298 * hardware pops up.
@@ -308,6 +300,17 @@ extern void sbus_iounmap(volatile void __iomem *vaddr, unsigned long size);
308#define RTC_PORT(x) (rtc_port + (x)) 300#define RTC_PORT(x) (rtc_port + (x))
309#define RTC_ALWAYS_BCD 0 301#define RTC_ALWAYS_BCD 0
310 302
303static inline int sbus_can_dma_64bit(void)
304{
305 return 0; /* actually, sparc_cpu_model==sun4d */
306}
307static inline int sbus_can_burst64(void)
308{
309 return 0; /* actually, sparc_cpu_model==sun4d */
310}
311struct device;
312extern void sbus_set_sbus64(struct device *, int);
313
311#endif 314#endif
312 315
313#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1 316#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h
index 0bff078ffdd0..4aee21dc9c6f 100644
--- a/arch/sparc/include/asm/io_64.h
+++ b/arch/sparc/include/asm/io_64.h
@@ -482,18 +482,16 @@ struct pci_dev;
482extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); 482extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
483extern void pci_iounmap(struct pci_dev *dev, void __iomem *); 483extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
484 484
485/* Similarly for SBUS. */ 485static inline int sbus_can_dma_64bit(void)
486#define sbus_ioremap(__res, __offset, __size, __name) \ 486{
487({ unsigned long __ret; \ 487 return 1;
488 __ret = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \ 488}
489 __ret += (unsigned long) (__offset); \ 489static inline int sbus_can_burst64(void)
490 if (! request_region((__ret), (__size), (__name))) \ 490{
491 __ret = 0UL; \ 491 return 1;
492 (void __iomem *) __ret; \ 492}
493}) 493struct device;
494 494extern void sbus_set_sbus64(struct device *, int);
495#define sbus_iounmap(__addr, __size) \
496 release_region((unsigned long)(__addr), (__size))
497 495
498/* 496/*
499 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 497 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
diff --git a/arch/sparc/include/asm/iommu_64.h b/arch/sparc/include/asm/iommu_64.h
index d7b9afcba08b..caf798b56191 100644
--- a/arch/sparc/include/asm/iommu_64.h
+++ b/arch/sparc/include/asm/iommu_64.h
@@ -48,6 +48,9 @@ struct strbuf {
48 unsigned long strbuf_control; 48 unsigned long strbuf_control;
49 unsigned long strbuf_pflush; 49 unsigned long strbuf_pflush;
50 unsigned long strbuf_fsync; 50 unsigned long strbuf_fsync;
51 unsigned long strbuf_err_stat;
52 unsigned long strbuf_tag_diag;
53 unsigned long strbuf_line_diag;
51 unsigned long strbuf_ctxflush; 54 unsigned long strbuf_ctxflush;
52 unsigned long strbuf_ctxmatch_base; 55 unsigned long strbuf_ctxmatch_base;
53 unsigned long strbuf_flushflag_pa; 56 unsigned long strbuf_flushflag_pa;
diff --git a/arch/sparc/include/asm/irq_64.h b/arch/sparc/include/asm/irq_64.h
index e3dd9303643d..71673eca3660 100644
--- a/arch/sparc/include/asm/irq_64.h
+++ b/arch/sparc/include/asm/irq_64.h
@@ -56,7 +56,6 @@ extern unsigned int sun4u_build_msi(u32 portid, unsigned int *virt_irq_p,
56 unsigned long imap_base, 56 unsigned long imap_base,
57 unsigned long iclr_base); 57 unsigned long iclr_base);
58extern void sun4u_destroy_msi(unsigned int virt_irq); 58extern void sun4u_destroy_msi(unsigned int virt_irq);
59extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
60 59
61extern unsigned char virt_irq_alloc(unsigned int dev_handle, 60extern unsigned char virt_irq_alloc(unsigned int dev_handle,
62 unsigned int dev_ino); 61 unsigned int dev_ino);
diff --git a/arch/sparc/include/asm/mc146818rtc_64.h b/arch/sparc/include/asm/mc146818rtc_64.h
index e9c0fcc25c6f..7238d174e0e3 100644
--- a/arch/sparc/include/asm/mc146818rtc_64.h
+++ b/arch/sparc/include/asm/mc146818rtc_64.h
@@ -7,12 +7,8 @@
7#include <asm/io.h> 7#include <asm/io.h>
8 8
9#ifndef RTC_PORT 9#ifndef RTC_PORT
10#ifdef CONFIG_PCI 10extern unsigned long cmos_regs;
11extern unsigned long ds1287_regs; 11#define RTC_PORT(x) (cmos_regs + (x))
12#else
13#define ds1287_regs (0UL)
14#endif
15#define RTC_PORT(x) (ds1287_regs + (x))
16#define RTC_ALWAYS_BCD 0 12#define RTC_ALWAYS_BCD 0
17#endif 13#endif
18 14
@@ -29,6 +25,4 @@ outb_p((addr),RTC_PORT(0)); \
29outb_p((val),RTC_PORT(1)); \ 25outb_p((val),RTC_PORT(1)); \
30}) 26})
31 27
32#define RTC_IRQ 8
33
34#endif /* __ASM_SPARC64_MC146818RTC_H */ 28#endif /* __ASM_SPARC64_MC146818RTC_H */
diff --git a/arch/sparc/include/asm/memctrl.h b/arch/sparc/include/asm/memctrl.h
new file mode 100644
index 000000000000..4065c56af7b6
--- /dev/null
+++ b/arch/sparc/include/asm/memctrl.h
@@ -0,0 +1,9 @@
1#ifndef _SPARC_MEMCTRL_H
2#define _SPARC_MEMCTRL_H
3
4typedef int (*dimm_printer_t)(int synd_code, unsigned long paddr, char *buf, int buflen);
5
6int register_dimm_printer(dimm_printer_t func);
7void unregister_dimm_printer(dimm_printer_t func);
8
9#endif /* _SPARC_MEMCTRL_H */
diff --git a/arch/sparc/include/asm/mostek.h b/arch/sparc/include/asm/mostek.h
deleted file mode 100644
index 433be3e0a69b..000000000000
--- a/arch/sparc/include/asm/mostek.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_MOSTEK_H
2#define ___ASM_SPARC_MOSTEK_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm/mostek_64.h>
5#else
6#include <asm/mostek_32.h>
7#endif
8#endif
diff --git a/arch/sparc/include/asm/mostek_32.h b/arch/sparc/include/asm/mostek_32.h
deleted file mode 100644
index a99590c4c507..000000000000
--- a/arch/sparc/include/asm/mostek_32.h
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * mostek.h: Describes the various Mostek time of day clock registers.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
6 * Added intersil code 05/25/98 Chris Davis (cdavis@cois.on.ca)
7 */
8
9#ifndef _SPARC_MOSTEK_H
10#define _SPARC_MOSTEK_H
11
12#include <asm/idprom.h>
13#include <asm/io.h>
14
15/* M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
16 *
17 * Data
18 * Address Function
19 * Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
20 * 7ff - - - - - - - - Year 00-99
21 * 7fe 0 0 0 - - - - - Month 01-12
22 * 7fd 0 0 - - - - - - Date 01-31
23 * 7fc 0 FT 0 0 0 - - - Day 01-07
24 * 7fb KS 0 - - - - - - Hours 00-23
25 * 7fa 0 - - - - - - - Minutes 00-59
26 * 7f9 ST - - - - - - - Seconds 00-59
27 * 7f8 W R S - - - - - Control
28 *
29 * * ST is STOP BIT
30 * * W is WRITE BIT
31 * * R is READ BIT
32 * * S is SIGN BIT
33 * * FT is FREQ TEST BIT
34 * * KS is KICK START BIT
35 */
36
37/* The Mostek 48t02 real time clock and NVRAM chip. The registers
38 * other than the control register are in binary coded decimal. Some
39 * control bits also live outside the control register.
40 */
41#define mostek_read(_addr) readb(_addr)
42#define mostek_write(_addr,_val) writeb(_val, _addr)
43#define MOSTEK_EEPROM 0x0000UL
44#define MOSTEK_IDPROM 0x07d8UL
45#define MOSTEK_CREG 0x07f8UL
46#define MOSTEK_SEC 0x07f9UL
47#define MOSTEK_MIN 0x07faUL
48#define MOSTEK_HOUR 0x07fbUL
49#define MOSTEK_DOW 0x07fcUL
50#define MOSTEK_DOM 0x07fdUL
51#define MOSTEK_MONTH 0x07feUL
52#define MOSTEK_YEAR 0x07ffUL
53
54struct mostek48t02 {
55 volatile char eeprom[2008]; /* This is the eeprom, don't touch! */
56 struct idprom idprom; /* The idprom lives here. */
57 volatile unsigned char creg; /* Control register */
58 volatile unsigned char sec; /* Seconds (0-59) */
59 volatile unsigned char min; /* Minutes (0-59) */
60 volatile unsigned char hour; /* Hour (0-23) */
61 volatile unsigned char dow; /* Day of the week (1-7) */
62 volatile unsigned char dom; /* Day of the month (1-31) */
63 volatile unsigned char month; /* Month of year (1-12) */
64 volatile unsigned char year; /* Year (0-99) */
65};
66
67extern spinlock_t mostek_lock;
68extern void __iomem *mstk48t02_regs;
69
70/* Control register values. */
71#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
72#define MSTK_CREG_READ 0x40 /* Stop updates to allow a clean read. */
73#define MSTK_CREG_SIGN 0x20 /* Slow/speed clock in calibration mode. */
74
75/* Control bits that live in the other registers. */
76#define MSTK_STOP 0x80 /* Stop the clock oscillator. (sec) */
77#define MSTK_KICK_START 0x80 /* Kick start the clock chip. (hour) */
78#define MSTK_FREQ_TEST 0x40 /* Frequency test mode. (day) */
79
80#define MSTK_YEAR_ZERO 1968 /* If year reg has zero, it is 1968. */
81#define MSTK_CVT_YEAR(yr) ((yr) + MSTK_YEAR_ZERO)
82
83/* Masks that define how much space each value takes up. */
84#define MSTK_SEC_MASK 0x7f
85#define MSTK_MIN_MASK 0x7f
86#define MSTK_HOUR_MASK 0x3f
87#define MSTK_DOW_MASK 0x07
88#define MSTK_DOM_MASK 0x3f
89#define MSTK_MONTH_MASK 0x1f
90#define MSTK_YEAR_MASK 0xffU
91
92/* Binary coded decimal conversion macros. */
93#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
94#define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
95
96/* Generic register set and get macros for internal use. */
97#define MSTK_GET(regs,var,mask) (MSTK_REGVAL_TO_DECIMAL(((struct mostek48t02 *)regs)->var & MSTK_ ## mask ## _MASK))
98#define MSTK_SET(regs,var,value,mask) do { ((struct mostek48t02 *)regs)->var &= ~(MSTK_ ## mask ## _MASK); ((struct mostek48t02 *)regs)->var |= MSTK_DECIMAL_TO_REGVAL(value) & (MSTK_ ## mask ## _MASK); } while (0)
99
100/* Macros to make register access easier on our fingers. These give you
101 * the decimal value of the register requested if applicable. You pass
102 * the a pointer to a 'struct mostek48t02'.
103 */
104#define MSTK_REG_CREG(regs) (((struct mostek48t02 *)regs)->creg)
105#define MSTK_REG_SEC(regs) MSTK_GET(regs,sec,SEC)
106#define MSTK_REG_MIN(regs) MSTK_GET(regs,min,MIN)
107#define MSTK_REG_HOUR(regs) MSTK_GET(regs,hour,HOUR)
108#define MSTK_REG_DOW(regs) MSTK_GET(regs,dow,DOW)
109#define MSTK_REG_DOM(regs) MSTK_GET(regs,dom,DOM)
110#define MSTK_REG_MONTH(regs) MSTK_GET(regs,month,MONTH)
111#define MSTK_REG_YEAR(regs) MSTK_GET(regs,year,YEAR)
112
113#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,sec,value,SEC)
114#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,min,value,MIN)
115#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,hour,value,HOUR)
116#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,dow,value,DOW)
117#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,dom,value,DOM)
118#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,month,value,MONTH)
119#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,year,value,YEAR)
120
121
122/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
123 * same (basically) layout of the 48t02 chip except for the extra
124 * NVRAM on board (8 KB against the 48t02's 2 KB).
125 */
126struct mostek48t08 {
127 char offset[6*1024]; /* Magic things may be here, who knows? */
128 struct mostek48t02 regs; /* Here is what we are interested in. */
129};
130
131#ifdef CONFIG_SUN4
132enum sparc_clock_type { MSTK48T02, MSTK48T08, \
133INTERSIL, MSTK_INVALID };
134#else
135enum sparc_clock_type { MSTK48T02, MSTK48T08, \
136MSTK_INVALID };
137#endif
138
139#ifdef CONFIG_SUN4
140/* intersil on a sun 4/260 code data from harris doc */
141struct intersil_dt {
142 volatile unsigned char int_csec;
143 volatile unsigned char int_hour;
144 volatile unsigned char int_min;
145 volatile unsigned char int_sec;
146 volatile unsigned char int_month;
147 volatile unsigned char int_day;
148 volatile unsigned char int_year;
149 volatile unsigned char int_dow;
150};
151
152struct intersil {
153 struct intersil_dt clk;
154 struct intersil_dt cmp;
155 volatile unsigned char int_intr_reg;
156 volatile unsigned char int_cmd_reg;
157};
158
159#define INTERSIL_STOP 0x0
160#define INTERSIL_START 0x8
161#define INTERSIL_INTR_DISABLE 0x0
162#define INTERSIL_INTR_ENABLE 0x10
163#define INTERSIL_32K 0x0
164#define INTERSIL_NORMAL 0x0
165#define INTERSIL_24H 0x4
166#define INTERSIL_INT_100HZ 0x2
167
168/* end of intersil info */
169#endif
170
171#endif /* !(_SPARC_MOSTEK_H) */
diff --git a/arch/sparc/include/asm/mostek_64.h b/arch/sparc/include/asm/mostek_64.h
deleted file mode 100644
index c5652de2ace2..000000000000
--- a/arch/sparc/include/asm/mostek_64.h
+++ /dev/null
@@ -1,143 +0,0 @@
1/* mostek.h: Describes the various Mostek time of day clock registers.
2 *
3 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
5 */
6
7#ifndef _SPARC64_MOSTEK_H
8#define _SPARC64_MOSTEK_H
9
10#include <asm/idprom.h>
11
12/* M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
13 *
14 * Data
15 * Address Function
16 * Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
17 * 7ff - - - - - - - - Year 00-99
18 * 7fe 0 0 0 - - - - - Month 01-12
19 * 7fd 0 0 - - - - - - Date 01-31
20 * 7fc 0 FT 0 0 0 - - - Day 01-07
21 * 7fb KS 0 - - - - - - Hours 00-23
22 * 7fa 0 - - - - - - - Minutes 00-59
23 * 7f9 ST - - - - - - - Seconds 00-59
24 * 7f8 W R S - - - - - Control
25 *
26 * * ST is STOP BIT
27 * * W is WRITE BIT
28 * * R is READ BIT
29 * * S is SIGN BIT
30 * * FT is FREQ TEST BIT
31 * * KS is KICK START BIT
32 */
33
34/* The Mostek 48t02 real time clock and NVRAM chip. The registers
35 * other than the control register are in binary coded decimal. Some
36 * control bits also live outside the control register.
37 *
38 * We now deal with physical addresses for I/O to the chip. -DaveM
39 */
40static inline u8 mostek_read(void __iomem *addr)
41{
42 u8 ret;
43
44 __asm__ __volatile__("lduba [%1] %2, %0"
45 : "=r" (ret)
46 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
47 return ret;
48}
49
50static inline void mostek_write(void __iomem *addr, u8 val)
51{
52 __asm__ __volatile__("stba %0, [%1] %2"
53 : /* no outputs */
54 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
55}
56
57#define MOSTEK_EEPROM 0x0000UL
58#define MOSTEK_IDPROM 0x07d8UL
59#define MOSTEK_CREG 0x07f8UL
60#define MOSTEK_SEC 0x07f9UL
61#define MOSTEK_MIN 0x07faUL
62#define MOSTEK_HOUR 0x07fbUL
63#define MOSTEK_DOW 0x07fcUL
64#define MOSTEK_DOM 0x07fdUL
65#define MOSTEK_MONTH 0x07feUL
66#define MOSTEK_YEAR 0x07ffUL
67
68extern spinlock_t mostek_lock;
69extern void __iomem *mstk48t02_regs;
70
71/* Control register values. */
72#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
73#define MSTK_CREG_READ 0x40 /* Stop updates to allow a clean read. */
74#define MSTK_CREG_SIGN 0x20 /* Slow/speed clock in calibration mode. */
75
76/* Control bits that live in the other registers. */
77#define MSTK_STOP 0x80 /* Stop the clock oscillator. (sec) */
78#define MSTK_KICK_START 0x80 /* Kick start the clock chip. (hour) */
79#define MSTK_FREQ_TEST 0x40 /* Frequency test mode. (day) */
80
81#define MSTK_YEAR_ZERO 1968 /* If year reg has zero, it is 1968. */
82#define MSTK_CVT_YEAR(yr) ((yr) + MSTK_YEAR_ZERO)
83
84/* Masks that define how much space each value takes up. */
85#define MSTK_SEC_MASK 0x7f
86#define MSTK_MIN_MASK 0x7f
87#define MSTK_HOUR_MASK 0x3f
88#define MSTK_DOW_MASK 0x07
89#define MSTK_DOM_MASK 0x3f
90#define MSTK_MONTH_MASK 0x1f
91#define MSTK_YEAR_MASK 0xffU
92
93/* Binary coded decimal conversion macros. */
94#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
95#define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
96
97/* Generic register set and get macros for internal use. */
98#define MSTK_GET(regs,name) \
99 (MSTK_REGVAL_TO_DECIMAL(mostek_read(regs + MOSTEK_ ## name) & MSTK_ ## name ## _MASK))
100#define MSTK_SET(regs,name,value) \
101do { u8 __val = mostek_read(regs + MOSTEK_ ## name); \
102 __val &= ~(MSTK_ ## name ## _MASK); \
103 __val |= (MSTK_DECIMAL_TO_REGVAL(value) & \
104 (MSTK_ ## name ## _MASK)); \
105 mostek_write(regs + MOSTEK_ ## name, __val); \
106} while(0)
107
108/* Macros to make register access easier on our fingers. These give you
109 * the decimal value of the register requested if applicable. You pass
110 * the a pointer to a 'struct mostek48t02'.
111 */
112#define MSTK_REG_CREG(regs) (mostek_read((regs) + MOSTEK_CREG))
113#define MSTK_REG_SEC(regs) MSTK_GET(regs,SEC)
114#define MSTK_REG_MIN(regs) MSTK_GET(regs,MIN)
115#define MSTK_REG_HOUR(regs) MSTK_GET(regs,HOUR)
116#define MSTK_REG_DOW(regs) MSTK_GET(regs,DOW)
117#define MSTK_REG_DOM(regs) MSTK_GET(regs,DOM)
118#define MSTK_REG_MONTH(regs) MSTK_GET(regs,MONTH)
119#define MSTK_REG_YEAR(regs) MSTK_GET(regs,YEAR)
120
121#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,SEC,value)
122#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,MIN,value)
123#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,HOUR,value)
124#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,DOW,value)
125#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,DOM,value)
126#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,MONTH,value)
127#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,YEAR,value)
128
129
130/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
131 * same (basically) layout of the 48t02 chip except for the extra
132 * NVRAM on board (8 KB against the 48t02's 2 KB).
133 */
134#define MOSTEK_48T08_OFFSET 0x0000UL /* Lower NVRAM portions */
135#define MOSTEK_48T08_48T02 0x1800UL /* Offset to 48T02 chip */
136
137/* SUN5 systems usually have 48t59 model clock chipsets. But we keep the older
138 * clock chip definitions around just in case.
139 */
140#define MOSTEK_48T59_OFFSET 0x0000UL /* Lower NVRAM portions */
141#define MOSTEK_48T59_48T02 0x1800UL /* Offset to 48T02 chip */
142
143#endif /* !(_SPARC64_MOSTEK_H) */
diff --git a/arch/sparc/include/asm/obio.h b/arch/sparc/include/asm/obio.h
index 1a7544ceb574..4ade0c8a2c79 100644
--- a/arch/sparc/include/asm/obio.h
+++ b/arch/sparc/include/asm/obio.h
@@ -155,17 +155,6 @@ static inline void bw_set_ctrl(int cpu, unsigned ctrl)
155 "i" (ASI_M_CTL)); 155 "i" (ASI_M_CTL));
156} 156}
157 157
158extern unsigned char cpu_leds[32];
159
160static inline void show_leds(int cpuid)
161{
162 cpuid &= 0x1e;
163 __asm__ __volatile__ ("stba %0, [%1] %2" : :
164 "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
165 "r" (ECSR_BASE(cpuid) | BB_LEDS),
166 "i" (ASI_M_CTL));
167}
168
169static inline unsigned cc_get_ipen(void) 158static inline unsigned cc_get_ipen(void)
170{ 159{
171 unsigned pending; 160 unsigned pending;
diff --git a/arch/sparc/include/asm/of_device.h b/arch/sparc/include/asm/of_device.h
index bba777a416d3..a5d9811f9697 100644
--- a/arch/sparc/include/asm/of_device.h
+++ b/arch/sparc/include/asm/of_device.h
@@ -30,6 +30,8 @@ struct of_device
30extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name); 30extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name);
31extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size); 31extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size);
32 32
33extern void of_propagate_archdata(struct of_device *bus);
34
33/* This is just here during the transition */ 35/* This is just here during the transition */
34#include <linux/of_platform.h> 36#include <linux/of_platform.h>
35 37
diff --git a/arch/sparc/include/asm/of_platform.h b/arch/sparc/include/asm/of_platform.h
index 2348ab90a57c..90da99059f83 100644
--- a/arch/sparc/include/asm/of_platform.h
+++ b/arch/sparc/include/asm/of_platform.h
@@ -13,9 +13,6 @@
13 * 13 *
14 */ 14 */
15 15
16extern struct bus_type ebus_bus_type;
17extern struct bus_type sbus_bus_type;
18
19#define of_bus_type of_platform_bus_type /* for compatibility */ 16#define of_bus_type of_platform_bus_type /* for compatibility */
20 17
21#endif 18#endif
diff --git a/arch/sparc/include/asm/oplib_32.h b/arch/sparc/include/asm/oplib_32.h
index b2631da259e0..699da05235c8 100644
--- a/arch/sparc/include/asm/oplib_32.h
+++ b/arch/sparc/include/asm/oplib_32.h
@@ -21,7 +21,6 @@ enum prom_major_version {
21 PROM_V2, /* sun4c and early sun4m V2 prom */ 21 PROM_V2, /* sun4c and early sun4m V2 prom */
22 PROM_V3, /* sun4m and later, up to sun4d/sun4e machines V3 */ 22 PROM_V3, /* sun4m and later, up to sun4d/sun4e machines V3 */
23 PROM_P1275, /* IEEE compliant ISA based Sun PROM, only sun4u */ 23 PROM_P1275, /* IEEE compliant ISA based Sun PROM, only sun4u */
24 PROM_SUN4, /* Old sun4 proms are totally different, but we'll shoehorn it to make it fit */
25}; 24};
26 25
27extern enum prom_major_version prom_vers; 26extern enum prom_major_version prom_vers;
diff --git a/arch/sparc/include/asm/page_32.h b/arch/sparc/include/asm/page_32.h
index cf5fb70ca1c1..d1806edc0958 100644
--- a/arch/sparc/include/asm/page_32.h
+++ b/arch/sparc/include/asm/page_32.h
@@ -8,11 +8,8 @@
8#ifndef _SPARC_PAGE_H 8#ifndef _SPARC_PAGE_H
9#define _SPARC_PAGE_H 9#define _SPARC_PAGE_H
10 10
11#ifdef CONFIG_SUN4
12#define PAGE_SHIFT 13
13#else
14#define PAGE_SHIFT 12 11#define PAGE_SHIFT 12
15#endif 12
16#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
17/* I have my suspicions... -DaveM */ 14/* I have my suspicions... -DaveM */
18#define PAGE_SIZE (1UL << PAGE_SHIFT) 15#define PAGE_SIZE (1UL << PAGE_SHIFT)
diff --git a/arch/sparc/include/asm/page_64.h b/arch/sparc/include/asm/page_64.h
index b579b910ef51..4274ed13ddb2 100644
--- a/arch/sparc/include/asm/page_64.h
+++ b/arch/sparc/include/asm/page_64.h
@@ -38,6 +38,8 @@
38 38
39#ifndef __ASSEMBLY__ 39#ifndef __ASSEMBLY__
40 40
41#define WANT_PAGE_VIRTUAL
42
41extern void _clear_page(void *page); 43extern void _clear_page(void *page);
42#define clear_page(X) _clear_page((void *)(X)) 44#define clear_page(X) _clear_page((void *)(X))
43struct page; 45struct page;
diff --git a/arch/sparc/include/asm/parport.h b/arch/sparc/include/asm/parport.h
index d9830621c906..dff3f0253aa8 100644
--- a/arch/sparc/include/asm/parport.h
+++ b/arch/sparc/include/asm/parport.h
@@ -8,7 +8,7 @@
8 8
9#include <linux/of_device.h> 9#include <linux/of_device.h>
10 10
11#include <asm/ebus.h> 11#include <asm/ebus_dma.h>
12#include <asm/ns87303.h> 12#include <asm/ns87303.h>
13#include <asm/prom.h> 13#include <asm/prom.h>
14 14
@@ -215,7 +215,7 @@ static int __devexit ecpp_remove(struct of_device *op)
215 return 0; 215 return 0;
216} 216}
217 217
218static struct of_device_id ecpp_match[] = { 218static const struct of_device_id ecpp_match[] = {
219 { 219 {
220 .name = "ecpp", 220 .name = "ecpp",
221 }, 221 },
diff --git a/arch/sparc/include/asm/pci_32.h b/arch/sparc/include/asm/pci_32.h
index 0ee949d220c0..b41c4c198159 100644
--- a/arch/sparc/include/asm/pci_32.h
+++ b/arch/sparc/include/asm/pci_32.h
@@ -3,6 +3,8 @@
3 3
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5 5
6#include <linux/dma-mapping.h>
7
6/* Can be used to override the logic in pci_scan_bus for skipping 8/* Can be used to override the logic in pci_scan_bus for skipping
7 * already-configured bus numbers - to be used for buggy BIOSes 9 * already-configured bus numbers - to be used for buggy BIOSes
8 * or architectures with incomplete PCI setup by the loader. 10 * or architectures with incomplete PCI setup by the loader.
diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h
index 08237fda8874..e0cabe790ec1 100644
--- a/arch/sparc/include/asm/pgtable_32.h
+++ b/arch/sparc/include/asm/pgtable_32.h
@@ -14,11 +14,7 @@
14#include <linux/spinlock.h> 14#include <linux/spinlock.h>
15#include <linux/swap.h> 15#include <linux/swap.h>
16#include <asm/types.h> 16#include <asm/types.h>
17#ifdef CONFIG_SUN4
18#include <asm/pgtsun4.h>
19#else
20#include <asm/pgtsun4c.h> 17#include <asm/pgtsun4c.h>
21#endif
22#include <asm/pgtsrmmu.h> 18#include <asm/pgtsrmmu.h>
23#include <asm/vac-ops.h> 19#include <asm/vac-ops.h>
24#include <asm/oplib.h> 20#include <asm/oplib.h>
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
index bb9ec2cce355..b049abf9902f 100644
--- a/arch/sparc/include/asm/pgtable_64.h
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -770,6 +770,8 @@ extern void sun4v_patch_tlb_handlers(void);
770 770
771extern unsigned long cmdline_memory_size; 771extern unsigned long cmdline_memory_size;
772 772
773extern asmlinkage void do_sparc64_fault(struct pt_regs *regs);
774
773#endif /* !(__ASSEMBLY__) */ 775#endif /* !(__ASSEMBLY__) */
774 776
775#endif /* !(_SPARC64_PGTABLE_H) */ 777#endif /* !(_SPARC64_PGTABLE_H) */
diff --git a/arch/sparc/include/asm/prom.h b/arch/sparc/include/asm/prom.h
index fd55522481cd..900d44714f8d 100644
--- a/arch/sparc/include/asm/prom.h
+++ b/arch/sparc/include/asm/prom.h
@@ -18,6 +18,7 @@
18 */ 18 */
19#include <linux/types.h> 19#include <linux/types.h>
20#include <linux/proc_fs.h> 20#include <linux/proc_fs.h>
21#include <linux/mutex.h>
21#include <asm/atomic.h> 22#include <asm/atomic.h>
22 23
23#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2 24#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2
@@ -73,6 +74,7 @@ struct of_irq_controller {
73 74
74extern struct device_node *of_find_node_by_cpuid(int cpuid); 75extern struct device_node *of_find_node_by_cpuid(int cpuid);
75extern int of_set_property(struct device_node *node, const char *name, void *val, int len); 76extern int of_set_property(struct device_node *node, const char *name, void *val, int len);
77extern struct mutex of_set_property_mutex;
76extern int of_getintprop_default(struct device_node *np, 78extern int of_getintprop_default(struct device_node *np,
77 const char *name, 79 const char *name,
78 int def); 80 int def);
@@ -94,6 +96,16 @@ static inline void of_node_put(struct device_node *node)
94{ 96{
95} 97}
96 98
99/* These routines are here to provide compatibility with how powerpc
100 * handles IRQ mapping for OF device nodes. We precompute and permanently
101 * register them in the of_device objects, whereas powerpc computes them
102 * on request.
103 */
104extern unsigned int irq_of_parse_and_map(struct device_node *node, int index);
105static inline void irq_dispose_mapping(unsigned int virq)
106{
107}
108
97/* 109/*
98 * NB: This is here while we transition from using asm/prom.h 110 * NB: This is here while we transition from using asm/prom.h
99 * to linux/of.h 111 * to linux/of.h
diff --git a/arch/sparc/include/asm/ptrace_64.h b/arch/sparc/include/asm/ptrace_64.h
index 06e4914c13f4..3d3e9c161d8b 100644
--- a/arch/sparc/include/asm/ptrace_64.h
+++ b/arch/sparc/include/asm/ptrace_64.h
@@ -113,6 +113,8 @@ struct sparc_trapf {
113 113
114#ifdef __KERNEL__ 114#ifdef __KERNEL__
115 115
116#include <linux/threads.h>
117
116static inline int pt_regs_trap_type(struct pt_regs *regs) 118static inline int pt_regs_trap_type(struct pt_regs *regs)
117{ 119{
118 return regs->magic & 0x1ff; 120 return regs->magic & 0x1ff;
@@ -138,6 +140,7 @@ struct global_reg_snapshot {
138 struct thread_info *thread; 140 struct thread_info *thread;
139 unsigned long pad1; 141 unsigned long pad1;
140}; 142};
143extern struct global_reg_snapshot global_reg_snapshot[NR_CPUS];
141 144
142#define __ARCH_WANT_COMPAT_SYS_PTRACE 145#define __ARCH_WANT_COMPAT_SYS_PTRACE
143 146
diff --git a/arch/sparc/include/asm/reboot.h b/arch/sparc/include/asm/reboot.h
deleted file mode 100644
index 3f3f43f5be5e..000000000000
--- a/arch/sparc/include/asm/reboot.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _SPARC64_REBOOT_H
2#define _SPARC64_REBOOT_H
3
4extern void machine_alt_power_off(void);
5
6#endif /* _SPARC64_REBOOT_H */
diff --git a/arch/sparc/include/asm/rtc.h b/arch/sparc/include/asm/rtc.h
deleted file mode 100644
index f9ecb1fe2ecd..000000000000
--- a/arch/sparc/include/asm/rtc.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * rtc.h: Definitions for access to the Mostek real time clock
3 *
4 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
5 */
6
7#ifndef _RTC_H
8#define _RTC_H
9
10#include <linux/ioctl.h>
11
12struct rtc_time
13{
14 int sec; /* Seconds (0-59) */
15 int min; /* Minutes (0-59) */
16 int hour; /* Hour (0-23) */
17 int dow; /* Day of the week (1-7) */
18 int dom; /* Day of the month (1-31) */
19 int month; /* Month of year (1-12) */
20 int year; /* Year (0-99) */
21};
22
23#define RTCGET _IOR('p', 20, struct rtc_time)
24#define RTCSET _IOW('p', 21, struct rtc_time)
25
26#endif
diff --git a/arch/sparc/include/asm/sbus.h b/arch/sparc/include/asm/sbus.h
deleted file mode 100644
index f82481ab44db..000000000000
--- a/arch/sparc/include/asm/sbus.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SBUS_H
2#define ___ASM_SPARC_SBUS_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm/sbus_64.h>
5#else
6#include <asm/sbus_32.h>
7#endif
8#endif
diff --git a/arch/sparc/include/asm/sbus_32.h b/arch/sparc/include/asm/sbus_32.h
deleted file mode 100644
index a7b4fa21931d..000000000000
--- a/arch/sparc/include/asm/sbus_32.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * sbus.h: Defines for the Sun SBus.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_SBUS_H
8#define _SPARC_SBUS_H
9
10#include <linux/dma-mapping.h>
11#include <linux/ioport.h>
12#include <linux/of_device.h>
13
14#include <asm/oplib.h>
15#include <asm/prom.h>
16#include <asm/scatterlist.h>
17
18/* We scan which devices are on the SBus using the PROM node device
19 * tree. SBus devices are described in two different ways. You can
20 * either get an absolute address at which to access the device, or
21 * you can get a SBus 'slot' number and an offset within that slot.
22 */
23
24/* The base address at which to calculate device OBIO addresses. */
25#define SUN_SBUS_BVADDR 0xf8000000
26#define SBUS_OFF_MASK 0x01ffffff
27
28/* These routines are used to calculate device address from slot
29 * numbers + offsets, and vice versa.
30 */
31
32static inline unsigned long sbus_devaddr(int slotnum, unsigned long offset)
33{
34 return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<25)+(offset));
35}
36
37static inline int sbus_dev_slot(unsigned long dev_addr)
38{
39 return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>25);
40}
41
42struct sbus_bus;
43
44/* Linux SBUS device tables */
45struct sbus_dev {
46 struct of_device ofdev;
47 struct sbus_bus *bus;
48 struct sbus_dev *next;
49 struct sbus_dev *child;
50 struct sbus_dev *parent;
51 int prom_node;
52 char prom_name[64];
53 int slot;
54
55 struct resource resource[PROMREG_MAX];
56
57 struct linux_prom_registers reg_addrs[PROMREG_MAX];
58 int num_registers;
59
60 struct linux_prom_ranges device_ranges[PROMREG_MAX];
61 int num_device_ranges;
62
63 unsigned int irqs[4];
64 int num_irqs;
65};
66#define to_sbus_device(d) container_of(d, struct sbus_dev, ofdev.dev)
67
68/* This struct describes the SBus(s) found on this machine. */
69struct sbus_bus {
70 struct of_device ofdev;
71 struct sbus_dev *devices; /* Link to devices on this SBus */
72 struct sbus_bus *next; /* next SBus, if more than one SBus */
73 int prom_node; /* PROM device tree node for this SBus */
74 char prom_name[64]; /* Usually "sbus" or "sbi" */
75 int clock_freq;
76
77 struct linux_prom_ranges sbus_ranges[PROMREG_MAX];
78 int num_sbus_ranges;
79
80 int devid;
81 int board;
82};
83#define to_sbus(d) container_of(d, struct sbus_bus, ofdev.dev)
84
85extern struct sbus_bus *sbus_root;
86
87static inline int
88sbus_is_slave(struct sbus_dev *dev)
89{
90 /* XXX Have to write this for sun4c's */
91 return 0;
92}
93
94/* Device probing routines could find these handy */
95#define for_each_sbus(bus) \
96 for((bus) = sbus_root; (bus); (bus)=(bus)->next)
97
98#define for_each_sbusdev(device, bus) \
99 for((device) = (bus)->devices; (device); (device)=(device)->next)
100
101#define for_all_sbusdev(device, bus) \
102 for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \
103 for ((device) = (bus)->devices; (device); (device) = (device)->next)
104
105/* Driver DVMA interfaces. */
106#define sbus_can_dma_64bit(sdev) (0) /* actually, sparc_cpu_model==sun4d */
107#define sbus_can_burst64(sdev) (0) /* actually, sparc_cpu_model==sun4d */
108extern void sbus_set_sbus64(struct sbus_dev *, int);
109extern void sbus_fill_device_irq(struct sbus_dev *);
110
111/* These yield IOMMU mappings in consistent mode. */
112extern void *sbus_alloc_consistent(struct sbus_dev *, long, u32 *dma_addrp);
113extern void sbus_free_consistent(struct sbus_dev *, long, void *, u32);
114void prom_adjust_ranges(struct linux_prom_ranges *, int,
115 struct linux_prom_ranges *, int);
116
117#define SBUS_DMA_BIDIRECTIONAL DMA_BIDIRECTIONAL
118#define SBUS_DMA_TODEVICE DMA_TO_DEVICE
119#define SBUS_DMA_FROMDEVICE DMA_FROM_DEVICE
120#define SBUS_DMA_NONE DMA_NONE
121
122/* All the rest use streaming mode mappings. */
123extern dma_addr_t sbus_map_single(struct sbus_dev *, void *, size_t, int);
124extern void sbus_unmap_single(struct sbus_dev *, dma_addr_t, size_t, int);
125extern int sbus_map_sg(struct sbus_dev *, struct scatterlist *, int, int);
126extern void sbus_unmap_sg(struct sbus_dev *, struct scatterlist *, int, int);
127
128/* Finally, allow explicit synchronization of streamable mappings. */
129extern void sbus_dma_sync_single_for_cpu(struct sbus_dev *, dma_addr_t, size_t, int);
130#define sbus_dma_sync_single sbus_dma_sync_single_for_cpu
131extern void sbus_dma_sync_single_for_device(struct sbus_dev *, dma_addr_t, size_t, int);
132extern void sbus_dma_sync_sg_for_cpu(struct sbus_dev *, struct scatterlist *, int, int);
133#define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu
134extern void sbus_dma_sync_sg_for_device(struct sbus_dev *, struct scatterlist *, int, int);
135
136/* Eric Brower (ebrower@usa.net)
137 * Translate SBus interrupt levels to ino values--
138 * this is used when converting sbus "interrupts" OBP
139 * node values to "intr" node values, and is platform
140 * dependent. If only we could call OBP with
141 * "sbus-intr>cpu (sbint -- ino)" from kernel...
142 * See .../drivers/sbus/sbus.c for details.
143 */
144BTFIXUPDEF_CALL(unsigned int, sbint_to_irq, struct sbus_dev *sdev, unsigned int)
145#define sbint_to_irq(sdev, sbint) BTFIXUP_CALL(sbint_to_irq)(sdev, sbint)
146
147extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *);
148extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *);
149extern void sbus_setup_arch_props(struct sbus_bus *, struct device_node *);
150extern int sbus_arch_preinit(void);
151extern void sbus_arch_postinit(void);
152
153#endif /* !(_SPARC_SBUS_H) */
diff --git a/arch/sparc/include/asm/sbus_64.h b/arch/sparc/include/asm/sbus_64.h
deleted file mode 100644
index b606c14343fb..000000000000
--- a/arch/sparc/include/asm/sbus_64.h
+++ /dev/null
@@ -1,190 +0,0 @@
1/* sbus.h: Defines for the Sun SBus.
2 *
3 * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _SPARC64_SBUS_H
7#define _SPARC64_SBUS_H
8
9#include <linux/dma-mapping.h>
10#include <linux/ioport.h>
11#include <linux/of_device.h>
12
13#include <asm/oplib.h>
14#include <asm/prom.h>
15#include <asm/iommu.h>
16#include <asm/scatterlist.h>
17
18/* We scan which devices are on the SBus using the PROM node device
19 * tree. SBus devices are described in two different ways. You can
20 * either get an absolute address at which to access the device, or
21 * you can get a SBus 'slot' number and an offset within that slot.
22 */
23
24/* The base address at which to calculate device OBIO addresses. */
25#define SUN_SBUS_BVADDR 0x00000000
26#define SBUS_OFF_MASK 0x0fffffff
27
28/* These routines are used to calculate device address from slot
29 * numbers + offsets, and vice versa.
30 */
31
32static inline unsigned long sbus_devaddr(int slotnum, unsigned long offset)
33{
34 return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<28)+(offset));
35}
36
37static inline int sbus_dev_slot(unsigned long dev_addr)
38{
39 return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>28);
40}
41
42struct sbus_bus;
43
44/* Linux SBUS device tables */
45struct sbus_dev {
46 struct of_device ofdev;
47 struct sbus_bus *bus;
48 struct sbus_dev *next;
49 struct sbus_dev *child;
50 struct sbus_dev *parent;
51 int prom_node;
52 char prom_name[64];
53 int slot;
54
55 struct resource resource[PROMREG_MAX];
56
57 struct linux_prom_registers reg_addrs[PROMREG_MAX];
58 int num_registers;
59
60 struct linux_prom_ranges device_ranges[PROMREG_MAX];
61 int num_device_ranges;
62
63 unsigned int irqs[4];
64 int num_irqs;
65};
66#define to_sbus_device(d) container_of(d, struct sbus_dev, ofdev.dev)
67
68/* This struct describes the SBus(s) found on this machine. */
69struct sbus_bus {
70 struct of_device ofdev;
71 struct sbus_dev *devices; /* Tree of SBUS devices */
72 struct sbus_bus *next; /* Next SBUS in system */
73 int prom_node; /* OBP node of SBUS */
74 char prom_name[64]; /* Usually "sbus" or "sbi" */
75 int clock_freq;
76
77 struct linux_prom_ranges sbus_ranges[PROMREG_MAX];
78 int num_sbus_ranges;
79
80 int portid;
81};
82#define to_sbus(d) container_of(d, struct sbus_bus, ofdev.dev)
83
84extern struct sbus_bus *sbus_root;
85
86/* Device probing routines could find these handy */
87#define for_each_sbus(bus) \
88 for((bus) = sbus_root; (bus); (bus)=(bus)->next)
89
90#define for_each_sbusdev(device, bus) \
91 for((device) = (bus)->devices; (device); (device)=(device)->next)
92
93#define for_all_sbusdev(device, bus) \
94 for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \
95 for ((device) = (bus)->devices; (device); (device) = (device)->next)
96
97/* Driver DVMA interfaces. */
98#define sbus_can_dma_64bit(sdev) (1)
99#define sbus_can_burst64(sdev) (1)
100extern void sbus_set_sbus64(struct sbus_dev *, int);
101extern void sbus_fill_device_irq(struct sbus_dev *);
102
103static inline void *sbus_alloc_consistent(struct sbus_dev *sdev , size_t size,
104 dma_addr_t *dma_handle)
105{
106 return dma_alloc_coherent(&sdev->ofdev.dev, size,
107 dma_handle, GFP_ATOMIC);
108}
109
110static inline void sbus_free_consistent(struct sbus_dev *sdev, size_t size,
111 void *vaddr, dma_addr_t dma_handle)
112{
113 return dma_free_coherent(&sdev->ofdev.dev, size, vaddr, dma_handle);
114}
115
116#define SBUS_DMA_BIDIRECTIONAL DMA_BIDIRECTIONAL
117#define SBUS_DMA_TODEVICE DMA_TO_DEVICE
118#define SBUS_DMA_FROMDEVICE DMA_FROM_DEVICE
119#define SBUS_DMA_NONE DMA_NONE
120
121/* All the rest use streaming mode mappings. */
122static inline dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr,
123 size_t size, int direction)
124{
125 return dma_map_single(&sdev->ofdev.dev, ptr, size,
126 (enum dma_data_direction) direction);
127}
128
129static inline void sbus_unmap_single(struct sbus_dev *sdev,
130 dma_addr_t dma_addr, size_t size,
131 int direction)
132{
133 dma_unmap_single(&sdev->ofdev.dev, dma_addr, size,
134 (enum dma_data_direction) direction);
135}
136
137static inline int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg,
138 int nents, int direction)
139{
140 return dma_map_sg(&sdev->ofdev.dev, sg, nents,
141 (enum dma_data_direction) direction);
142}
143
144static inline void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg,
145 int nents, int direction)
146{
147 dma_unmap_sg(&sdev->ofdev.dev, sg, nents,
148 (enum dma_data_direction) direction);
149}
150
151/* Finally, allow explicit synchronization of streamable mappings. */
152static inline void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev,
153 dma_addr_t dma_handle,
154 size_t size, int direction)
155{
156 dma_sync_single_for_cpu(&sdev->ofdev.dev, dma_handle, size,
157 (enum dma_data_direction) direction);
158}
159#define sbus_dma_sync_single sbus_dma_sync_single_for_cpu
160
161static inline void sbus_dma_sync_single_for_device(struct sbus_dev *sdev,
162 dma_addr_t dma_handle,
163 size_t size, int direction)
164{
165 /* No flushing needed to sync cpu writes to the device. */
166}
167
168static inline void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev,
169 struct scatterlist *sg,
170 int nents, int direction)
171{
172 dma_sync_sg_for_cpu(&sdev->ofdev.dev, sg, nents,
173 (enum dma_data_direction) direction);
174}
175#define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu
176
177static inline void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev,
178 struct scatterlist *sg,
179 int nents, int direction)
180{
181 /* No flushing needed to sync cpu writes to the device. */
182}
183
184extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *);
185extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *);
186extern void sbus_setup_arch_props(struct sbus_bus *, struct device_node *);
187extern int sbus_arch_preinit(void);
188extern void sbus_arch_postinit(void);
189
190#endif /* !(_SPARC64_SBUS_H) */
diff --git a/arch/sparc/include/asm/spinlock_32.h b/arch/sparc/include/asm/spinlock_32.h
index de2249b267c6..bf2d532593e3 100644
--- a/arch/sparc/include/asm/spinlock_32.h
+++ b/arch/sparc/include/asm/spinlock_32.h
@@ -6,8 +6,6 @@
6#ifndef __SPARC_SPINLOCK_H 6#ifndef __SPARC_SPINLOCK_H
7#define __SPARC_SPINLOCK_H 7#define __SPARC_SPINLOCK_H
8 8
9#include <linux/threads.h> /* For NR_CPUS */
10
11#ifndef __ASSEMBLY__ 9#ifndef __ASSEMBLY__
12 10
13#include <asm/psr.h> 11#include <asm/psr.h>
diff --git a/arch/sparc/include/asm/spinlock_64.h b/arch/sparc/include/asm/spinlock_64.h
index 0006fe9f8c7a..120cfe4577c7 100644
--- a/arch/sparc/include/asm/spinlock_64.h
+++ b/arch/sparc/include/asm/spinlock_64.h
@@ -6,8 +6,6 @@
6#ifndef __SPARC64_SPINLOCK_H 6#ifndef __SPARC64_SPINLOCK_H
7#define __SPARC64_SPINLOCK_H 7#define __SPARC64_SPINLOCK_H
8 8
9#include <linux/threads.h> /* For NR_CPUS */
10
11#ifndef __ASSEMBLY__ 9#ifndef __ASSEMBLY__
12 10
13/* To get debugging spinlocks which detect and catch 11/* To get debugging spinlocks which detect and catch
diff --git a/arch/sparc/include/asm/sstate.h b/arch/sparc/include/asm/sstate.h
deleted file mode 100644
index a7c35dbcb281..000000000000
--- a/arch/sparc/include/asm/sstate.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef _SPARC64_SSTATE_H
2#define _SPARC64_SSTATE_H
3
4extern void sstate_booting(void);
5extern void sstate_running(void);
6extern void sstate_halt(void);
7extern void sstate_poweroff(void);
8extern void sstate_panic(void);
9extern void sstate_reboot(void);
10
11extern void sun4v_sstate_init(void);
12
13#endif /* _SPARC64_SSTATE_H */
diff --git a/arch/sparc/include/asm/starfire.h b/arch/sparc/include/asm/starfire.h
index 07bafd31e33c..d56ce60a5992 100644
--- a/arch/sparc/include/asm/starfire.h
+++ b/arch/sparc/include/asm/starfire.h
@@ -12,7 +12,6 @@
12extern int this_is_starfire; 12extern int this_is_starfire;
13 13
14extern void check_if_starfire(void); 14extern void check_if_starfire(void);
15extern void starfire_cpu_setup(void);
16extern int starfire_hard_smp_processor_id(void); 15extern int starfire_hard_smp_processor_id(void);
17extern void starfire_hookup(int); 16extern void starfire_hookup(int);
18extern unsigned int starfire_translate(unsigned long imap, unsigned int upaid); 17extern unsigned int starfire_translate(unsigned long imap, unsigned int upaid);
diff --git a/arch/sparc/include/asm/sun4paddr.h b/arch/sparc/include/asm/sun4paddr.h
deleted file mode 100644
index d52985f19f42..000000000000
--- a/arch/sparc/include/asm/sun4paddr.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * sun4paddr.h: Various physical addresses on sun4 machines
3 *
4 * Copyright (C) 1997 Anton Blanchard (anton@progsoc.uts.edu.au)
5 * Copyright (C) 1998 Chris Davis (cdavis@cois.on.ca)
6 *
7 * Now supports more sun4's
8 */
9
10#ifndef _SPARC_SUN4PADDR_H
11#define _SPARC_SUN4PADDR_H
12
13#define SUN4_IE_PHYSADDR 0xf5000000
14#define SUN4_UNUSED_PHYSADDR 0
15
16/* these work for me */
17#define SUN4_200_MEMREG_PHYSADDR 0xf4000000
18#define SUN4_200_CLOCK_PHYSADDR 0xf3000000
19#define SUN4_200_BWTWO_PHYSADDR 0xfd000000
20#define SUN4_200_ETH_PHYSADDR 0xf6000000
21#define SUN4_200_SI_PHYSADDR 0xff200000
22
23/* these were here before */
24#define SUN4_300_MEMREG_PHYSADDR 0xf4000000
25#define SUN4_300_CLOCK_PHYSADDR 0xf2000000
26#define SUN4_300_TIMER_PHYSADDR 0xef000000
27#define SUN4_300_ETH_PHYSADDR 0xf9000000
28#define SUN4_300_BWTWO_PHYSADDR 0xfb400000
29#define SUN4_300_DMA_PHYSADDR 0xfa001000
30#define SUN4_300_ESP_PHYSADDR 0xfa000000
31
32/* Are these right? */
33#define SUN4_400_MEMREG_PHYSADDR 0xf4000000
34#define SUN4_400_CLOCK_PHYSADDR 0xf2000000
35#define SUN4_400_TIMER_PHYSADDR 0xef000000
36#define SUN4_400_ETH_PHYSADDR 0xf9000000
37#define SUN4_400_BWTWO_PHYSADDR 0xfb400000
38#define SUN4_400_DMA_PHYSADDR 0xfa001000
39#define SUN4_400_ESP_PHYSADDR 0xfa000000
40
41/*
42 these are the actual values set and used in the code. Unused items set
43 to SUN_UNUSED_PHYSADDR
44 */
45
46extern int sun4_memreg_physaddr; /* memory register (ecc?) */
47extern int sun4_clock_physaddr; /* system clock */
48extern int sun4_timer_physaddr; /* timer, where applicable */
49extern int sun4_eth_physaddr; /* onboard ethernet (ie/le) */
50extern int sun4_si_physaddr; /* sun3 scsi adapter */
51extern int sun4_bwtwo_physaddr; /* onboard bw2 */
52extern int sun4_dma_physaddr; /* scsi dma */
53extern int sun4_esp_physaddr; /* esp scsi */
54extern int sun4_ie_physaddr; /* interrupt enable */
55
56#endif /* !(_SPARC_SUN4PADDR_H) */
diff --git a/arch/sparc/include/asm/sun4prom.h b/arch/sparc/include/asm/sun4prom.h
deleted file mode 100644
index 9c8b4cbf629a..000000000000
--- a/arch/sparc/include/asm/sun4prom.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * sun4prom.h -- interface to sun4 PROM monitor. We don't use most of this,
3 * so most of these are just placeholders.
4 */
5
6#ifndef _SUN4PROM_H_
7#define _SUN4PROM_H_
8
9/*
10 * Although this looks similar to an romvec for a OpenProm machine, it is
11 * actually closer to what was used in the Sun2 and Sun3.
12 *
13 * V2 entries exist only in version 2 PROMs and later, V3 in version 3 and later.
14 *
15 * Many of the function prototypes are guesses. Some are certainly wrong.
16 * Use with care.
17 */
18
19typedef struct {
20 char *initSP; /* Initial system stack ptr */
21 void (*startmon)(void); /* Initial PC for hardware */
22 int *diagberr; /* Bus err handler for diags */
23 struct linux_arguments_v0 **bootParam; /* Info for bootstrapped pgm */
24 unsigned int *memorysize; /* Usable memory in bytes */
25 unsigned char (*getchar)(void); /* Get char from input device */
26 void (*putchar)(char); /* Put char to output device */
27 int (*mayget)(void); /* Maybe get char, or -1 */
28 int (*mayput)(int); /* Maybe put char, or -1 */
29 unsigned char *echo; /* Should getchar echo? */
30 unsigned char *insource; /* Input source selector */
31 unsigned char *outsink; /* Output sink selector */
32 int (*getkey)(void); /* Get next key if one exists */
33 void (*initgetkey)(void); /* Initialize get key */
34 unsigned int *translation; /* Kbd translation selector */
35 unsigned char *keybid; /* Keyboard ID byte */
36 int *screen_x; /* V2: Screen x pos (r/o) */
37 int *screen_y; /* V2: Screen y pos (r/o) */
38 struct keybuf *keybuf; /* Up/down keycode buffer */
39 char *monid; /* Monitor version ID */
40 void (*fbwritechar)(char); /* Write a character to FB */
41 int *fbAddr; /* Address of frame buffer */
42 char **font; /* Font table for FB */
43 void (*fbwritestr)(char *); /* Write string to FB */
44 void (*reboot)(char *); /* e.g. reboot("sd()vmlinux") */
45 unsigned char *linebuf; /* The line input buffer */
46 unsigned char **lineptr; /* Cur pointer into linebuf */
47 int *linesize; /* length of line in linebuf */
48 void (*getline)(char *); /* Get line from user */
49 unsigned char (*getnextchar)(void); /* Get next char from linebuf */
50 unsigned char (*peeknextchar)(void); /* Peek at next char */
51 int *fbthere; /* =1 if frame buffer there */
52 int (*getnum)(void); /* Grab hex num from line */
53 int (*printf)(char *, ...); /* See prom_printf() instead */
54 void (*printhex)(int); /* Format N digits in hex */
55 unsigned char *leds; /* RAM copy of LED register */
56 void (*setLEDs)(unsigned char *); /* Sets LED's and RAM copy */
57 void (*NMIaddr)(void *); /* Addr for level 7 vector */
58 void (*abortentry)(void); /* Entry for keyboard abort */
59 int *nmiclock; /* Counts up in msec */
60 int *FBtype; /* Frame buffer type */
61 unsigned int romvecversion; /* Version number for this romvec */
62 struct globram *globram; /* monitor global variables ??? */
63 void * kbdaddr; /* Addr of keyboard in use */
64 int *keyrinit; /* ms before kbd repeat */
65 unsigned char *keyrtick; /* ms between repetitions */
66 unsigned int *memoryavail; /* V1: Main mem usable size */
67 long *resetaddr; /* where to jump on a reset */
68 long *resetmap; /* pgmap entry for resetaddr */
69 void (*exittomon)(void); /* Exit from user program */
70 unsigned char **memorybitmap; /* V1: &{0 or &bits} */
71 void (*setcxsegmap)(int ctxt, char *va, int pmeg); /* Set seg in any context */
72 void (**vector_cmd)(void *); /* V2: Handler for 'v' cmd */
73 unsigned long *expectedtrapsig; /* V3: Location of the expected trap signal */
74 unsigned long *trapvectorbasetable; /* V3: Address of the trap vector table */
75 int unused1;
76 int unused2;
77 int unused3;
78 int unused4;
79} linux_sun4_romvec;
80
81extern linux_sun4_romvec *sun4_romvec;
82
83#endif /* _SUN4PROM_H_ */
diff --git a/arch/sparc/include/asm/system_32.h b/arch/sparc/include/asm/system_32.h
index b4b024445fc9..8623fc48fe24 100644
--- a/arch/sparc/include/asm/system_32.h
+++ b/arch/sparc/include/asm/system_32.h
@@ -34,13 +34,7 @@ enum sparc_cpu {
34 34
35extern enum sparc_cpu sparc_cpu_model; 35extern enum sparc_cpu sparc_cpu_model;
36 36
37#ifndef CONFIG_SUN4 37#define ARCH_SUN4C (sparc_cpu_model==sun4c)
38#define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
39#define ARCH_SUN4 0
40#else
41#define ARCH_SUN4C_SUN4 1
42#define ARCH_SUN4 1
43#endif
44 38
45#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */ 39#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
46 40
@@ -55,6 +49,7 @@ extern unsigned long empty_zero_page;
55extern void sun_do_break(void); 49extern void sun_do_break(void);
56extern int serial_console; 50extern int serial_console;
57extern int stop_a_enabled; 51extern int stop_a_enabled;
52extern int scons_pwroff;
58 53
59static inline int con_is_present(void) 54static inline int con_is_present(void)
60{ 55{
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h
index db9e742a406a..8759f2a1b837 100644
--- a/arch/sparc/include/asm/system_64.h
+++ b/arch/sparc/include/asm/system_64.h
@@ -26,9 +26,8 @@ enum sparc_cpu {
26 26
27#define sparc_cpu_model sun4u 27#define sparc_cpu_model sun4u
28 28
29/* This cannot ever be a sun4c nor sun4 :) That's just history. */ 29/* This cannot ever be a sun4c :) That's just history. */
30#define ARCH_SUN4C_SUN4 0 30#define ARCH_SUN4C 0
31#define ARCH_SUN4 0
32 31
33extern char reboot_command[]; 32extern char reboot_command[];
34 33
@@ -118,6 +117,7 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
118 117
119extern void sun_do_break(void); 118extern void sun_do_break(void);
120extern int stop_a_enabled; 119extern int stop_a_enabled;
120extern int scons_pwroff;
121 121
122extern void fault_in_user_windows(void); 122extern void fault_in_user_windows(void);
123extern void synchronize_user_stack(void); 123extern void synchronize_user_stack(void);
diff --git a/arch/sparc/include/asm/thread_info_32.h b/arch/sparc/include/asm/thread_info_32.h
index cbb892d0dff0..29899fd5b1b2 100644
--- a/arch/sparc/include/asm/thread_info_32.h
+++ b/arch/sparc/include/asm/thread_info_32.h
@@ -80,11 +80,7 @@ register struct thread_info *current_thread_info_reg asm("g6");
80/* 80/*
81 * thread information allocation 81 * thread information allocation
82 */ 82 */
83#if PAGE_SHIFT == 13
84#define THREAD_INFO_ORDER 0
85#else /* PAGE_SHIFT */
86#define THREAD_INFO_ORDER 1 83#define THREAD_INFO_ORDER 1
87#endif
88 84
89#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR 85#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
90 86
diff --git a/arch/sparc/include/asm/timer_32.h b/arch/sparc/include/asm/timer_32.h
index 361e53898dd7..2ec030ef3810 100644
--- a/arch/sparc/include/asm/timer_32.h
+++ b/arch/sparc/include/asm/timer_32.h
@@ -9,96 +9,9 @@
9#define _SPARC_TIMER_H 9#define _SPARC_TIMER_H
10 10
11#include <asm/system.h> /* For SUN4M_NCPUS */ 11#include <asm/system.h> /* For SUN4M_NCPUS */
12#include <asm/sun4paddr.h>
13#include <asm/btfixup.h> 12#include <asm/btfixup.h>
14 13
15/* Timer structures. The interrupt timer has two properties which
16 * are the counter (which is handled in do_timer in sched.c) and the limit.
17 * This limit is where the timer's counter 'wraps' around. Oddly enough,
18 * the sun4c timer when it hits the limit wraps back to 1 and not zero
19 * thus when calculating the value at which it will fire a microsecond you
20 * must adjust by one. Thanks SUN for designing such great hardware ;(
21 */
22
23/* Note that I am only going to use the timer that interrupts at
24 * Sparc IRQ 10. There is another one available that can fire at
25 * IRQ 14. Currently it is left untouched, we keep the PROM's limit
26 * register value and let the prom take these interrupts. This allows
27 * L1-A to work.
28 */
29
30struct sun4c_timer_info {
31 __volatile__ unsigned int cur_count10;
32 __volatile__ unsigned int timer_limit10;
33 __volatile__ unsigned int cur_count14;
34 __volatile__ unsigned int timer_limit14;
35};
36
37#define SUN4C_TIMER_PHYSADDR 0xf3000000
38#ifdef CONFIG_SUN4
39#define SUN_TIMER_PHYSADDR SUN4_300_TIMER_PHYSADDR
40#else
41#define SUN_TIMER_PHYSADDR SUN4C_TIMER_PHYSADDR
42#endif
43
44/* A sun4m has two blocks of registers which are probably of the same
45 * structure. LSI Logic's L64851 is told to _decrement_ from the limit
46 * value. Aurora behaves similarly but its limit value is compacted in
47 * other fashion (it's wider). Documented fields are defined here.
48 */
49
50/* As with the interrupt register, we have two classes of timer registers
51 * which are per-cpu and master. Per-cpu timers only hit that cpu and are
52 * only level 14 ticks, master timer hits all cpus and is level 10.
53 */
54
55#define SUN4M_PRM_CNT_L 0x80000000
56#define SUN4M_PRM_CNT_LVALUE 0x7FFFFC00
57
58struct sun4m_timer_percpu_info {
59 __volatile__ unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */
60 __volatile__ unsigned int l14_cur_count;
61
62 /* This register appears to be write only and/or inaccessible
63 * on Uni-Processor sun4m machines.
64 */
65 __volatile__ unsigned int l14_limit_noclear; /* Data access error is here */
66
67 __volatile__ unsigned int cntrl; /* =1 after POST on Aurora */
68 __volatile__ unsigned char space[PAGE_SIZE - 16];
69};
70
71struct sun4m_timer_regs {
72 struct sun4m_timer_percpu_info cpu_timers[SUN4M_NCPUS];
73 volatile unsigned int l10_timer_limit;
74 volatile unsigned int l10_cur_count;
75
76 /* Again, this appears to be write only and/or inaccessible
77 * on uni-processor sun4m machines.
78 */
79 volatile unsigned int l10_limit_noclear;
80
81 /* This register too, it must be magic. */
82 volatile unsigned int foobar;
83
84 volatile unsigned int cfg; /* equals zero at boot time... */
85};
86
87#define SUN4D_PRM_CNT_L 0x80000000
88#define SUN4D_PRM_CNT_LVALUE 0x7FFFFC00
89
90struct sun4d_timer_regs {
91 volatile unsigned int l10_timer_limit;
92 volatile unsigned int l10_cur_countx;
93 volatile unsigned int l10_limit_noclear;
94 volatile unsigned int ctrl;
95 volatile unsigned int l10_cur_count;
96};
97
98extern struct sun4d_timer_regs *sun4d_timers;
99
100extern __volatile__ unsigned int *master_l10_counter; 14extern __volatile__ unsigned int *master_l10_counter;
101extern __volatile__ unsigned int *master_l10_limit;
102 15
103/* FIXME: Make do_[gs]ettimeofday btfixup calls */ 16/* FIXME: Make do_[gs]ettimeofday btfixup calls */
104BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv) 17BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv)
diff --git a/arch/sparc/include/asm/vac-ops.h b/arch/sparc/include/asm/vac-ops.h
index d10527611f11..a63e88ef0426 100644
--- a/arch/sparc/include/asm/vac-ops.h
+++ b/arch/sparc/include/asm/vac-ops.h
@@ -76,11 +76,7 @@
76 * cacheable bit in the pte's of all such pages. 76 * cacheable bit in the pte's of all such pages.
77 */ 77 */
78 78
79#ifdef CONFIG_SUN4
80#define S4CVAC_BADBITS 0x0001e000
81#else
82#define S4CVAC_BADBITS 0x0000f000 79#define S4CVAC_BADBITS 0x0000f000
83#endif
84 80
85/* The following is true if vaddr1 and vaddr2 would cause 81/* The following is true if vaddr1 and vaddr2 would cause
86 * a 'bad alias'. 82 * a 'bad alias'.
@@ -94,10 +90,7 @@
94 */ 90 */
95struct sun4c_vac_props { 91struct sun4c_vac_props {
96 unsigned int num_bytes; /* Size of the cache */ 92 unsigned int num_bytes; /* Size of the cache */
97 unsigned int num_lines; /* Number of cache lines */
98 unsigned int do_hwflushes; /* Hardware flushing available? */ 93 unsigned int do_hwflushes; /* Hardware flushing available? */
99 enum { VAC_NONE, VAC_WRITE_THROUGH,
100 VAC_WRITE_BACK } type; /* What type of VAC? */
101 unsigned int linesize; /* Size of each line in bytes */ 94 unsigned int linesize; /* Size of each line in bytes */
102 unsigned int log2lsize; /* log2(linesize) */ 95 unsigned int log2lsize; /* log2(linesize) */
103 unsigned int on; /* VAC is enabled */ 96 unsigned int on; /* VAC is enabled */
diff --git a/arch/sparc/include/asm/vfc_ioctls.h b/arch/sparc/include/asm/vfc_ioctls.h
deleted file mode 100644
index af8b69007b22..000000000000
--- a/arch/sparc/include/asm/vfc_ioctls.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/* Copyright (c) 1996 by Manish Vachharajani */
2
3#ifndef _LINUX_VFC_IOCTLS_H_
4#define _LINUX_VFC_IOCTLS_H_
5
6 /* IOCTLs */
7#define VFC_IOCTL(a) (('j' << 8) | a)
8#define VFCGCTRL (VFC_IOCTL (0)) /* get vfc attributes */
9#define VFCSCTRL (VFC_IOCTL (1)) /* set vfc attributes */
10#define VFCGVID (VFC_IOCTL (2)) /* get video decoder attributes */
11#define VFCSVID (VFC_IOCTL (3)) /* set video decoder attributes */
12#define VFCHUE (VFC_IOCTL (4)) /* set hue */
13#define VFCPORTCHG (VFC_IOCTL (5)) /* change port */
14#define VFCRDINFO (VFC_IOCTL (6)) /* read info */
15
16 /* Options for setting the vfc attributes and status */
17#define MEMPRST 0x1 /* reset FIFO ptr. */
18#define CAPTRCMD 0x2 /* start capture and wait */
19#define DIAGMODE 0x3 /* diag mode */
20#define NORMMODE 0x4 /* normal mode */
21#define CAPTRSTR 0x5 /* start capture */
22#define CAPTRWAIT 0x6 /* wait for capture to finish */
23
24
25 /* Options for the decoder */
26#define STD_NTSC 0x1 /* NTSC mode */
27#define STD_PAL 0x2 /* PAL mode */
28#define COLOR_ON 0x3 /* force color ON */
29#define MONO 0x4 /* force color OFF */
30
31 /* Values returned by ioctl 2 */
32
33#define NO_LOCK 1
34#define NTSC_COLOR 2
35#define NTSC_NOCOLOR 3
36#define PAL_COLOR 4
37#define PAL_NOCOLOR 5
38
39/* Not too sure what this does yet */
40 /* Options for setting Field number */
41#define ODD_FIELD 0x1
42#define EVEN_FIELD 0x0
43#define ACTIVE_ONLY 0x2
44#define NON_ACTIVE 0x0
45
46/* Debug options */
47#define VFC_I2C_SEND 0
48#define VFC_I2C_RECV 1
49
50struct vfc_debug_inout
51{
52 unsigned long addr;
53 unsigned long ret;
54 unsigned long len;
55 unsigned char __user *buffer;
56};
57
58#endif /* _LINUX_VFC_IOCTLS_H_ */
diff --git a/arch/sparc/include/asm/visasm.h b/arch/sparc/include/asm/visasm.h
index de797b9bf552..39ca301920db 100644
--- a/arch/sparc/include/asm/visasm.h
+++ b/arch/sparc/include/asm/visasm.h
@@ -57,6 +57,7 @@ static inline void save_and_clear_fpu(void) {
57" " : : "i" (FPRS_FEF|FPRS_DU) : 57" " : : "i" (FPRS_FEF|FPRS_DU) :
58 "o5", "g1", "g2", "g3", "g7", "cc"); 58 "o5", "g1", "g2", "g3", "g7", "cc");
59} 59}
60extern int vis_emul(struct pt_regs *, unsigned int);
60#endif 61#endif
61 62
62#endif /* _SPARC64_ASI_H */ 63#endif /* _SPARC64_ASI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 09:00:51 -0500