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-rw-r--r--arch/sh/Kconfig9
-rw-r--r--arch/sh/Makefile1
-rw-r--r--arch/sh/kernel/traps.c164
-rw-r--r--arch/sh/math-emu/Makefile1
-rw-r--r--arch/sh/math-emu/math.c624
-rw-r--r--arch/sh/math-emu/sfp-util.h72
6 files changed, 832 insertions, 39 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index d1d724447826..07d6d699e9c2 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -339,6 +339,15 @@ config SH_FPU
339 339
340 This option must be set in order to enable the FPU. 340 This option must be set in order to enable the FPU.
341 341
342config SH_FPU_EMU
343 bool "FPU emulation support"
344 depends on !SH_FPU && EXPERIMENTAL
345 default n
346 help
347 Selecting this option will enable support for software FPU emulation.
348 Most SH-3 users will want to say Y here, whereas most SH-4 users will
349 want to say N.
350
342config SH_DSP 351config SH_DSP
343 bool "DSP support" 352 bool "DSP support"
344 depends on !CPU_SH4 353 depends on !CPU_SH4
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 859285d47a29..13b688b13e1c 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -79,6 +79,7 @@ head-y := arch/sh/kernel/head.o arch/sh/kernel/init_task.o
79LIBGCC := $(shell $(CC) $(CFLAGS) -print-libgcc-file-name) 79LIBGCC := $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
80 80
81core-y += arch/sh/kernel/ arch/sh/mm/ 81core-y += arch/sh/kernel/ arch/sh/mm/
82core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
82 83
83# Boards 84# Boards
84machdir-$(CONFIG_SH_SOLUTION_ENGINE) := se/770x 85machdir-$(CONFIG_SH_SOLUTION_ENGINE) := se/770x
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index 21bef1b5f991..95c810b3c97e 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -36,40 +36,15 @@
36 36
37#ifdef CONFIG_SH_KGDB 37#ifdef CONFIG_SH_KGDB
38#include <asm/kgdb.h> 38#include <asm/kgdb.h>
39#define CHK_REMOTE_DEBUG(regs) \ 39#define CHK_REMOTE_DEBUG(regs) \
40{ \ 40{ \
41 if ((kgdb_debug_hook != (kgdb_debug_hook_t *) NULL) && (!user_mode(regs))) \ 41 if (kgdb_debug_hook && !user_mode(regs))\
42 { \ 42 (*kgdb_debug_hook)(regs); \
43 (*kgdb_debug_hook)(regs); \
44 } \
45} 43}
46#else 44#else
47#define CHK_REMOTE_DEBUG(regs) 45#define CHK_REMOTE_DEBUG(regs)
48#endif 46#endif
49 47
50#define DO_ERROR(trapnr, signr, str, name, tsk) \
51asmlinkage void do_##name(unsigned long r4, unsigned long r5, \
52 unsigned long r6, unsigned long r7, \
53 struct pt_regs regs) \
54{ \
55 unsigned long error_code; \
56 \
57 /* Check if it's a DSP instruction */ \
58 if (is_dsp_inst(&regs)) { \
59 /* Enable DSP mode, and restart instruction. */ \
60 regs.sr |= SR_DSP; \
61 return; \
62 } \
63 \
64 asm volatile("stc r2_bank, %0": "=r" (error_code)); \
65 local_irq_enable(); \
66 tsk->thread.error_code = error_code; \
67 tsk->thread.trap_no = trapnr; \
68 CHK_REMOTE_DEBUG(&regs); \
69 force_sig(signr, tsk); \
70 die_if_no_fixup(str,&regs,error_code); \
71}
72
73#ifdef CONFIG_CPU_SH2 48#ifdef CONFIG_CPU_SH2
74#define TRAP_RESERVED_INST 4 49#define TRAP_RESERVED_INST 4
75#define TRAP_ILLEGAL_SLOT_INST 6 50#define TRAP_ILLEGAL_SLOT_INST 6
@@ -575,8 +550,117 @@ int is_dsp_inst(struct pt_regs *regs)
575#define is_dsp_inst(regs) (0) 550#define is_dsp_inst(regs) (0)
576#endif /* CONFIG_SH_DSP */ 551#endif /* CONFIG_SH_DSP */
577 552
578DO_ERROR(TRAP_RESERVED_INST, SIGILL, "reserved instruction", reserved_inst, current) 553extern int do_fpu_inst(unsigned short, struct pt_regs*);
579DO_ERROR(TRAP_ILLEGAL_SLOT_INST, SIGILL, "illegal slot instruction", illegal_slot_inst, current) 554
555asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
556 unsigned long r6, unsigned long r7,
557 struct pt_regs regs)
558{
559 unsigned long error_code;
560 struct task_struct *tsk = current;
561
562#ifdef CONFIG_SH_FPU_EMU
563 unsigned short inst;
564 int err;
565
566 get_user(inst, (unsigned short*)regs.pc);
567
568 err = do_fpu_inst(inst, &regs);
569 if (!err) {
570 regs.pc += 2;
571 return;
572 }
573 /* not a FPU inst. */
574#endif
575
576#ifdef CONFIG_SH_DSP
577 /* Check if it's a DSP instruction */
578 if (is_dsp_inst(&regs)) {
579 /* Enable DSP mode, and restart instruction. */
580 regs.sr |= SR_DSP;
581 return;
582 }
583#endif
584
585 asm volatile("stc r2_bank, %0": "=r" (error_code));
586 local_irq_enable();
587 tsk->thread.error_code = error_code;
588 tsk->thread.trap_no = TRAP_RESERVED_INST;
589 CHK_REMOTE_DEBUG(&regs);
590 force_sig(SIGILL, tsk);
591 die_if_no_fixup("reserved instruction", &regs, error_code);
592}
593
594#ifdef CONFIG_SH_FPU_EMU
595static int emulate_branch(unsigned short inst, struct pt_regs* regs)
596{
597 /*
598 * bfs: 8fxx: PC+=d*2+4;
599 * bts: 8dxx: PC+=d*2+4;
600 * bra: axxx: PC+=D*2+4;
601 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
602 * braf:0x23: PC+=Rn*2+4;
603 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
604 * jmp: 4x2b: PC=Rn;
605 * jsr: 4x0b: PC=Rn after PR=PC+4;
606 * rts: 000b: PC=PR;
607 */
608 if ((inst & 0xfd00) == 0x8d00) {
609 regs->pc += SH_PC_8BIT_OFFSET(inst);
610 return 0;
611 }
612
613 if ((inst & 0xe000) == 0xa000) {
614 regs->pc += SH_PC_12BIT_OFFSET(inst);
615 return 0;
616 }
617
618 if ((inst & 0xf0df) == 0x0003) {
619 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
620 return 0;
621 }
622
623 if ((inst & 0xf0df) == 0x400b) {
624 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
625 return 0;
626 }
627
628 if ((inst & 0xffff) == 0x000b) {
629 regs->pc = regs->pr;
630 return 0;
631 }
632
633 return 1;
634}
635#endif
636
637asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
638 unsigned long r6, unsigned long r7,
639 struct pt_regs regs)
640{
641 unsigned long error_code;
642 struct task_struct *tsk = current;
643#ifdef CONFIG_SH_FPU_EMU
644 unsigned short inst;
645
646 get_user(inst, (unsigned short *)regs.pc + 1);
647 if (!do_fpu_inst(inst, &regs)) {
648 get_user(inst, (unsigned short *)regs.pc);
649 if (!emulate_branch(inst, &regs))
650 return;
651 /* fault in branch.*/
652 }
653 /* not a FPU inst. */
654#endif
655
656 asm volatile("stc r2_bank, %0": "=r" (error_code));
657 local_irq_enable();
658 tsk->thread.error_code = error_code;
659 tsk->thread.trap_no = TRAP_RESERVED_INST;
660 CHK_REMOTE_DEBUG(&regs);
661 force_sig(SIGILL, tsk);
662 die_if_no_fixup("illegal slot instruction", &regs, error_code);
663}
580 664
581asmlinkage void do_exception_error(unsigned long r4, unsigned long r5, 665asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
582 unsigned long r6, unsigned long r7, 666 unsigned long r6, unsigned long r7,
@@ -634,14 +718,16 @@ void __init trap_init(void)
634 exception_handling_table[TRAP_ILLEGAL_SLOT_INST] 718 exception_handling_table[TRAP_ILLEGAL_SLOT_INST]
635 = (void *)do_illegal_slot_inst; 719 = (void *)do_illegal_slot_inst;
636 720
637#ifdef CONFIG_CPU_SH4 721#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
638 if (!(cpu_data->flags & CPU_HAS_FPU)) { 722 defined(CONFIG_SH_FPU_EMU)
639 /* For SH-4 lacking an FPU, treat floating point instructions 723 /*
640 as reserved. */ 724 * For SH-4 lacking an FPU, treat floating point instructions as
641 /* entry 64 corresponds to EXPEVT=0x800 */ 725 * reserved. They'll be handled in the math-emu case, or faulted on
642 exception_handling_table[64] = (void *)do_reserved_inst; 726 * otherwise.
643 exception_handling_table[65] = (void *)do_illegal_slot_inst; 727 */
644 } 728 /* entry 64 corresponds to EXPEVT=0x800 */
729 exception_handling_table[64] = (void *)do_reserved_inst;
730 exception_handling_table[65] = (void *)do_illegal_slot_inst;
645#endif 731#endif
646 732
647 /* Setup VBR for boot cpu */ 733 /* Setup VBR for boot cpu */
diff --git a/arch/sh/math-emu/Makefile b/arch/sh/math-emu/Makefile
new file mode 100644
index 000000000000..638b342c781a
--- /dev/null
+++ b/arch/sh/math-emu/Makefile
@@ -0,0 +1 @@
obj-y := math.o
diff --git a/arch/sh/math-emu/math.c b/arch/sh/math-emu/math.c
new file mode 100644
index 000000000000..26b6046814fd
--- /dev/null
+++ b/arch/sh/math-emu/math.c
@@ -0,0 +1,624 @@
1/*
2 * arch/sh/math-emu/math.c
3 *
4 * Copyright (C) 2006 Takashi YOSHII <takasi-y@ops.dti.ne.jp>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/config.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/types.h>
14#include <linux/sched.h>
15#include <linux/signal.h>
16
17#include <asm/system.h>
18#include <asm/uaccess.h>
19#include <asm/processor.h>
20#include <asm/io.h>
21
22#include "sfp-util.h"
23#include <math-emu/soft-fp.h>
24#include <math-emu/single.h>
25#include <math-emu/double.h>
26
27#define FPUL (fregs->fpul)
28#define FPSCR (fregs->fpscr)
29#define FPSCR_RM (FPSCR&3)
30#define FPSCR_DN ((FPSCR>>18)&1)
31#define FPSCR_PR ((FPSCR>>19)&1)
32#define FPSCR_SZ ((FPSCR>>20)&1)
33#define FPSCR_FR ((FPSCR>>21)&1)
34#define FPSCR_MASK 0x003fffffUL
35
36#define BANK(n) (n^(FPSCR_FR?16:0))
37#define FR ((unsigned long*)(fregs->fp_regs))
38#define FR0 (FR[BANK(0)])
39#define FRn (FR[BANK(n)])
40#define FRm (FR[BANK(m)])
41#define DR ((unsigned long long*)(fregs->fp_regs))
42#define DRn (DR[BANK(n)/2])
43#define DRm (DR[BANK(m)/2])
44
45#define XREG(n) (n^16)
46#define XFn (FR[BANK(XREG(n))])
47#define XFm (FR[BANK(XREG(m))])
48#define XDn (DR[BANK(XREG(n))/2])
49#define XDm (DR[BANK(XREG(m))/2])
50
51#define R0 (regs->regs[0])
52#define Rn (regs->regs[n])
53#define Rm (regs->regs[m])
54
55#define WRITE(d,a) ({if(put_user(d, (typeof (d)*)a)) return -EFAULT;})
56#define READ(d,a) ({if(get_user(d, (typeof (d)*)a)) return -EFAULT;})
57
58#define PACK_S(r,f) FP_PACK_SP(&r,f)
59#define UNPACK_S(f,r) FP_UNPACK_SP(f,&r)
60#define PACK_D(r,f) \
61 {u32 t[2]; FP_PACK_DP(t,f); ((u32*)&r)[0]=t[1]; ((u32*)&r)[1]=t[0];}
62#define UNPACK_D(f,r) \
63 {u32 t[2]; t[0]=((u32*)&r)[1]; t[1]=((u32*)&r)[0]; FP_UNPACK_DP(f,t);}
64
65// 2 args instructions.
66#define BOTH_PRmn(op,x) \
67 FP_DECL_EX; if(FPSCR_PR) op(D,x,DRm,DRn); else op(S,x,FRm,FRn);
68
69#define CMP_X(SZ,R,M,N) do{ \
70 FP_DECL_##SZ(Fm); FP_DECL_##SZ(Fn); \
71 UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
72 FP_CMP_##SZ(R, Fn, Fm, 2); }while(0)
73#define EQ_X(SZ,R,M,N) do{ \
74 FP_DECL_##SZ(Fm); FP_DECL_##SZ(Fn); \
75 UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
76 FP_CMP_EQ_##SZ(R, Fn, Fm); }while(0)
77#define CMP(OP) ({ int r; BOTH_PRmn(OP##_X,r); r; })
78
79static int
80fcmp_gt(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
81{
82 if (CMP(CMP) > 0)
83 regs->sr |= 1;
84 else
85 regs->sr &= ~1;
86
87 return 0;
88}
89
90static int
91fcmp_eq(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
92{
93 if (CMP(CMP /*EQ*/) == 0)
94 regs->sr |= 1;
95 else
96 regs->sr &= ~1;
97 return 0;
98}
99
100#define ARITH_X(SZ,OP,M,N) do{ \
101 FP_DECL_##SZ(Fm); FP_DECL_##SZ(Fn); FP_DECL_##SZ(Fr); \
102 UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
103 FP_##OP##_##SZ(Fr, Fn, Fm); \
104 PACK_##SZ(N, Fr); }while(0)
105
106static int
107fadd(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
108{
109 BOTH_PRmn(ARITH_X, ADD);
110 return 0;
111}
112
113static int
114fsub(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
115{
116 BOTH_PRmn(ARITH_X, SUB);
117 return 0;
118}
119
120static int
121fmul(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
122{
123 BOTH_PRmn(ARITH_X, MUL);
124 return 0;
125}
126
127static int
128fdiv(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
129{
130 BOTH_PRmn(ARITH_X, DIV);
131 return 0;
132}
133
134static int
135fmac(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
136{
137 FP_DECL_EX;
138 FP_DECL_S(Fr);
139 FP_DECL_S(Ft);
140 FP_DECL_S(F0);
141 FP_DECL_S(Fm);
142 FP_DECL_S(Fn);
143 UNPACK_S(F0, FR0);
144 UNPACK_S(Fm, FRm);
145 UNPACK_S(Fn, FRn);
146 FP_MUL_S(Ft, Fm, F0);
147 FP_ADD_S(Fr, Fn, Ft);
148 PACK_S(FRn, Fr);
149 return 0;
150}
151
152// to process fmov's extention (odd n for DR access XD).
153#define FMOV_EXT(x) if(x&1) x+=16-1
154
155static int
156fmov_idx_reg(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
157 int n)
158{
159 if (FPSCR_SZ) {
160 FMOV_EXT(n);
161 READ(FRn, Rm + R0 + 4);
162 n++;
163 READ(FRn, Rm + R0);
164 } else {
165 READ(FRn, Rm + R0);
166 }
167
168 return 0;
169}
170
171static int
172fmov_mem_reg(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
173 int n)
174{
175 if (FPSCR_SZ) {
176 FMOV_EXT(n);
177 READ(FRn, Rm + 4);
178 n++;
179 READ(FRn, Rm);
180 } else {
181 READ(FRn, Rm);
182 }
183
184 return 0;
185}
186
187static int
188fmov_inc_reg(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
189 int n)
190{
191 if (FPSCR_SZ) {
192 FMOV_EXT(n);
193 READ(FRn, Rm + 4);
194 n++;
195 READ(FRn, Rm);
196 Rm += 8;
197 } else {
198 READ(FRn, Rm);
199 Rm += 4;
200 }
201
202 return 0;
203}
204
205static int
206fmov_reg_idx(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
207 int n)
208{
209 if (FPSCR_SZ) {
210 FMOV_EXT(m);
211 WRITE(FRm, Rn + R0 + 4);
212 m++;
213 WRITE(FRm, Rn + R0);
214 } else {
215 WRITE(FRm, Rn + R0);
216 }
217
218 return 0;
219}
220
221static int
222fmov_reg_mem(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
223 int n)
224{
225 if (FPSCR_SZ) {
226 FMOV_EXT(m);
227 WRITE(FRm, Rn + 4);
228 m++;
229 WRITE(FRm, Rn);
230 } else {
231 WRITE(FRm, Rn);
232 }
233
234 return 0;
235}
236
237static int
238fmov_reg_dec(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
239 int n)
240{
241 if (FPSCR_SZ) {
242 FMOV_EXT(m);
243 Rn -= 8;
244 WRITE(FRm, Rn + 4);
245 m++;
246 WRITE(FRm, Rn);
247 } else {
248 Rn -= 4;
249 WRITE(FRm, Rn);
250 }
251
252 return 0;
253}
254
255static int
256fmov_reg_reg(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
257 int n)
258{
259 if (FPSCR_SZ) {
260 FMOV_EXT(m);
261 FMOV_EXT(n);
262 DRn = DRm;
263 } else {
264 FRn = FRm;
265 }
266
267 return 0;
268}
269
270static int
271fnop_mn(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
272{
273 return -EINVAL;
274}
275
276// 1 arg instructions.
277#define NOTYETn(i) static int i(struct sh_fpu_soft_struct *fregs, int n) \
278 { printk( #i " not yet done.\n"); return 0; }
279
280NOTYETn(ftrv)
281NOTYETn(fsqrt)
282NOTYETn(fipr)
283NOTYETn(fsca)
284NOTYETn(fsrra)
285
286#define EMU_FLOAT_X(SZ,N) do { \
287 FP_DECL_##SZ(Fn); \
288 FP_FROM_INT_##SZ(Fn, FPUL, 32, int); \
289 PACK_##SZ(N, Fn); }while(0)
290static int ffloat(struct sh_fpu_soft_struct *fregs, int n)
291{
292 FP_DECL_EX;
293
294 if (FPSCR_PR)
295 EMU_FLOAT_X(D, DRn);
296 else
297 EMU_FLOAT_X(S, FRn);
298
299 return 0;
300}
301
302#define EMU_FTRC_X(SZ,N) do { \
303 FP_DECL_##SZ(Fn); \
304 UNPACK_##SZ(Fn, N); \
305 FP_TO_INT_##SZ(FPUL, Fn, 32, 1); }while(0)
306static int ftrc(struct sh_fpu_soft_struct *fregs, int n)
307{
308 FP_DECL_EX;
309
310 if (FPSCR_PR)
311 EMU_FTRC_X(D, DRn);
312 else
313 EMU_FTRC_X(S, FRn);
314
315 return 0;
316}
317
318static int fcnvsd(struct sh_fpu_soft_struct *fregs, int n)
319{
320 FP_DECL_EX;
321 FP_DECL_S(Fn);
322 FP_DECL_D(Fr);
323 UNPACK_S(Fn, FPUL);
324 FP_CONV(D, S, 2, 1, Fr, Fn);
325 PACK_D(DRn, Fr);
326 return 0;
327}
328
329static int fcnvds(struct sh_fpu_soft_struct *fregs, int n)
330{
331 FP_DECL_EX;
332 FP_DECL_D(Fn);
333 FP_DECL_S(Fr);
334 UNPACK_D(Fn, DRn);
335 FP_CONV(S, D, 1, 2, Fr, Fn);
336 PACK_S(FPUL, Fr);
337 return 0;
338}
339
340static int fxchg(struct sh_fpu_soft_struct *fregs, int flag)
341{
342 FPSCR ^= flag;
343 return 0;
344}
345
346static int fsts(struct sh_fpu_soft_struct *fregs, int n)
347{
348 FRn = FPUL;
349 return 0;
350}
351
352static int flds(struct sh_fpu_soft_struct *fregs, int n)
353{
354 FPUL = FRn;
355 return 0;
356}
357
358static int fneg(struct sh_fpu_soft_struct *fregs, int n)
359{
360 FRn ^= (1 << (_FP_W_TYPE_SIZE - 1));
361 return 0;
362}
363
364static int fabs(struct sh_fpu_soft_struct *fregs, int n)
365{
366 FRn &= ~(1 << (_FP_W_TYPE_SIZE - 1));
367 return 0;
368}
369
370static int fld0(struct sh_fpu_soft_struct *fregs, int n)
371{
372 FRn = 0;
373 return 0;
374}
375
376static int fld1(struct sh_fpu_soft_struct *fregs, int n)
377{
378 FRn = (_FP_EXPBIAS_S << (_FP_FRACBITS_S - 1));
379 return 0;
380}
381
382static int fnop_n(struct sh_fpu_soft_struct *fregs, int n)
383{
384 return -EINVAL;
385}
386
387/// Instruction decoders.
388
389static int id_fxfd(struct sh_fpu_soft_struct *, int);
390static int id_fnxd(struct sh_fpu_soft_struct *, struct pt_regs *, int, int);
391
392static int (*fnxd[])(struct sh_fpu_soft_struct *, int) = {
393 fsts, flds, ffloat, ftrc, fneg, fabs, fsqrt, fsrra,
394 fld0, fld1, fcnvsd, fcnvds, fnop_n, fnop_n, fipr, id_fxfd
395};
396
397static int (*fnmx[])(struct sh_fpu_soft_struct *, struct pt_regs *, int, int) = {
398 fadd, fsub, fmul, fdiv, fcmp_eq, fcmp_gt, fmov_idx_reg, fmov_reg_idx,
399 fmov_mem_reg, fmov_inc_reg, fmov_reg_mem, fmov_reg_dec,
400 fmov_reg_reg, id_fnxd, fmac, fnop_mn};
401
402static int id_fxfd(struct sh_fpu_soft_struct *fregs, int x)
403{
404 const int flag[] = { FPSCR_SZ, FPSCR_PR, FPSCR_FR, 0 };
405 switch (x & 3) {
406 case 3:
407 fxchg(fregs, flag[x >> 2]);
408 break;
409 case 1:
410 ftrv(fregs, x - 1);
411 break;
412 default:
413 fsca(fregs, x);
414 }
415 return 0;
416}
417
418static int
419id_fnxd(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int x, int n)
420{
421 return (fnxd[x])(fregs, n);
422}
423
424static int
425id_fnmx(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, u16 code)
426{
427 int n = (code >> 8) & 0xf, m = (code >> 4) & 0xf, x = code & 0xf;
428 return (fnmx[x])(fregs, regs, m, n);
429}
430
431static int
432id_sys(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, u16 code)
433{
434 int n = ((code >> 8) & 0xf);
435 unsigned long *reg = (code & 0x0010) ? &FPUL : &FPSCR;
436
437 switch (code & 0xf0ff) {
438 case 0x005a:
439 case 0x006a:
440 Rn = *reg;
441 break;
442 case 0x405a:
443 case 0x406a:
444 *reg = Rn;
445 break;
446 case 0x4052:
447 case 0x4062:
448 Rn -= 4;
449 WRITE(*reg, Rn);
450 break;
451 case 0x4056:
452 case 0x4066:
453 READ(*reg, Rn);
454 Rn += 4;
455 break;
456 default:
457 return -EINVAL;
458 }
459
460 return 0;
461}
462
463static int fpu_emulate(u16 code, struct sh_fpu_soft_struct *fregs, struct pt_regs *regs)
464{
465 if ((code & 0xf000) == 0xf000)
466 return id_fnmx(fregs, regs, code);
467 else
468 return id_sys(fregs, regs, code);
469}
470
471/**
472 * denormal_to_double - Given denormalized float number,
473 * store double float
474 *
475 * @fpu: Pointer to sh_fpu_hard structure
476 * @n: Index to FP register
477 */
478static void denormal_to_double(struct sh_fpu_hard_struct *fpu, int n)
479{
480 unsigned long du, dl;
481 unsigned long x = fpu->fpul;
482 int exp = 1023 - 126;
483
484 if (x != 0 && (x & 0x7f800000) == 0) {
485 du = (x & 0x80000000);
486 while ((x & 0x00800000) == 0) {
487 x <<= 1;
488 exp--;
489 }
490 x &= 0x007fffff;
491 du |= (exp << 20) | (x >> 3);
492 dl = x << 29;
493
494 fpu->fp_regs[n] = du;
495 fpu->fp_regs[n+1] = dl;
496 }
497}
498
499/**
500 * ieee_fpe_handler - Handle denormalized number exception
501 *
502 * @regs: Pointer to register structure
503 *
504 * Returns 1 when it's handled (should not cause exception).
505 */
506static int ieee_fpe_handler(struct pt_regs *regs)
507{
508 unsigned short insn = *(unsigned short *)regs->pc;
509 unsigned short finsn;
510 unsigned long nextpc;
511 int nib[4] = {
512 (insn >> 12) & 0xf,
513 (insn >> 8) & 0xf,
514 (insn >> 4) & 0xf,
515 insn & 0xf};
516
517 if (nib[0] == 0xb ||
518 (nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb)) /* bsr & jsr */
519 regs->pr = regs->pc + 4;
520
521 if (nib[0] == 0xa || nib[0] == 0xb) { /* bra & bsr */
522 nextpc = regs->pc + 4 + ((short) ((insn & 0xfff) << 4) >> 3);
523 finsn = *(unsigned short *) (regs->pc + 2);
524 } else if (nib[0] == 0x8 && nib[1] == 0xd) { /* bt/s */
525 if (regs->sr & 1)
526 nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
527 else
528 nextpc = regs->pc + 4;
529 finsn = *(unsigned short *) (regs->pc + 2);
530 } else if (nib[0] == 0x8 && nib[1] == 0xf) { /* bf/s */
531 if (regs->sr & 1)
532 nextpc = regs->pc + 4;
533 else
534 nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
535 finsn = *(unsigned short *) (regs->pc + 2);
536 } else if (nib[0] == 0x4 && nib[3] == 0xb &&
537 (nib[2] == 0x0 || nib[2] == 0x2)) { /* jmp & jsr */
538 nextpc = regs->regs[nib[1]];
539 finsn = *(unsigned short *) (regs->pc + 2);
540 } else if (nib[0] == 0x0 && nib[3] == 0x3 &&
541 (nib[2] == 0x0 || nib[2] == 0x2)) { /* braf & bsrf */
542 nextpc = regs->pc + 4 + regs->regs[nib[1]];
543 finsn = *(unsigned short *) (regs->pc + 2);
544 } else if (insn == 0x000b) { /* rts */
545 nextpc = regs->pr;
546 finsn = *(unsigned short *) (regs->pc + 2);
547 } else {
548 nextpc = regs->pc + 2;
549 finsn = insn;
550 }
551
552 if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */
553 struct task_struct *tsk = current;
554
555 if ((tsk->thread.fpu.hard.fpscr & (1 << 17))) {
556 /* FPU error */
557 denormal_to_double (&tsk->thread.fpu.hard,
558 (finsn >> 8) & 0xf);
559 tsk->thread.fpu.hard.fpscr &=
560 ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
561 set_tsk_thread_flag(tsk, TIF_USEDFPU);
562 } else {
563 tsk->thread.trap_no = 11;
564 tsk->thread.error_code = 0;
565 force_sig(SIGFPE, tsk);
566 }
567
568 regs->pc = nextpc;
569 return 1;
570 }
571
572 return 0;
573}
574
575asmlinkage void do_fpu_error(unsigned long r4, unsigned long r5,
576 unsigned long r6, unsigned long r7,
577 struct pt_regs regs)
578{
579 struct task_struct *tsk = current;
580
581 if (ieee_fpe_handler (&regs))
582 return;
583
584 regs.pc += 2;
585 tsk->thread.trap_no = 11;
586 tsk->thread.error_code = 0;
587 force_sig(SIGFPE, tsk);
588}
589
590/**
591 * fpu_init - Initialize FPU registers
592 * @fpu: Pointer to software emulated FPU registers.
593 */
594static void fpu_init(struct sh_fpu_soft_struct *fpu)
595{
596 int i;
597
598 fpu->fpscr = FPSCR_INIT;
599 fpu->fpul = 0;
600
601 for (i = 0; i < 16; i++) {
602 fpu->fp_regs[i] = 0;
603 fpu->xfp_regs[i]= 0;
604 }
605}
606
607/**
608 * do_fpu_inst - Handle reserved instructions for FPU emulation
609 * @inst: instruction code.
610 * @regs: registers on stack.
611 */
612int do_fpu_inst(unsigned short inst, struct pt_regs *regs)
613{
614 struct task_struct *tsk = current;
615 struct sh_fpu_soft_struct *fpu = &(tsk->thread.fpu.soft);
616
617 if (!test_tsk_thread_flag(tsk, TIF_USEDFPU)) {
618 /* initialize once. */
619 fpu_init(fpu);
620 set_tsk_thread_flag(tsk, TIF_USEDFPU);
621 }
622
623 return fpu_emulate(inst, fpu, regs);
624}
diff --git a/arch/sh/math-emu/sfp-util.h b/arch/sh/math-emu/sfp-util.h
new file mode 100644
index 000000000000..8ae1bd310ad0
--- /dev/null
+++ b/arch/sh/math-emu/sfp-util.h
@@ -0,0 +1,72 @@
1/*
2 * These are copied from glibc/stdlib/longlong.h
3 */
4
5#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
6 do { \
7 UWtype __x; \
8 __x = (al) + (bl); \
9 (sh) = (ah) + (bh) + (__x < (al)); \
10 (sl) = __x; \
11 } while (0)
12
13#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
14 do { \
15 UWtype __x; \
16 __x = (al) - (bl); \
17 (sh) = (ah) - (bh) - (__x > (al)); \
18 (sl) = __x; \
19 } while (0)
20
21#define umul_ppmm(w1, w0, u, v) \
22 __asm__ ("dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
23 : "=r" ((u32)(w1)), "=r" ((u32)(w0)) \
24 : "r" ((u32)(u)), "r" ((u32)(v)) \
25 : "macl", "mach")
26
27#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
28#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
29#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
30
31#define udiv_qrnnd(q, r, n1, n0, d) \
32 do { \
33 UWtype __d1, __d0, __q1, __q0; \
34 UWtype __r1, __r0, __m; \
35 __d1 = __ll_highpart (d); \
36 __d0 = __ll_lowpart (d); \
37 \
38 __r1 = (n1) % __d1; \
39 __q1 = (n1) / __d1; \
40 __m = (UWtype) __q1 * __d0; \
41 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
42 if (__r1 < __m) \
43 { \
44 __q1--, __r1 += (d); \
45 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
46 if (__r1 < __m) \
47 __q1--, __r1 += (d); \
48 } \
49 __r1 -= __m; \
50 \
51 __r0 = __r1 % __d1; \
52 __q0 = __r1 / __d1; \
53 __m = (UWtype) __q0 * __d0; \
54 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
55 if (__r0 < __m) \
56 { \
57 __q0--, __r0 += (d); \
58 if (__r0 >= (d)) \
59 if (__r0 < __m) \
60 __q0--, __r0 += (d); \
61 } \
62 __r0 -= __m; \
63 \
64 (q) = (UWtype) __q1 * __ll_B | __q0; \
65 (r) = __r0; \
66 } while (0)
67
68#define abort() return 0
69
70#define __BYTE_ORDER __LITTLE_ENDIAN
71
72
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 18:30:48 -0500