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-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c50
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 3ef5825ffa9e..9ff8a448a0a3 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -712,6 +712,56 @@ static struct clk sh7722_mstpcr_clocks[] = {
712 MSTPCR("vpu0", "bus_clk", 2, 1), 712 MSTPCR("vpu0", "bus_clk", 2, 1),
713 MSTPCR("lcdc0", "bus_clk", 2, 0), 713 MSTPCR("lcdc0", "bus_clk", 2, 0),
714#endif 714#endif
715#if defined(CONFIG_CPU_SUBTYPE_SH7723)
716 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
717 MSTPCR("tlb0", "cpu_clk", 0, 31),
718 MSTPCR("ic0", "cpu_clk", 0, 30),
719 MSTPCR("oc0", "cpu_clk", 0, 29),
720 MSTPCR("l2c0", "sh_clk", 0, 28),
721 MSTPCR("ilmem0", "cpu_clk", 0, 27),
722 MSTPCR("fpu0", "cpu_clk", 0, 24),
723 MSTPCR("intc0", "cpu_clk", 0, 22),
724 MSTPCR("dmac0", "bus_clk", 0, 21),
725 MSTPCR("sh0", "sh_clk", 0, 20),
726 MSTPCR("hudi0", "peripheral_clk", 0, 19),
727 MSTPCR("ubc0", "cpu_clk", 0, 17),
728 MSTPCR("tmu0", "peripheral_clk", 0, 15),
729 MSTPCR("cmt0", "r_clk", 0, 14),
730 MSTPCR("rwdt0", "r_clk", 0, 13),
731 MSTPCR("dmac1", "bus_clk", 0, 12),
732 MSTPCR("tmu1", "peripheral_clk", 0, 11),
733 MSTPCR("flctl0", "peripheral_clk", 0, 10),
734 MSTPCR("scif0", "peripheral_clk", 0, 9),
735 MSTPCR("scif1", "peripheral_clk", 0, 8),
736 MSTPCR("scif2", "peripheral_clk", 0, 7),
737 MSTPCR("scif3", "bus_clk", 0, 6),
738 MSTPCR("scif4", "bus_clk", 0, 5),
739 MSTPCR("scif5", "bus_clk", 0, 4),
740 MSTPCR("msiof0", "bus_clk", 0, 2),
741 MSTPCR("msiof1", "bus_clk", 0, 1),
742 MSTPCR("meram0", "sh_clk", 0, 0),
743 MSTPCR("i2c0", "peripheral_clk", 1, 9),
744 MSTPCR("rtc0", "r_clk", 1, 8),
745 MSTPCR("atapi0", "sh_clk", 2, 28),
746 MSTPCR("adc0", "peripheral_clk", 2, 28),
747 MSTPCR("tpu0", "bus_clk", 2, 25),
748 MSTPCR("irda0", "peripheral_clk", 2, 24),
749 MSTPCR("tsif0", "bus_clk", 2, 22),
750 MSTPCR("icb0", "bus_clk", 2, 21),
751 MSTPCR("sdhi0", "bus_clk", 2, 18),
752 MSTPCR("sdhi1", "bus_clk", 2, 17),
753 MSTPCR("keysc0", "r_clk", 2, 14),
754 MSTPCR("usb0", "bus_clk", 2, 11),
755 MSTPCR("2dg0", "bus_clk", 2, 10),
756 MSTPCR("siu0", "bus_clk", 2, 8),
757 MSTPCR("veu1", "bus_clk", 2, 6),
758 MSTPCR("vou0", "bus_clk", 2, 5),
759 MSTPCR("beu0", "bus_clk", 2, 4),
760 MSTPCR("ceu0", "bus_clk", 2, 3),
761 MSTPCR("veu0", "bus_clk", 2, 2),
762 MSTPCR("vpu0", "bus_clk", 2, 1),
763 MSTPCR("lcdc0", "bus_clk", 2, 0),
764#endif
715}; 765};
716 766
717static struct clk *sh7722_clocks[] = { 767static struct clk *sh7722_clocks[] = {