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-rw-r--r--arch/sh/boards/board-sh7785lcr.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
index 33b194b0454d..c2894c5b71ea 100644
--- a/arch/sh/boards/board-sh7785lcr.c
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -24,6 +24,7 @@
24#include <mach/sh7785lcr.h> 24#include <mach/sh7785lcr.h>
25#include <asm/heartbeat.h> 25#include <asm/heartbeat.h>
26#include <asm/clock.h> 26#include <asm/clock.h>
27#include <cpu/sh7785.h>
27 28
28/* 29/*
29 * NOTE: This board has 2 physical memory maps. 30 * NOTE: This board has 2 physical memory maps.
@@ -320,6 +321,26 @@ static void __init sh7785lcr_setup(char **cmdline_p)
320 writel(0x000307c2, sm501_reg); 321 writel(0x000307c2, sm501_reg);
321} 322}
322 323
324/* Return the board specific boot mode pin configuration */
325static int sh7785lcr_mode_pins(void)
326{
327 int value = 0;
328
329 /* These are the factory default settings of S1 and S2.
330 * If you change these dip switches then you will need to
331 * adjust the values below as well.
332 */
333 value |= 1 << MODE_PIN_MODE4; /* Clock Mode 16 */
334 value |= 1 << MODE_PIN_MODE5; /* 32-bit Area0 bus width */
335 value |= 1 << MODE_PIN_MODE6; /* 32-bit Area0 bus width */
336 value |= 1 << MODE_PIN_MODE7; /* Area 0 SRAM interface [fixed] */
337 value |= 1 << MODE_PIN_MODE8; /* Little Endian */
338 value |= 1 << MODE_PIN_MODE9; /* Master Mode */
339 value |= 1 << MODE_PIN_MODE14; /* No PLL step-up */
340
341 return value;
342}
343
323/* 344/*
324 * The Machine Vector 345 * The Machine Vector
325 */ 346 */
@@ -328,5 +349,6 @@ static struct sh_machine_vector mv_sh7785lcr __initmv = {
328 .mv_setup = sh7785lcr_setup, 349 .mv_setup = sh7785lcr_setup,
329 .mv_clk_init = sh7785lcr_clk_init, 350 .mv_clk_init = sh7785lcr_clk_init,
330 .mv_init_irq = init_sh7785lcr_IRQ, 351 .mv_init_irq = init_sh7785lcr_IRQ,
352 .mv_mode_pins = sh7785lcr_mode_pins,
331}; 353};
332 354