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-rw-r--r--arch/sh/mm/cache-sh4.c22
1 files changed, 10 insertions, 12 deletions
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index a98c7d8984fa..519e2d16cd06 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -26,7 +26,7 @@
26#define MAX_DCACHE_PAGES 64 /* XXX: Tune for ways */ 26#define MAX_DCACHE_PAGES 64 /* XXX: Tune for ways */
27#define MAX_ICACHE_PAGES 32 27#define MAX_ICACHE_PAGES 32
28 28
29static void __flush_cache_4096(unsigned long addr, unsigned long phys, 29static void __flush_cache_one(unsigned long addr, unsigned long phys,
30 unsigned long exec_offset); 30 unsigned long exec_offset);
31 31
32/* 32/*
@@ -89,8 +89,7 @@ static void __uses_jump_to_uncached sh4_flush_icache_range(void *args)
89 local_irq_restore(flags); 89 local_irq_restore(flags);
90} 90}
91 91
92static inline void flush_cache_4096(unsigned long start, 92static inline void flush_cache_one(unsigned long start, unsigned long phys)
93 unsigned long phys)
94{ 93{
95 unsigned long flags, exec_offset = 0; 94 unsigned long flags, exec_offset = 0;
96 95
@@ -103,8 +102,7 @@ static inline void flush_cache_4096(unsigned long start,
103 exec_offset = 0x20000000; 102 exec_offset = 0x20000000;
104 103
105 local_irq_save(flags); 104 local_irq_save(flags);
106 __flush_cache_4096(start | SH_CACHE_ASSOC, 105 __flush_cache_one(start | SH_CACHE_ASSOC, P1SEGADDR(phys), exec_offset);
107 P1SEGADDR(phys), exec_offset);
108 local_irq_restore(flags); 106 local_irq_restore(flags);
109} 107}
110 108
@@ -129,8 +127,8 @@ static void sh4_flush_dcache_page(void *arg)
129 127
130 /* Loop all the D-cache */ 128 /* Loop all the D-cache */
131 n = boot_cpu_data.dcache.n_aliases; 129 n = boot_cpu_data.dcache.n_aliases;
132 for (i = 0; i < n; i++, addr += 4096) 130 for (i = 0; i < n; i++, addr += PAGE_SIZE)
133 flush_cache_4096(addr, phys); 131 flush_cache_one(addr, phys);
134 } 132 }
135 133
136 wmb(); 134 wmb();
@@ -318,11 +316,11 @@ static void sh4_flush_cache_page(void *args)
318 /* We only need to flush D-cache when we have alias */ 316 /* We only need to flush D-cache when we have alias */
319 if ((address^phys) & alias_mask) { 317 if ((address^phys) & alias_mask) {
320 /* Loop 4K of the D-cache */ 318 /* Loop 4K of the D-cache */
321 flush_cache_4096( 319 flush_cache_one(
322 CACHE_OC_ADDRESS_ARRAY | (address & alias_mask), 320 CACHE_OC_ADDRESS_ARRAY | (address & alias_mask),
323 phys); 321 phys);
324 /* Loop another 4K of the D-cache */ 322 /* Loop another 4K of the D-cache */
325 flush_cache_4096( 323 flush_cache_one(
326 CACHE_OC_ADDRESS_ARRAY | (phys & alias_mask), 324 CACHE_OC_ADDRESS_ARRAY | (phys & alias_mask),
327 phys); 325 phys);
328 } 326 }
@@ -337,7 +335,7 @@ static void sh4_flush_cache_page(void *args)
337 * kernel has never executed the code through its identity 335 * kernel has never executed the code through its identity
338 * translation. 336 * translation.
339 */ 337 */
340 flush_cache_4096( 338 flush_cache_one(
341 CACHE_IC_ADDRESS_ARRAY | (address & alias_mask), 339 CACHE_IC_ADDRESS_ARRAY | (address & alias_mask),
342 phys); 340 phys);
343 } 341 }
@@ -393,7 +391,7 @@ static void sh4_flush_cache_range(void *args)
393} 391}
394 392
395/** 393/**
396 * __flush_cache_4096 394 * __flush_cache_one
397 * 395 *
398 * @addr: address in memory mapped cache array 396 * @addr: address in memory mapped cache array
399 * @phys: P1 address to flush (has to match tags if addr has 'A' bit 397 * @phys: P1 address to flush (has to match tags if addr has 'A' bit
@@ -406,7 +404,7 @@ static void sh4_flush_cache_range(void *args)
406 * operation (purge/write-back) is selected by the lower 2 bits of 404 * operation (purge/write-back) is selected by the lower 2 bits of
407 * 'phys'. 405 * 'phys'.
408 */ 406 */
409static void __flush_cache_4096(unsigned long addr, unsigned long phys, 407static void __flush_cache_one(unsigned long addr, unsigned long phys,
410 unsigned long exec_offset) 408 unsigned long exec_offset)
411{ 409{
412 int way_count; 410 int way_count;