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-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c43
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c45
2 files changed, 84 insertions, 4 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index d84c4575fc0a..e8fd33ff0605 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -10,6 +10,7 @@
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/io.h>
13#include <asm/sci.h> 14#include <asm/sci.h>
14 15
15static struct resource rtc_resources[] = { 16static struct resource rtc_resources[] = {
@@ -239,7 +240,7 @@ static struct intc_vect irl_vectors[] __initdata = {
239}; 240};
240 241
241static struct intc_mask_reg irl3210_mask_registers[] __initdata = { 242static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
242 { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */ 243 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
243 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 244 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
244 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 245 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
245 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 246 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
@@ -247,7 +248,7 @@ static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
247}; 248};
248 249
249static struct intc_mask_reg irl7654_mask_registers[] __initdata = { 250static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
250 { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */ 251 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
251 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 252 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
252 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 253 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
253 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 254 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
@@ -261,8 +262,28 @@ static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
261static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors, 262static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
262 NULL, NULL, irl3210_mask_registers, NULL, NULL); 263 NULL, NULL, irl3210_mask_registers, NULL, NULL);
263 264
265#define INTC_ICR0 0xffd00000
266#define INTC_INTMSK0 0xffd00044
267#define INTC_INTMSK1 0xffd00048
268#define INTC_INTMSK2 0xffd40080
269#define INTC_INTMSKCLR1 0xffd00068
270#define INTC_INTMSKCLR2 0xffd40084
271
264void __init plat_irq_setup(void) 272void __init plat_irq_setup(void)
265{ 273{
274 /* disable IRQ7-0 */
275 ctrl_outl(0xff000000, INTC_INTMSK0);
276
277 /* disable IRL3-0 + IRL7-4 */
278 ctrl_outl(0xc0000000, INTC_INTMSK1);
279 ctrl_outl(0xfffefffe, INTC_INTMSK2);
280
281 /* select IRL mode for IRL3-0 + IRL7-4 */
282 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
283
284 /* disable holding function, ie enable "SH-4 Mode" */
285 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
286
266 register_intc_controller(&intc_desc); 287 register_intc_controller(&intc_desc);
267} 288}
268 289
@@ -270,12 +291,28 @@ void __init plat_irq_setup_pins(int mode)
270{ 291{
271 switch (mode) { 292 switch (mode) {
272 case IRQ_MODE_IRQ: 293 case IRQ_MODE_IRQ:
294 /* select IRQ mode for IRL3-0 + IRL7-4 */
295 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
273 register_intc_controller(&intc_irq_desc); 296 register_intc_controller(&intc_irq_desc);
274 break; 297 break;
275 case IRQ_MODE_IRL7654: 298 case IRQ_MODE_IRL7654:
276 register_intc_controller(&intc_irl7654_desc); 299 /* enable IRL7-4 but don't provide any masking */
300 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
301 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
277 break; 302 break;
278 case IRQ_MODE_IRL3210: 303 case IRQ_MODE_IRL3210:
304 /* enable IRL0-3 but don't provide any masking */
305 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
306 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
307 break;
308 case IRQ_MODE_IRL7654_MASK:
309 /* enable IRL7-4 and mask using cpu intc controller */
310 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
311 register_intc_controller(&intc_irl7654_desc);
312 break;
313 case IRQ_MODE_IRL3210_MASK:
314 /* enable IRL0-3 and mask using cpu intc controller */
315 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
279 register_intc_controller(&intc_irl3210_desc); 316 register_intc_controller(&intc_irl3210_desc);
280 break; 317 break;
281 default: 318 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index a595203f74c6..486dabe4d272 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -10,6 +10,7 @@
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/io.h>
13#include <asm/sci.h> 14#include <asm/sci.h>
14 15
15static struct plat_sci_port sci_platform_data[] = { 16static struct plat_sci_port sci_platform_data[] = {
@@ -282,24 +283,66 @@ static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
282static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567, 283static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
283 NULL, NULL, mask_registers, NULL, NULL); 284 NULL, NULL, mask_registers, NULL, NULL);
284 285
286#define INTC_ICR0 0xffd00000
287#define INTC_INTMSK0 0xffd00044
288#define INTC_INTMSK1 0xffd00048
289#define INTC_INTMSK2 0xffd40080
290#define INTC_INTMSKCLR1 0xffd00068
291#define INTC_INTMSKCLR2 0xffd40084
292
285void __init plat_irq_setup(void) 293void __init plat_irq_setup(void)
286{ 294{
295 /* disable IRQ3-0 + IRQ7-4 */
296 ctrl_outl(0xff000000, INTC_INTMSK0);
297
298 /* disable IRL3-0 + IRL7-4 */
299 ctrl_outl(0xc0000000, INTC_INTMSK1);
300 ctrl_outl(0xfffefffe, INTC_INTMSK2);
301
302 /* select IRL mode for IRL3-0 + IRL7-4 */
303 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
304
305 /* disable holding function, ie enable "SH-4 Mode" */
306 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
307
287 register_intc_controller(&intc_desc); 308 register_intc_controller(&intc_desc);
288} 309}
289 310
290void __init plat_irq_setup_pins(int mode) 311void __init plat_irq_setup_pins(int mode)
291{ 312{
313 ctrl_outl(0xc0000000, INTC_INTMSKCLR1);
314 ctrl_outl(0xfffefffe, INTC_INTMSKCLR2);
315 return;
316
292 switch (mode) { 317 switch (mode) {
293 case IRQ_MODE_IRQ7654: 318 case IRQ_MODE_IRQ7654:
319 /* select IRQ mode for IRL7-4 */
320 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
294 register_intc_controller(&intc_desc_irq4567); 321 register_intc_controller(&intc_desc_irq4567);
295 break; 322 break;
296 case IRQ_MODE_IRQ3210: 323 case IRQ_MODE_IRQ3210:
324 /* select IRQ mode for IRL3-0 */
325 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
297 register_intc_controller(&intc_desc_irq0123); 326 register_intc_controller(&intc_desc_irq0123);
298 break; 327 break;
299 case IRQ_MODE_IRL7654: 328 case IRQ_MODE_IRL7654:
300 register_intc_controller(&intc_desc_irl4567); 329 /* enable IRL7-4 but don't provide any masking */
330 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
331 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
301 break; 332 break;
302 case IRQ_MODE_IRL3210: 333 case IRQ_MODE_IRL3210:
334 /* enable IRL0-3 but don't provide any masking */
335 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
336 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
337 break;
338 case IRQ_MODE_IRL7654_MASK:
339 /* enable IRL7-4 and mask using cpu intc controller */
340 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
341 register_intc_controller(&intc_desc_irl4567);
342 break;
343 case IRQ_MODE_IRL3210_MASK:
344 /* enable IRL0-3 and mask using cpu intc controller */
345 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
303 register_intc_controller(&intc_desc_irl0123); 346 register_intc_controller(&intc_desc_irl0123);
304 break; 347 break;
305 default: 348 default: