6 files changed, 192 insertions, 11 deletions

diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 8d2cd1de5726..5b94cacc7d54 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -167,6 +167,12 @@ config CPU_SUBTYPE_SH7263
         select CPU_SH2A
         select CPU_HAS_FPU
 
+config CPU_SUBTYPE_MXG
+        bool "Support MX-G processor"
+        select CPU_SH2A
+        help
+          Select MX-G if running on an R8A03022BG part.
+
 # SH-3 Processor Support
 
 config CPU_SUBTYPE_SH7705
@@ -560,7 +566,7 @@ config SH_TMU
 config SH_CMT
         def_bool y
         prompt "CMT timer support"
-        depends on CPU_SH2
+        depends on CPU_SH2 && !CPU_SUBTYPE_MXG
         help
           This enables the use of the CMT as the system timer.
 
@@ -578,6 +584,7 @@ config SH_TIMER_IRQ
         default "86" if CPU_SUBTYPE_SH7619
         default "140" if CPU_SUBTYPE_SH7206
         default "142" if CPU_SUBTYPE_SH7203
+        default "238" if CPU_SUBTYPE_MXG
         default "16"
 
 config SH_PCLK_FREQ
@@ -588,7 +595,7 @@ config SH_PCLK_FREQ
         default "33333333" if CPU_SUBTYPE_SH7770 || \
                               CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
                               CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
-                              CPU_SUBTYPE_SH7263
+                              CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG
         default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
         default "66000000" if CPU_SUBTYPE_SH4_202
         default "50000000"
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index 5dcb74b947a9..d9d28f9dd0db 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -29,16 +29,17 @@ config EARLY_SCIF_CONSOLE
 config EARLY_SCIF_CONSOLE_PORT
         hex
         depends on EARLY_SCIF_CONSOLE
-        default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763
-        default "0xffe00000" if CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
-        default "0xffea0000" if CPU_SUBTYPE_SH7785
-        default "0xfffe8000" if CPU_SUBTYPE_SH7203
-        default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
-        default "0xf8420000" if CPU_SUBTYPE_SH7619
         default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
         default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
+        default "0xf8420000" if CPU_SUBTYPE_SH7619
+        default "0xff804000" if CPU_SUBTYPE_MXG
         default "0xffc30000" if CPU_SUBTYPE_SHX3
+        default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
+                                CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
         default "0xffe80000" if CPU_SH4
+        default "0xffea0000" if CPU_SUBTYPE_SH7785
+        default "0xfffe8000" if CPU_SUBTYPE_SH7203
+        default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
         default "0x00000000"
 
 config EARLY_PRINTK
diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile
index b279cdc3a233..7e2b90cfa7bf 100644
--- a/arch/sh/kernel/cpu/sh2a/Makefile
+++ b/arch/sh/kernel/cpu/sh2a/Makefile
@@ -8,6 +8,7 @@ common-y	+= $(addprefix ../sh2/, ex.o entry.o)
 
 obj-$(CONFIG_SH_FPU)    += fpu.o
 
-obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
-obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
-obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7206)        += setup-sh7206.o clock-sh7206.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7203)        += setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7263)        += setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_MXG)           += setup-mxg.o clock-sh7206.o
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index 6910e2664468..6e79132f6f30 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -29,6 +29,9 @@ int __init detect_cpu_and_cache_system(void)
         boot_cpu_data.type                      = CPU_SH7206;
         /* While SH7206 has a DSP.. */
         boot_cpu_data.flags                     |= CPU_HAS_DSP;
+#elif defined(CONFIG_CPU_SUBTYPE_MXG)
+        boot_cpu_data.type                      = CPU_MXG;
+        boot_cpu_data.flags                     |= CPU_HAS_DSP;
 #endif
 
         boot_cpu_data.dcache.ways               = 4;
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
new file mode 100644
index 000000000000..e611d79fac4c
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -0,0 +1,168 @@
+/*
+ * Renesas MX-G (R8A03022BG) Setup
+ *
+ *  Copyright (C) 2008  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/serial_sci.h>
+
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources */
+        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+        IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
+
+        PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
+
+        SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
+
+        SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
+        SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
+
+        MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
+        MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
+        MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
+        MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
+        MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
+        MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
+        MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
+
+        /* interrupt groups */
+        PINT, SCIF0, SCIF1,
+        MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
+};
+
+static struct intc_vect vectors[] __initdata = {
+        INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
+        INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
+        INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
+        INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
+        INTC_IRQ(IRQ8, 72), INTC_IRQ(IRQ9, 73),
+        INTC_IRQ(IRQ10, 74), INTC_IRQ(IRQ11, 75),
+        INTC_IRQ(IRQ12, 76), INTC_IRQ(IRQ13, 77),
+        INTC_IRQ(IRQ14, 78), INTC_IRQ(IRQ15, 79),
+
+        INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
+        INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
+        INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
+        INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
+
+        INTC_IRQ(SINT8, 94), INTC_IRQ(SINT7, 95),
+        INTC_IRQ(SINT6, 96), INTC_IRQ(SINT5, 97),
+        INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
+        INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
+
+        INTC_IRQ(SCIF0_RXI, 220), INTC_IRQ(SCIF0_TXI, 221),
+        INTC_IRQ(SCIF0_BRI, 222), INTC_IRQ(SCIF0_ERI, 223),
+        INTC_IRQ(SCIF1_RXI, 224), INTC_IRQ(SCIF1_TXI, 225),
+        INTC_IRQ(SCIF1_BRI, 226), INTC_IRQ(SCIF1_ERI, 227),
+
+        INTC_IRQ(MTU2_TGI0A, 228), INTC_IRQ(MTU2_TGI0B, 229),
+        INTC_IRQ(MTU2_TGI0C, 230), INTC_IRQ(MTU2_TGI0D, 231),
+        INTC_IRQ(MTU2_TCI0V, 232), INTC_IRQ(MTU2_TGI0E, 233),
+
+        INTC_IRQ(MTU2_TGI0F, 234), INTC_IRQ(MTU2_TGI1A, 235),
+        INTC_IRQ(MTU2_TGI1B, 236), INTC_IRQ(MTU2_TCI1V, 237),
+        INTC_IRQ(MTU2_TCI1U, 238), INTC_IRQ(MTU2_TGI2A, 239),
+
+        INTC_IRQ(MTU2_TGI2B, 240), INTC_IRQ(MTU2_TCI2V, 241),
+        INTC_IRQ(MTU2_TCI2U, 242), INTC_IRQ(MTU2_TGI3A, 243),
+
+        INTC_IRQ(MTU2_TGI3B, 244),
+        INTC_IRQ(MTU2_TGI3C, 245),
+
+        INTC_IRQ(MTU2_TGI3D, 246), INTC_IRQ(MTU2_TCI3V, 247),
+        INTC_IRQ(MTU2_TGI4A, 248), INTC_IRQ(MTU2_TGI4B, 249),
+        INTC_IRQ(MTU2_TGI4C, 250), INTC_IRQ(MTU2_TGI4D, 251),
+
+        INTC_IRQ(MTU2_TCI4V, 252), INTC_IRQ(MTU2_TGI5U, 253),
+        INTC_IRQ(MTU2_TGI5V, 254), INTC_IRQ(MTU2_TGI5W, 255),
+};
+
+static struct intc_group groups[] __initdata = {
+        INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
+                   PINT4, PINT5, PINT6, PINT7),
+        INTC_GROUP(MTU2_GROUP1, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
+                   MTU2_TCI0V, MTU2_TGI0E),
+        INTC_GROUP(MTU2_GROUP2, MTU2_TGI0F, MTU2_TGI1A, MTU2_TGI1B,
+                   MTU2_TCI1V, MTU2_TCI1U, MTU2_TGI2A),
+        INTC_GROUP(MTU2_GROUP3, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
+                   MTU2_TGI3A),
+        INTC_GROUP(MTU2_GROUP4, MTU2_TGI3D, MTU2_TCI3V, MTU2_TGI4A,
+                   MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
+        INTC_GROUP(MTU2_GROUP5, MTU2_TCI4V, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
+        INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
+        INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { 0xfffd9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
+        { 0xfffd941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
+        { 0xfffd941c, 0, 16, 4, /* IPR03 */ { IRQ8, IRQ9, IRQ10, IRQ11 } },
+        { 0xfffd941e, 0, 16, 4, /* IPR04 */ { IRQ12, IRQ13, IRQ14, IRQ15 } },
+        { 0xfffd9420, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
+        { 0xfffd9800, 0, 16, 4, /* IPR06 */ { } },
+        { 0xfffd9802, 0, 16, 4, /* IPR07 */ { } },
+        { 0xfffd9804, 0, 16, 4, /* IPR08 */ { } },
+        { 0xfffd9806, 0, 16, 4, /* IPR09 */ { } },
+        { 0xfffd9808, 0, 16, 4, /* IPR10 */ { } },
+        { 0xfffd980a, 0, 16, 4, /* IPR11 */ { } },
+        { 0xfffd980c, 0, 16, 4, /* IPR12 */ { } },
+        { 0xfffd980e, 0, 16, 4, /* IPR13 */ { } },
+        { 0xfffd9810, 0, 16, 4, /* IPR14 */ { 0, 0, 0, SCIF0 } },
+        { 0xfffd9812, 0, 16, 4, /* IPR15 */
+                { SCIF1, MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3 } },
+        { 0xfffd9814, 0, 16, 4, /* IPR16 */
+                { MTU2_TGI3B, MTU2_TGI3C, MTU2_GROUP4, MTU2_GROUP5 } },
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+        { 0xfffd9408, 0, 16, /* PINTER */
+          { 0, 0, 0, 0, 0, 0, 0, 0,
+            PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
+                         mask_registers, prio_registers, NULL);
+
+static struct plat_sci_port sci_platform_data[] = {
+        {
+                .mapbase        = 0xff804000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 223, 220, 221, 222 },
+        }, {
+                .flags = 0,
+        }
+};
+
+static struct platform_device sci_device = {
+        .name           = "sh-sci",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = sci_platform_data,
+        },
+};
+
+static struct platform_device *mxg_devices[] __initdata = {
+        &sci_device,
+};
+
+static int __init mxg_devices_setup(void)
+{
+        return platform_add_devices(mxg_devices,
+                                    ARRAY_SIZE(mxg_devices));
+}
+__initcall(mxg_devices_setup);
+
+void __init plat_irq_setup(void)
+{
+        register_intc_controller(&intc_desc);
+}
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 23bc707c2b03..0ee776888c65 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -335,6 +335,7 @@ static const char *cpu_name[] = {
         [CPU_SH7343]    = "SH7343",     [CPU_SH7785]    = "SH7785",
         [CPU_SH7722]    = "SH7722",     [CPU_SHX3]      = "SH-X3",
         [CPU_SH5_101]   = "SH5-101",    [CPU_SH5_103]   = "SH5-103",
+        [CPU_MXG]       = "MX-G",
         [CPU_SH7366]    = "SH7366",     [CPU_SH_NONE]   = "Unknown"
 };