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-rw-r--r--arch/sh/include/asm/dma-sh.h13
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c70
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c159
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c113
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c113
5 files changed, 442 insertions, 26 deletions
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
index e934a2e66651..2e3631d6e273 100644
--- a/arch/sh/include/asm/dma-sh.h
+++ b/arch/sh/include/asm/dma-sh.h
@@ -154,10 +154,17 @@ struct sh_dmae_slave_config {
154 char mid_rid; 154 char mid_rid;
155}; 155};
156 156
157struct sh_dmae_channel {
158 unsigned int offset;
159 unsigned int dmars;
160 unsigned int dmars_bit;
161};
162
157struct sh_dmae_pdata { 163struct sh_dmae_pdata {
158 unsigned int mode; 164 struct sh_dmae_slave_config *slave;
159 struct sh_dmae_slave_config *config; 165 int slave_num;
160 int config_num; 166 struct sh_dmae_channel *channel;
167 int channel_num;
161}; 168};
162 169
163struct device; 170struct device;
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 538280a3dc66..aec182bed8a1 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -75,15 +75,79 @@ static struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
75 }, 75 },
76}; 76};
77 77
78static struct sh_dmae_channel sh7722_dmae_channels[] = {
79 {
80 .offset = 0,
81 .dmars = 0,
82 .dmars_bit = 0,
83 }, {
84 .offset = 0x10,
85 .dmars = 0,
86 .dmars_bit = 8,
87 }, {
88 .offset = 0x20,
89 .dmars = 4,
90 .dmars_bit = 0,
91 }, {
92 .offset = 0x30,
93 .dmars = 4,
94 .dmars_bit = 8,
95 }, {
96 .offset = 0x50,
97 .dmars = 8,
98 .dmars_bit = 0,
99 }, {
100 .offset = 0x60,
101 .dmars = 8,
102 .dmars_bit = 8,
103 }
104};
105
78static struct sh_dmae_pdata dma_platform_data = { 106static struct sh_dmae_pdata dma_platform_data = {
79 .mode = 0, 107 .slave = sh7722_dmae_slaves,
80 .config = sh7722_dmae_slaves, 108 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
81 .config_num = ARRAY_SIZE(sh7722_dmae_slaves), 109 .channel = sh7722_dmae_channels,
110 .channel_num = ARRAY_SIZE(sh7722_dmae_channels),
111};
112
113static struct resource sh7722_dmae_resources[] = {
114 [0] = {
115 /* Channel registers and DMAOR */
116 .start = 0xfe008020,
117 .end = 0xfe00808f,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 /* DMARSx */
122 .start = 0xfe009000,
123 .end = 0xfe00900b,
124 .flags = IORESOURCE_MEM,
125 },
126 {
127 /* DMA error IRQ */
128 .start = 78,
129 .end = 78,
130 .flags = IORESOURCE_IRQ,
131 },
132 {
133 /* IRQ for channels 0-3 */
134 .start = 48,
135 .end = 51,
136 .flags = IORESOURCE_IRQ,
137 },
138 {
139 /* IRQ for channels 4-5 */
140 .start = 76,
141 .end = 77,
142 .flags = IORESOURCE_IRQ,
143 },
82}; 144};
83 145
84struct platform_device dma_device = { 146struct platform_device dma_device = {
85 .name = "sh-dma-engine", 147 .name = "sh-dma-engine",
86 .id = -1, 148 .id = -1,
149 .resource = sh7722_dmae_resources,
150 .num_resources = ARRAY_SIZE(sh7722_dmae_resources),
87 .dev = { 151 .dev = {
88 .platform_data = &dma_platform_data, 152 .platform_data = &dma_platform_data,
89 }, 153 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 31e3451f7e3d..aca1fb2c571b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -28,15 +28,157 @@
28#include <cpu/sh7724.h> 28#include <cpu/sh7724.h>
29 29
30/* DMA */ 30/* DMA */
31static struct sh_dmae_pdata dma_platform_data = { 31static struct sh_dmae_channel sh7724_dmae0_channels[] = {
32 .mode = SHDMA_DMAOR1, 32 {
33 .offset = 0,
34 .dmars = 0,
35 .dmars_bit = 0,
36 }, {
37 .offset = 0x10,
38 .dmars = 0,
39 .dmars_bit = 8,
40 }, {
41 .offset = 0x20,
42 .dmars = 4,
43 .dmars_bit = 0,
44 }, {
45 .offset = 0x30,
46 .dmars = 4,
47 .dmars_bit = 8,
48 }, {
49 .offset = 0x50,
50 .dmars = 8,
51 .dmars_bit = 0,
52 }, {
53 .offset = 0x60,
54 .dmars = 8,
55 .dmars_bit = 8,
56 }
57};
58
59static struct sh_dmae_channel sh7724_dmae1_channels[] = {
60 {
61 .offset = 0,
62 .dmars = 0,
63 .dmars_bit = 0,
64 }, {
65 .offset = 0x10,
66 .dmars = 0,
67 .dmars_bit = 8,
68 }, {
69 .offset = 0x20,
70 .dmars = 4,
71 .dmars_bit = 0,
72 }, {
73 .offset = 0x30,
74 .dmars = 4,
75 .dmars_bit = 8,
76 }, {
77 .offset = 0x50,
78 .dmars = 8,
79 .dmars_bit = 0,
80 }, {
81 .offset = 0x60,
82 .dmars = 8,
83 .dmars_bit = 8,
84 }
85};
86
87static struct sh_dmae_pdata dma0_platform_data = {
88 .channel = sh7724_dmae0_channels,
89 .channel_num = ARRAY_SIZE(sh7724_dmae0_channels),
90};
91
92static struct sh_dmae_pdata dma1_platform_data = {
93 .channel = sh7724_dmae1_channels,
94 .channel_num = ARRAY_SIZE(sh7724_dmae1_channels),
95};
96
97/* Resource order important! */
98static struct resource sh7724_dmae0_resources[] = {
99 {
100 /* Channel registers and DMAOR */
101 .start = 0xfe008020,
102 .end = 0xfe00808f,
103 .flags = IORESOURCE_MEM,
104 },
105 {
106 /* DMARSx */
107 .start = 0xfe009000,
108 .end = 0xfe00900b,
109 .flags = IORESOURCE_MEM,
110 },
111 {
112 /* DMA error IRQ */
113 .start = 78,
114 .end = 78,
115 .flags = IORESOURCE_IRQ,
116 },
117 {
118 /* IRQ for channels 0-3 */
119 .start = 48,
120 .end = 51,
121 .flags = IORESOURCE_IRQ,
122 },
123 {
124 /* IRQ for channels 4-5 */
125 .start = 76,
126 .end = 77,
127 .flags = IORESOURCE_IRQ,
128 },
33}; 129};
34 130
35static struct platform_device dma_device = { 131/* Resource order important! */
36 .name = "sh-dma-engine", 132static struct resource sh7724_dmae1_resources[] = {
37 .id = -1, 133 {
38 .dev = { 134 /* Channel registers and DMAOR */
39 .platform_data = &dma_platform_data, 135 .start = 0xfdc08020,
136 .end = 0xfdc0808f,
137 .flags = IORESOURCE_MEM,
138 },
139 {
140 /* DMARSx */
141 .start = 0xfdc09000,
142 .end = 0xfdc0900b,
143 .flags = IORESOURCE_MEM,
144 },
145 {
146 /* DMA error IRQ */
147 .start = 74,
148 .end = 74,
149 .flags = IORESOURCE_IRQ,
150 },
151 {
152 /* IRQ for channels 0-3 */
153 .start = 40,
154 .end = 43,
155 .flags = IORESOURCE_IRQ,
156 },
157 {
158 /* IRQ for channels 4-5 */
159 .start = 72,
160 .end = 73,
161 .flags = IORESOURCE_IRQ,
162 },
163};
164
165static struct platform_device dma0_device = {
166 .name = "sh-dma-engine",
167 .id = 0,
168 .resource = sh7724_dmae0_resources,
169 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
170 .dev = {
171 .platform_data = &dma0_platform_data,
172 },
173};
174
175static struct platform_device dma1_device = {
176 .name = "sh-dma-engine",
177 .id = 1,
178 .resource = sh7724_dmae1_resources,
179 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
180 .dev = {
181 .platform_data = &dma1_platform_data,
40 }, 182 },
41}; 183};
42 184
@@ -663,7 +805,8 @@ static struct platform_device *sh7724_devices[] __initdata = {
663 &tmu3_device, 805 &tmu3_device,
664 &tmu4_device, 806 &tmu4_device,
665 &tmu5_device, 807 &tmu5_device,
666 &dma_device, 808 &dma0_device,
809 &dma1_device,
667 &rtc_device, 810 &rtc_device,
668 &iic0_device, 811 &iic0_device,
669 &iic1_device, 812 &iic1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index f8f21618d785..338dfc2c2bb5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -247,15 +247,115 @@ static struct platform_device rtc_device = {
247 .resource = rtc_resources, 247 .resource = rtc_resources,
248}; 248};
249 249
250static struct sh_dmae_pdata dma_platform_data = { 250/* DMA */
251 .mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1), 251static struct sh_dmae_channel sh7780_dmae0_channels[] = {
252 {
253 .offset = 0,
254 .dmars = 0,
255 .dmars_bit = 0,
256 }, {
257 .offset = 0x10,
258 .dmars = 0,
259 .dmars_bit = 8,
260 }, {
261 .offset = 0x20,
262 .dmars = 4,
263 .dmars_bit = 0,
264 }, {
265 .offset = 0x30,
266 .dmars = 4,
267 .dmars_bit = 8,
268 }, {
269 .offset = 0x50,
270 .dmars = 8,
271 .dmars_bit = 0,
272 }, {
273 .offset = 0x60,
274 .dmars = 8,
275 .dmars_bit = 8,
276 }
277};
278
279static struct sh_dmae_channel sh7780_dmae1_channels[] = {
280 {
281 .offset = 0,
282 }, {
283 .offset = 0x10,
284 }, {
285 .offset = 0x20,
286 }, {
287 .offset = 0x30,
288 }, {
289 .offset = 0x50,
290 }, {
291 .offset = 0x60,
292 }
293};
294
295static struct sh_dmae_pdata dma0_platform_data = {
296 .channel = sh7780_dmae0_channels,
297 .channel_num = ARRAY_SIZE(sh7780_dmae0_channels),
298};
299
300static struct sh_dmae_pdata dma1_platform_data = {
301 .channel = sh7780_dmae1_channels,
302 .channel_num = ARRAY_SIZE(sh7780_dmae1_channels),
303};
304
305static struct resource sh7780_dmae0_resources[] = {
306 [0] = {
307 /* Channel registers and DMAOR */
308 .start = 0xfc808020,
309 .end = 0xfc80808f,
310 .flags = IORESOURCE_MEM,
311 },
312 [1] = {
313 /* DMARSx */
314 .start = 0xfc809000,
315 .end = 0xfc80900b,
316 .flags = IORESOURCE_MEM,
317 },
318 {
319 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
320 .start = 34,
321 .end = 34,
322 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
323 },
324};
325
326static struct resource sh7780_dmae1_resources[] = {
327 [0] = {
328 /* Channel registers and DMAOR */
329 .start = 0xfc818020,
330 .end = 0xfc81808f,
331 .flags = IORESOURCE_MEM,
332 },
333 /* DMAC1 has no DMARS */
334 {
335 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
336 .start = 46,
337 .end = 46,
338 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
339 },
252}; 340};
253 341
254static struct platform_device dma_device = { 342static struct platform_device dma0_device = {
255 .name = "sh-dma-engine", 343 .name = "sh-dma-engine",
256 .id = -1, 344 .id = 0,
345 .resource = sh7780_dmae0_resources,
346 .num_resources = ARRAY_SIZE(sh7780_dmae0_resources),
257 .dev = { 347 .dev = {
258 .platform_data = &dma_platform_data, 348 .platform_data = &dma0_platform_data,
349 },
350};
351
352static struct platform_device dma1_device = {
353 .name = "sh-dma-engine",
354 .id = 1,
355 .resource = sh7780_dmae1_resources,
356 .num_resources = ARRAY_SIZE(sh7780_dmae1_resources),
357 .dev = {
358 .platform_data = &dma1_platform_data,
259 }, 359 },
260}; 360};
261 361
@@ -269,7 +369,8 @@ static struct platform_device *sh7780_devices[] __initdata = {
269 &tmu4_device, 369 &tmu4_device,
270 &tmu5_device, 370 &tmu5_device,
271 &rtc_device, 371 &rtc_device,
272 &dma_device, 372 &dma0_device,
373 &dma1_device,
273}; 374};
274 375
275static int __init sh7780_devices_setup(void) 376static int __init sh7780_devices_setup(void)
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 23448d8c6711..fbb5d1f51f1a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -295,15 +295,115 @@ static struct platform_device tmu5_device = {
295 .num_resources = ARRAY_SIZE(tmu5_resources), 295 .num_resources = ARRAY_SIZE(tmu5_resources),
296}; 296};
297 297
298static struct sh_dmae_pdata dma_platform_data = { 298/* DMA */
299 .mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1), 299static struct sh_dmae_channel sh7785_dmae0_channels[] = {
300 {
301 .offset = 0,
302 .dmars = 0,
303 .dmars_bit = 0,
304 }, {
305 .offset = 0x10,
306 .dmars = 0,
307 .dmars_bit = 8,
308 }, {
309 .offset = 0x20,
310 .dmars = 4,
311 .dmars_bit = 0,
312 }, {
313 .offset = 0x30,
314 .dmars = 4,
315 .dmars_bit = 8,
316 }, {
317 .offset = 0x50,
318 .dmars = 8,
319 .dmars_bit = 0,
320 }, {
321 .offset = 0x60,
322 .dmars = 8,
323 .dmars_bit = 8,
324 }
325};
326
327static struct sh_dmae_channel sh7785_dmae1_channels[] = {
328 {
329 .offset = 0,
330 }, {
331 .offset = 0x10,
332 }, {
333 .offset = 0x20,
334 }, {
335 .offset = 0x30,
336 }, {
337 .offset = 0x50,
338 }, {
339 .offset = 0x60,
340 }
341};
342
343static struct sh_dmae_pdata dma0_platform_data = {
344 .channel = sh7785_dmae0_channels,
345 .channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
346};
347
348static struct sh_dmae_pdata dma1_platform_data = {
349 .channel = sh7785_dmae1_channels,
350 .channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
351};
352
353static struct resource sh7785_dmae0_resources[] = {
354 [0] = {
355 /* Channel registers and DMAOR */
356 .start = 0xfc808020,
357 .end = 0xfc80808f,
358 .flags = IORESOURCE_MEM,
359 },
360 [1] = {
361 /* DMARSx */
362 .start = 0xfc809000,
363 .end = 0xfc80900b,
364 .flags = IORESOURCE_MEM,
365 },
366 {
367 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
368 .start = 33,
369 .end = 33,
370 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
371 },
372};
373
374static struct resource sh7785_dmae1_resources[] = {
375 [0] = {
376 /* Channel registers and DMAOR */
377 .start = 0xfcc08020,
378 .end = 0xfcc0808f,
379 .flags = IORESOURCE_MEM,
380 },
381 /* DMAC1 has no DMARS */
382 {
383 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
384 .start = 52,
385 .end = 52,
386 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
387 },
300}; 388};
301 389
302static struct platform_device dma_device = { 390static struct platform_device dma0_device = {
303 .name = "sh-dma-engine", 391 .name = "sh-dma-engine",
304 .id = -1, 392 .id = 0,
393 .resource = sh7785_dmae0_resources,
394 .num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
305 .dev = { 395 .dev = {
306 .platform_data = &dma_platform_data, 396 .platform_data = &dma0_platform_data,
397 },
398};
399
400static struct platform_device dma1_device = {
401 .name = "sh-dma-engine",
402 .id = 1,
403 .resource = sh7785_dmae1_resources,
404 .num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
405 .dev = {
406 .platform_data = &dma1_platform_data,
307 }, 407 },
308}; 408};
309 409
@@ -320,7 +420,8 @@ static struct platform_device *sh7785_devices[] __initdata = {
320 &tmu3_device, 420 &tmu3_device,
321 &tmu4_device, 421 &tmu4_device,
322 &tmu5_device, 422 &tmu5_device,
323 &dma_device, 423 &dma0_device,
424 &dma1_device,
324}; 425};
325 426
326static int __init sh7785_devices_setup(void) 427static int __init sh7785_devices_setup(void)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 09:22:01 -0500