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-rw-r--r--arch/sh/Kconfig20
-rw-r--r--arch/sh/boards/board-secureedge5410.c2
-rw-r--r--arch/sh/boards/mach-rsk/devices-rsk7203.c37
-rw-r--r--arch/sh/boards/mach-sdk7786/Makefile2
-rw-r--r--arch/sh/boards/mach-sdk7786/nmi.c83
-rw-r--r--arch/sh/boards/mach-sdk7786/setup.c1
-rw-r--r--arch/sh/boards/mach-se/7206/setup.c6
-rw-r--r--arch/sh/boards/mach-se/board-se7619.c6
-rw-r--r--arch/sh/configs/migor_defconfig2
-rw-r--r--arch/sh/drivers/pci/pci.c3
-rw-r--r--arch/sh/include/asm/io.h345
-rw-r--r--arch/sh/include/asm/io_generic.h25
-rw-r--r--arch/sh/include/asm/machvec.h21
-rw-r--r--arch/sh/include/asm/ptrace.h4
-rw-r--r--arch/sh/include/asm/ptrace_32.h2
-rw-r--r--arch/sh/include/asm/ptrace_64.h2
-rw-r--r--arch/sh/include/asm/unaligned-sh4a.h164
-rw-r--r--arch/sh/include/mach-sdk7786/mach/fpga.h8
-rw-r--r--arch/sh/kernel/Makefile6
-rw-r--r--arch/sh/kernel/cpu/Makefile2
-rw-r--r--arch/sh/kernel/cpu/proc.c148
-rw-r--r--arch/sh/kernel/cpu/sh2/clock-sh7619.c22
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7201.c20
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7203.c21
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7206.c20
-rw-r--r--arch/sh/kernel/cpu/sh4/perf_event.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/perf_event.c2
-rw-r--r--arch/sh/kernel/io_generic.c180
-rw-r--r--arch/sh/kernel/iomap.c165
-rw-r--r--arch/sh/kernel/ioport.c43
-rw-r--r--arch/sh/kernel/machvec.c22
-rw-r--r--arch/sh/kernel/perf_event.c2
-rw-r--r--arch/sh/kernel/setup.c144
33 files changed, 795 insertions, 737 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 25cf0b34dffd..e9e71120040c 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -162,7 +162,8 @@ config ARCH_HAS_CPU_IDLE_WAIT
162 def_bool y 162 def_bool y
163 163
164config NO_IOPORT 164config NO_IOPORT
165 bool 165 def_bool !PCI
166 depends on !SH_CAYMAN && !SH_SH4202_MICRODEV
166 167
167config IO_TRAPPED 168config IO_TRAPPED
168 bool 169 bool
@@ -275,6 +276,7 @@ config CPU_SUBTYPE_SH7203
275 select CPU_HAS_FPU 276 select CPU_HAS_FPU
276 select SYS_SUPPORTS_CMT 277 select SYS_SUPPORTS_CMT
277 select SYS_SUPPORTS_MTU2 278 select SYS_SUPPORTS_MTU2
279 select ARCH_WANT_OPTIONAL_GPIOLIB
278 280
279config CPU_SUBTYPE_SH7206 281config CPU_SUBTYPE_SH7206
280 bool "Support SH7206 processor" 282 bool "Support SH7206 processor"
@@ -346,6 +348,7 @@ config CPU_SUBTYPE_SH7720
346 select CPU_SH3 348 select CPU_SH3
347 select CPU_HAS_DSP 349 select CPU_HAS_DSP
348 select SYS_SUPPORTS_CMT 350 select SYS_SUPPORTS_CMT
351 select ARCH_WANT_OPTIONAL_GPIOLIB
349 help 352 help
350 Select SH7720 if you have a SH3-DSP SH7720 CPU. 353 Select SH7720 if you have a SH3-DSP SH7720 CPU.
351 354
@@ -408,6 +411,7 @@ config CPU_SUBTYPE_SH7723
408 select ARCH_SHMOBILE 411 select ARCH_SHMOBILE
409 select ARCH_SPARSEMEM_ENABLE 412 select ARCH_SPARSEMEM_ENABLE
410 select SYS_SUPPORTS_CMT 413 select SYS_SUPPORTS_CMT
414 select ARCH_WANT_OPTIONAL_GPIOLIB
411 help 415 help
412 Select SH7723 if you have an SH-MobileR2 CPU. 416 Select SH7723 if you have an SH-MobileR2 CPU.
413 417
@@ -418,6 +422,7 @@ config CPU_SUBTYPE_SH7724
418 select ARCH_SHMOBILE 422 select ARCH_SHMOBILE
419 select ARCH_SPARSEMEM_ENABLE 423 select ARCH_SPARSEMEM_ENABLE
420 select SYS_SUPPORTS_CMT 424 select SYS_SUPPORTS_CMT
425 select ARCH_WANT_OPTIONAL_GPIOLIB
421 help 426 help
422 Select SH7724 if you have an SH-MobileR2R CPU. 427 Select SH7724 if you have an SH-MobileR2R CPU.
423 428
@@ -425,6 +430,7 @@ config CPU_SUBTYPE_SH7757
425 bool "Support SH7757 processor" 430 bool "Support SH7757 processor"
426 select CPU_SH4A 431 select CPU_SH4A
427 select CPU_SHX2 432 select CPU_SHX2
433 select ARCH_WANT_OPTIONAL_GPIOLIB
428 help 434 help
429 Select SH7757 if you have a SH4A SH7757 CPU. 435 Select SH7757 if you have a SH4A SH7757 CPU.
430 436
@@ -448,6 +454,7 @@ config CPU_SUBTYPE_SH7785
448 select CPU_SHX2 454 select CPU_SHX2
449 select ARCH_SPARSEMEM_ENABLE 455 select ARCH_SPARSEMEM_ENABLE
450 select SYS_SUPPORTS_NUMA 456 select SYS_SUPPORTS_NUMA
457 select ARCH_WANT_OPTIONAL_GPIOLIB
451 458
452config CPU_SUBTYPE_SH7786 459config CPU_SUBTYPE_SH7786
453 bool "Support SH7786 processor" 460 bool "Support SH7786 processor"
@@ -455,6 +462,7 @@ config CPU_SUBTYPE_SH7786
455 select CPU_SHX3 462 select CPU_SHX3
456 select CPU_HAS_PTEAEX 463 select CPU_HAS_PTEAEX
457 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 464 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
465 select ARCH_WANT_OPTIONAL_GPIOLIB
458 466
459config CPU_SUBTYPE_SHX3 467config CPU_SUBTYPE_SHX3
460 bool "Support SH-X3 processor" 468 bool "Support SH-X3 processor"
@@ -479,6 +487,7 @@ config CPU_SUBTYPE_SH7722
479 select ARCH_SPARSEMEM_ENABLE 487 select ARCH_SPARSEMEM_ENABLE
480 select SYS_SUPPORTS_NUMA 488 select SYS_SUPPORTS_NUMA
481 select SYS_SUPPORTS_CMT 489 select SYS_SUPPORTS_CMT
490 select ARCH_WANT_OPTIONAL_GPIOLIB
482 491
483config CPU_SUBTYPE_SH7366 492config CPU_SUBTYPE_SH7366
484 bool "Support SH7366 processor" 493 bool "Support SH7366 processor"
@@ -568,15 +577,6 @@ config SH_CLK_CPG_LEGACY
568 def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ 577 def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
569 !CPU_SHX3 && !CPU_SUBTYPE_SH7757 578 !CPU_SHX3 && !CPU_SUBTYPE_SH7757
570 579
571config SH_CLK_MD
572 int "CPU Mode Pin Setting"
573 depends on CPU_SH2
574 default 6 if CPU_SUBTYPE_SH7206
575 default 5 if CPU_SUBTYPE_SH7619
576 default 0
577 help
578 MD2 - MD0 pin setting.
579
580source "kernel/time/Kconfig" 580source "kernel/time/Kconfig"
581 581
582endmenu 582endmenu
diff --git a/arch/sh/boards/board-secureedge5410.c b/arch/sh/boards/board-secureedge5410.c
index 32f875e8493d..f968f17891a4 100644
--- a/arch/sh/boards/board-secureedge5410.c
+++ b/arch/sh/boards/board-secureedge5410.c
@@ -29,8 +29,6 @@ unsigned short secureedge5410_ioport;
29 */ 29 */
30static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id) 30static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
31{ 31{
32 ctrl_delay(); /* dummy read */
33
34 printk("SnapGear: erase switch interrupt!\n"); 32 printk("SnapGear: erase switch interrupt!\n");
35 33
36 return IRQ_HANDLED; 34 return IRQ_HANDLED;
diff --git a/arch/sh/boards/mach-rsk/devices-rsk7203.c b/arch/sh/boards/mach-rsk/devices-rsk7203.c
index 4fa08ba10253..a8089f79d058 100644
--- a/arch/sh/boards/mach-rsk/devices-rsk7203.c
+++ b/arch/sh/boards/mach-rsk/devices-rsk7203.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Renesas Technology Europe RSK+ 7203 Support. 2 * Renesas Technology Europe RSK+ 7203 Support.
3 * 3 *
4 * Copyright (C) 2008 Paul Mundt 4 * Copyright (C) 2008 - 2010 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -12,7 +12,9 @@
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/smsc911x.h> 14#include <linux/smsc911x.h>
15#include <linux/input.h>
15#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/gpio_keys.h>
16#include <linux/leds.h> 18#include <linux/leds.h>
17#include <asm/machvec.h> 19#include <asm/machvec.h>
18#include <asm/io.h> 20#include <asm/io.h>
@@ -84,9 +86,42 @@ static struct platform_device led_device = {
84 }, 86 },
85}; 87};
86 88
89static struct gpio_keys_button rsk7203_gpio_keys_table[] = {
90 {
91 .code = BTN_0,
92 .gpio = GPIO_PB0,
93 .active_low = 1,
94 .desc = "SW1",
95 }, {
96 .code = BTN_1,
97 .gpio = GPIO_PB1,
98 .active_low = 1,
99 .desc = "SW2",
100 }, {
101 .code = BTN_2,
102 .gpio = GPIO_PB2,
103 .active_low = 1,
104 .desc = "SW3",
105 },
106};
107
108static struct gpio_keys_platform_data rsk7203_gpio_keys_info = {
109 .buttons = rsk7203_gpio_keys_table,
110 .nbuttons = ARRAY_SIZE(rsk7203_gpio_keys_table),
111 .poll_interval = 50, /* default to 50ms */
112};
113
114static struct platform_device keys_device = {
115 .name = "gpio-keys-polled",
116 .dev = {
117 .platform_data = &rsk7203_gpio_keys_info,
118 },
119};
120
87static struct platform_device *rsk7203_devices[] __initdata = { 121static struct platform_device *rsk7203_devices[] __initdata = {
88 &smsc911x_device, 122 &smsc911x_device,
89 &led_device, 123 &led_device,
124 &keys_device,
90}; 125};
91 126
92static int __init rsk7203_devices_setup(void) 127static int __init rsk7203_devices_setup(void)
diff --git a/arch/sh/boards/mach-sdk7786/Makefile b/arch/sh/boards/mach-sdk7786/Makefile
index 23ff7d4ac491..8ae56e9560ac 100644
--- a/arch/sh/boards/mach-sdk7786/Makefile
+++ b/arch/sh/boards/mach-sdk7786/Makefile
@@ -1,4 +1,4 @@
1obj-y := fpga.o irq.o setup.o 1obj-y := fpga.o irq.o nmi.o setup.o
2 2
3obj-$(CONFIG_GENERIC_GPIO) += gpio.o 3obj-$(CONFIG_GENERIC_GPIO) += gpio.o
4obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o 4obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o
diff --git a/arch/sh/boards/mach-sdk7786/nmi.c b/arch/sh/boards/mach-sdk7786/nmi.c
new file mode 100644
index 000000000000..edcfa1f568ba
--- /dev/null
+++ b/arch/sh/boards/mach-sdk7786/nmi.c
@@ -0,0 +1,83 @@
1/*
2 * SDK7786 FPGA NMI Support.
3 *
4 * Copyright (C) 2010 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <mach/fpga.h>
14
15enum {
16 NMI_MODE_MANUAL,
17 NMI_MODE_AUX,
18 NMI_MODE_MASKED,
19 NMI_MODE_ANY,
20 NMI_MODE_UNKNOWN,
21};
22
23/*
24 * Default to the manual NMI switch.
25 */
26static unsigned int __initdata nmi_mode = NMI_MODE_ANY;
27
28static int __init nmi_mode_setup(char *str)
29{
30 if (!str)
31 return 0;
32
33 if (strcmp(str, "manual") == 0)
34 nmi_mode = NMI_MODE_MANUAL;
35 else if (strcmp(str, "aux") == 0)
36 nmi_mode = NMI_MODE_AUX;
37 else if (strcmp(str, "masked") == 0)
38 nmi_mode = NMI_MODE_MASKED;
39 else if (strcmp(str, "any") == 0)
40 nmi_mode = NMI_MODE_ANY;
41 else {
42 nmi_mode = NMI_MODE_UNKNOWN;
43 pr_warning("Unknown NMI mode %s\n", str);
44 }
45
46 printk("Set NMI mode to %d\n", nmi_mode);
47 return 0;
48}
49early_param("nmi_mode", nmi_mode_setup);
50
51void __init sdk7786_nmi_init(void)
52{
53 unsigned int source, mask, tmp;
54
55 switch (nmi_mode) {
56 case NMI_MODE_MANUAL:
57 source = NMISR_MAN_NMI;
58 mask = NMIMR_MAN_NMIM;
59 break;
60 case NMI_MODE_AUX:
61 source = NMISR_AUX_NMI;
62 mask = NMIMR_AUX_NMIM;
63 break;
64 case NMI_MODE_ANY:
65 source = NMISR_MAN_NMI | NMISR_AUX_NMI;
66 mask = NMIMR_MAN_NMIM | NMIMR_AUX_NMIM;
67 break;
68 case NMI_MODE_MASKED:
69 case NMI_MODE_UNKNOWN:
70 default:
71 source = mask = 0;
72 break;
73 }
74
75 /* Set the NMI source */
76 tmp = fpga_read_reg(NMISR);
77 tmp &= ~NMISR_MASK;
78 tmp |= source;
79 fpga_write_reg(tmp, NMISR);
80
81 /* And the IRQ masking */
82 fpga_write_reg(NMIMR_MASK ^ mask, NMIMR);
83}
diff --git a/arch/sh/boards/mach-sdk7786/setup.c b/arch/sh/boards/mach-sdk7786/setup.c
index 7e0c4e3878e0..75e4ddbbec3e 100644
--- a/arch/sh/boards/mach-sdk7786/setup.c
+++ b/arch/sh/boards/mach-sdk7786/setup.c
@@ -237,6 +237,7 @@ static void __init sdk7786_setup(char **cmdline_p)
237 pr_info("Renesas Technology Europe SDK7786 support:\n"); 237 pr_info("Renesas Technology Europe SDK7786 support:\n");
238 238
239 sdk7786_fpga_init(); 239 sdk7786_fpga_init();
240 sdk7786_nmi_init();
240 241
241 pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf); 242 pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
242 243
diff --git a/arch/sh/boards/mach-se/7206/setup.c b/arch/sh/boards/mach-se/7206/setup.c
index 7f4871c71a01..33039e0dc568 100644
--- a/arch/sh/boards/mach-se/7206/setup.c
+++ b/arch/sh/boards/mach-se/7206/setup.c
@@ -79,6 +79,11 @@ static int __init se7206_devices_setup(void)
79} 79}
80__initcall(se7206_devices_setup); 80__initcall(se7206_devices_setup);
81 81
82static int se7206_mode_pins(void)
83{
84 return MODE_PIN1 | MODE_PIN2;
85}
86
82/* 87/*
83 * The Machine Vector 88 * The Machine Vector
84 */ 89 */
@@ -87,4 +92,5 @@ static struct sh_machine_vector mv_se __initmv = {
87 .mv_name = "SolutionEngine", 92 .mv_name = "SolutionEngine",
88 .mv_nr_irqs = 256, 93 .mv_nr_irqs = 256,
89 .mv_init_irq = init_se7206_IRQ, 94 .mv_init_irq = init_se7206_IRQ,
95 .mv_mode_pins = se7206_mode_pins,
90}; 96};
diff --git a/arch/sh/boards/mach-se/board-se7619.c b/arch/sh/boards/mach-se/board-se7619.c
index 1d0ef7faa10d..82b6d4a5dc02 100644
--- a/arch/sh/boards/mach-se/board-se7619.c
+++ b/arch/sh/boards/mach-se/board-se7619.c
@@ -11,6 +11,11 @@
11#include <asm/io.h> 11#include <asm/io.h>
12#include <asm/machvec.h> 12#include <asm/machvec.h>
13 13
14static int se7619_mode_pins(void)
15{
16 return MODE_PIN2 | MODE_PIN0;
17}
18
14/* 19/*
15 * The Machine Vector 20 * The Machine Vector
16 */ 21 */
@@ -18,4 +23,5 @@
18static struct sh_machine_vector mv_se __initmv = { 23static struct sh_machine_vector mv_se __initmv = {
19 .mv_name = "SolutionEngine", 24 .mv_name = "SolutionEngine",
20 .mv_nr_irqs = 108, 25 .mv_nr_irqs = 108,
26 .mv_mode_pins = se7619_mode_pins,
21}; 27};
diff --git a/arch/sh/configs/migor_defconfig b/arch/sh/configs/migor_defconfig
index 9ad904a110de..cc61eda44922 100644
--- a/arch/sh/configs/migor_defconfig
+++ b/arch/sh/configs/migor_defconfig
@@ -54,6 +54,8 @@ CONFIG_INPUT_EVDEV=y
54# CONFIG_KEYBOARD_ATKBD is not set 54# CONFIG_KEYBOARD_ATKBD is not set
55CONFIG_KEYBOARD_SH_KEYSC=y 55CONFIG_KEYBOARD_SH_KEYSC=y
56# CONFIG_INPUT_MOUSE is not set 56# CONFIG_INPUT_MOUSE is not set
57CONFIG_INPUT_TOUCHSCREEN=y
58CONFIG_TOUCHSCREEN_MIGOR=y
57# CONFIG_SERIO is not set 59# CONFIG_SERIO is not set
58CONFIG_VT_HW_CONSOLE_BINDING=y 60CONFIG_VT_HW_CONSOLE_BINDING=y
59CONFIG_SERIAL_SH_SCI=y 61CONFIG_SERIAL_SH_SCI=y
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 60ee09a4e121..a09c77dd09db 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -382,14 +382,13 @@ static void __iomem *ioport_map_pci(struct pci_dev *dev,
382 struct pci_channel *chan = dev->sysdata; 382 struct pci_channel *chan = dev->sysdata;
383 383
384 if (unlikely(!chan->io_map_base)) { 384 if (unlikely(!chan->io_map_base)) {
385 chan->io_map_base = generic_io_base; 385 chan->io_map_base = sh_io_port_base;
386 386
387 if (pci_domains_supported) 387 if (pci_domains_supported)
388 panic("To avoid data corruption io_map_base MUST be " 388 panic("To avoid data corruption io_map_base MUST be "
389 "set with multiple PCI domains."); 389 "set with multiple PCI domains.");
390 } 390 }
391 391
392
393 return (void __iomem *)(chan->io_map_base + port); 392 return (void __iomem *)(chan->io_map_base + port);
394} 393}
395 394
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index b237d525d592..89ab2c57a4c2 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -1,5 +1,6 @@
1#ifndef __ASM_SH_IO_H 1#ifndef __ASM_SH_IO_H
2#define __ASM_SH_IO_H 2#define __ASM_SH_IO_H
3
3/* 4/*
4 * Convention: 5 * Convention:
5 * read{b,w,l,q}/write{b,w,l,q} are for PCI, 6 * read{b,w,l,q}/write{b,w,l,q} are for PCI,
@@ -15,12 +16,6 @@
15 * SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice 16 * SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice
16 * these have the same semantics as the __raw variants, and as such, all 17 * these have the same semantics as the __raw variants, and as such, all
17 * new code should be using the __raw versions. 18 * new code should be using the __raw versions.
18 *
19 * All ISA I/O routines are wrapped through the machine vector. If a
20 * board does not provide overrides, a generic set that are copied in
21 * from the default machine vector are used instead. These are largely
22 * for old compat code for I/O offseting to SuperIOs, all of which are
23 * better handled through the machvec ioport mapping routines these days.
24 */ 19 */
25#include <linux/errno.h> 20#include <linux/errno.h>
26#include <asm/cache.h> 21#include <asm/cache.h>
@@ -31,39 +26,10 @@
31#include <asm-generic/iomap.h> 26#include <asm-generic/iomap.h>
32 27
33#ifdef __KERNEL__ 28#ifdef __KERNEL__
34/* 29#define __IO_PREFIX generic
35 * Depending on which platform we are running on, we need different
36 * I/O functions.
37 */
38#define __IO_PREFIX generic
39#include <asm/io_generic.h> 30#include <asm/io_generic.h>
40#include <asm/io_trapped.h> 31#include <asm/io_trapped.h>
41 32
42#ifdef CONFIG_HAS_IOPORT
43
44#define inb(p) sh_mv.mv_inb((p))
45#define inw(p) sh_mv.mv_inw((p))
46#define inl(p) sh_mv.mv_inl((p))
47#define outb(x,p) sh_mv.mv_outb((x),(p))
48#define outw(x,p) sh_mv.mv_outw((x),(p))
49#define outl(x,p) sh_mv.mv_outl((x),(p))
50
51#define inb_p(p) sh_mv.mv_inb_p((p))
52#define inw_p(p) sh_mv.mv_inw_p((p))
53#define inl_p(p) sh_mv.mv_inl_p((p))
54#define outb_p(x,p) sh_mv.mv_outb_p((x),(p))
55#define outw_p(x,p) sh_mv.mv_outw_p((x),(p))
56#define outl_p(x,p) sh_mv.mv_outl_p((x),(p))
57
58#define insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
59#define insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
60#define insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
61#define outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
62#define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
63#define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
64
65#endif
66
67#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v)) 33#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
68#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v)) 34#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
69#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) 35#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
@@ -74,68 +40,39 @@
74#define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a)) 40#define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
75#define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a)) 41#define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
76 42
77#define readb(a) ({ u8 r_ = __raw_readb(a); mb(); r_; }) 43#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
78#define readw(a) ({ u16 r_ = __raw_readw(a); mb(); r_; }) 44#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \
79#define readl(a) ({ u32 r_ = __raw_readl(a); mb(); r_; }) 45 __raw_readw(c)); __v; })
80#define readq(a) ({ u64 r_ = __raw_readq(a); mb(); r_; }) 46#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32) \
81 47 __raw_readl(c)); __v; })
82#define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); }) 48#define readq_relaxed(c) ({ u64 __v = le64_to_cpu((__force __le64) \
83#define writew(v,a) ({ __raw_writew((v),(a)); mb(); }) 49 __raw_readq(c)); __v; })
84#define writel(v,a) ({ __raw_writel((v),(a)); mb(); }) 50
85#define writeq(v,a) ({ __raw_writeq((v),(a)); mb(); }) 51#define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
86 52#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
87/* 53 cpu_to_le16(v),c))
88 * Legacy SuperH on-chip I/O functions 54#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
89 * 55 cpu_to_le32(v),c))
90 * These are all deprecated, all new (and especially cross-platform) code 56#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64) \
91 * should be using the __raw_xxx() routines directly. 57 cpu_to_le64(v),c))
92 */ 58
93static inline u8 __deprecated ctrl_inb(unsigned long addr) 59#define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
94{ 60#define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
95 return __raw_readb(addr); 61#define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
96} 62#define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
97 63
98static inline u16 __deprecated ctrl_inw(unsigned long addr) 64#define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); })
99{ 65#define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); })
100 return __raw_readw(addr); 66#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
101} 67#define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
102 68
103static inline u32 __deprecated ctrl_inl(unsigned long addr) 69#define readsb(p,d,l) __raw_readsb(p,d,l)
104{ 70#define readsw(p,d,l) __raw_readsw(p,d,l)
105 return __raw_readl(addr); 71#define readsl(p,d,l) __raw_readsl(p,d,l)
106} 72
107 73#define writesb(p,d,l) __raw_writesb(p,d,l)
108static inline u64 __deprecated ctrl_inq(unsigned long addr) 74#define writesw(p,d,l) __raw_writesw(p,d,l)
109{ 75#define writesl(p,d,l) __raw_writesl(p,d,l)
110 return __raw_readq(addr);
111}
112
113static inline void __deprecated ctrl_outb(u8 v, unsigned long addr)
114{
115 __raw_writeb(v, addr);
116}
117
118static inline void __deprecated ctrl_outw(u16 v, unsigned long addr)
119{
120 __raw_writew(v, addr);
121}
122
123static inline void __deprecated ctrl_outl(u32 v, unsigned long addr)
124{
125 __raw_writel(v, addr);
126}
127
128static inline void __deprecated ctrl_outq(u64 v, unsigned long addr)
129{
130 __raw_writeq(v, addr);
131}
132
133extern unsigned long generic_io_base;
134
135static inline void ctrl_delay(void)
136{
137 __raw_readw(generic_io_base);
138}
139 76
140#define __BUILD_UNCACHED_IO(bwlq, type) \ 77#define __BUILD_UNCACHED_IO(bwlq, type) \
141static inline type read##bwlq##_uncached(unsigned long addr) \ 78static inline type read##bwlq##_uncached(unsigned long addr) \
@@ -159,10 +96,11 @@ __BUILD_UNCACHED_IO(w, u16)
159__BUILD_UNCACHED_IO(l, u32) 96__BUILD_UNCACHED_IO(l, u32)
160__BUILD_UNCACHED_IO(q, u64) 97__BUILD_UNCACHED_IO(q, u64)
161 98
162#define __BUILD_MEMORY_STRING(bwlq, type) \ 99#define __BUILD_MEMORY_STRING(pfx, bwlq, type) \
163 \ 100 \
164static inline void __raw_writes##bwlq(volatile void __iomem *mem, \ 101static inline void \
165 const void *addr, unsigned int count) \ 102pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \
103 unsigned int count) \
166{ \ 104{ \
167 const volatile type *__addr = addr; \ 105 const volatile type *__addr = addr; \
168 \ 106 \
@@ -172,8 +110,8 @@ static inline void __raw_writes##bwlq(volatile void __iomem *mem, \
172 } \ 110 } \
173} \ 111} \
174 \ 112 \
175static inline void __raw_reads##bwlq(volatile void __iomem *mem, \ 113static inline void pfx##reads##bwlq(volatile void __iomem *mem, \
176 void *addr, unsigned int count) \ 114 void *addr, unsigned int count) \
177{ \ 115{ \
178 volatile type *__addr = addr; \ 116 volatile type *__addr = addr; \
179 \ 117 \
@@ -183,85 +121,166 @@ static inline void __raw_reads##bwlq(volatile void __iomem *mem, \
183 } \ 121 } \
184} 122}
185 123
186__BUILD_MEMORY_STRING(b, u8) 124__BUILD_MEMORY_STRING(__raw_, b, u8)
187__BUILD_MEMORY_STRING(w, u16) 125__BUILD_MEMORY_STRING(__raw_, w, u16)
188 126
189#ifdef CONFIG_SUPERH32 127#ifdef CONFIG_SUPERH32
190void __raw_writesl(void __iomem *addr, const void *data, int longlen); 128void __raw_writesl(void __iomem *addr, const void *data, int longlen);
191void __raw_readsl(const void __iomem *addr, void *data, int longlen); 129void __raw_readsl(const void __iomem *addr, void *data, int longlen);
192#else 130#else
193__BUILD_MEMORY_STRING(l, u32) 131__BUILD_MEMORY_STRING(__raw_, l, u32)
194#endif 132#endif
195 133
196__BUILD_MEMORY_STRING(q, u64) 134__BUILD_MEMORY_STRING(__raw_, q, u64)
197 135
198#define writesb __raw_writesb 136#ifdef CONFIG_HAS_IOPORT
199#define writesw __raw_writesw 137
200#define writesl __raw_writesl 138/*
201 139 * Slowdown I/O port space accesses for antique hardware.
202#define readsb __raw_readsb 140 */
203#define readsw __raw_readsw 141#undef CONF_SLOWDOWN_IO
204#define readsl __raw_readsl 142
205 143/*
206#define readb_relaxed(a) readb(a) 144 * On SuperH I/O ports are memory mapped, so we access them using normal
207#define readw_relaxed(a) readw(a) 145 * load/store instructions. sh_io_port_base is the virtual address to
208#define readl_relaxed(a) readl(a) 146 * which all ports are being mapped.
209#define readq_relaxed(a) readq(a) 147 */
210 148extern const unsigned long sh_io_port_base;
211#ifndef CONFIG_GENERIC_IOMAP 149
212/* Simple MMIO */ 150static inline void __set_io_port_base(unsigned long pbase)
213#define ioread8(a) __raw_readb(a) 151{
214#define ioread16(a) __raw_readw(a) 152 *(unsigned long *)&sh_io_port_base = pbase;
215#define ioread16be(a) be16_to_cpu(__raw_readw((a))) 153 barrier();
216#define ioread32(a) __raw_readl(a) 154}
217#define ioread32be(a) be32_to_cpu(__raw_readl((a))) 155
218 156#ifdef CONFIG_GENERIC_IOMAP
219#define iowrite8(v,a) __raw_writeb((v),(a)) 157#define __ioport_map ioport_map
220#define iowrite16(v,a) __raw_writew((v),(a)) 158#else
221#define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a)) 159extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
222#define iowrite32(v,a) __raw_writel((v),(a))
223#define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
224
225#define ioread8_rep(a, d, c) __raw_readsb((a), (d), (c))
226#define ioread16_rep(a, d, c) __raw_readsw((a), (d), (c))
227#define ioread32_rep(a, d, c) __raw_readsl((a), (d), (c))
228
229#define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c))
230#define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c))
231#define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c))
232#endif 160#endif
233 161
234#define mmio_insb(p,d,c) __raw_readsb(p,d,c) 162#ifdef CONF_SLOWDOWN_IO
235#define mmio_insw(p,d,c) __raw_readsw(p,d,c) 163#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
236#define mmio_insl(p,d,c) __raw_readsl(p,d,c) 164#else
165#define SLOW_DOWN_IO
166#endif
237 167
238#define mmio_outsb(p,s,c) __raw_writesb(p,s,c) 168#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
239#define mmio_outsw(p,s,c) __raw_writesw(p,s,c) 169 \
240#define mmio_outsl(p,s,c) __raw_writesl(p,s,c) 170static inline void pfx##out##bwlq##p(type val, unsigned long port) \
171{ \
172 volatile type *__addr; \
173 \
174 __addr = __ioport_map(port, sizeof(type)); \
175 *__addr = val; \
176 slow; \
177} \
178 \
179static inline type pfx##in##bwlq##p(unsigned long port) \
180{ \
181 volatile type *__addr; \
182 type __val; \
183 \
184 __addr = __ioport_map(port, sizeof(type)); \
185 __val = *__addr; \
186 slow; \
187 \
188 return __val; \
189}
241 190
242/* synco on SH-4A, otherwise a nop */ 191#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
243#define mmiowb() wmb() 192 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
193 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
244 194
245#define IO_SPACE_LIMIT 0xffffffff 195#define BUILDIO_IOPORT(bwlq, type) \
196 __BUILD_IOPORT_PFX(, bwlq, type)
246 197
247#ifdef CONFIG_HAS_IOPORT 198BUILDIO_IOPORT(b, u8)
199BUILDIO_IOPORT(w, u16)
200BUILDIO_IOPORT(l, u32)
201BUILDIO_IOPORT(q, u64)
202
203#define __BUILD_IOPORT_STRING(bwlq, type) \
204 \
205static inline void outs##bwlq(unsigned long port, const void *addr, \
206 unsigned int count) \
207{ \
208 const volatile type *__addr = addr; \
209 \
210 while (count--) { \
211 out##bwlq(*__addr, port); \
212 __addr++; \
213 } \
214} \
215 \
216static inline void ins##bwlq(unsigned long port, void *addr, \
217 unsigned int count) \
218{ \
219 volatile type *__addr = addr; \
220 \
221 while (count--) { \
222 *__addr = in##bwlq(port); \
223 __addr++; \
224 } \
225}
226
227__BUILD_IOPORT_STRING(b, u8)
228__BUILD_IOPORT_STRING(w, u16)
229__BUILD_IOPORT_STRING(l, u32)
230__BUILD_IOPORT_STRING(q, u64)
231
232#endif
248 233
249/* 234/*
250 * This function provides a method for the generic case where a 235 * Legacy SuperH on-chip I/O functions
251 * board-specific ioport_map simply needs to return the port + some
252 * arbitrary port base.
253 * 236 *
254 * We use this at board setup time to implicitly set the port base, and 237 * These are all deprecated, all new (and especially cross-platform) code
255 * as a result, we can use the generic ioport_map. 238 * should be using the __raw_xxx() routines directly.
256 */ 239 */
257static inline void __set_io_port_base(unsigned long pbase) 240static inline u8 __deprecated ctrl_inb(unsigned long addr)
258{ 241{
259 generic_io_base = pbase; 242 return __raw_readb(addr);
260} 243}
261 244
262#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n)) 245static inline u16 __deprecated ctrl_inw(unsigned long addr)
246{
247 return __raw_readw(addr);
248}
263 249
264#endif 250static inline u32 __deprecated ctrl_inl(unsigned long addr)
251{
252 return __raw_readl(addr);
253}
254
255static inline u64 __deprecated ctrl_inq(unsigned long addr)
256{
257 return __raw_readq(addr);
258}
259
260static inline void __deprecated ctrl_outb(u8 v, unsigned long addr)
261{
262 __raw_writeb(v, addr);
263}
264
265static inline void __deprecated ctrl_outw(u16 v, unsigned long addr)
266{
267 __raw_writew(v, addr);
268}
269
270static inline void __deprecated ctrl_outl(u32 v, unsigned long addr)
271{
272 __raw_writel(v, addr);
273}
274
275static inline void __deprecated ctrl_outq(u64 v, unsigned long addr)
276{
277 __raw_writeq(v, addr);
278}
279
280#define IO_SPACE_LIMIT 0xffffffff
281
282/* synco on SH-4A, otherwise a nop */
283#define mmiowb() wmb()
265 284
266/* We really want to try and get these to memcpy etc */ 285/* We really want to try and get these to memcpy etc */
267void memcpy_fromio(void *, const volatile void __iomem *, unsigned long); 286void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
@@ -395,10 +414,6 @@ static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
395#define ioremap_nocache ioremap 414#define ioremap_nocache ioremap
396#define iounmap __iounmap 415#define iounmap __iounmap
397 416
398#define maybebadio(port) \
399 printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
400 __func__, __LINE__, (port), (u32)__builtin_return_address(0))
401
402/* 417/*
403 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 418 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
404 * access 419 * access
diff --git a/arch/sh/include/asm/io_generic.h b/arch/sh/include/asm/io_generic.h
index 491df93cbf8e..b5f6956f19c8 100644
--- a/arch/sh/include/asm/io_generic.h
+++ b/arch/sh/include/asm/io_generic.h
@@ -11,31 +11,6 @@
11#error "Don't include this header without a valid system prefix" 11#error "Don't include this header without a valid system prefix"
12#endif 12#endif
13 13
14u8 IO_CONCAT(__IO_PREFIX,inb)(unsigned long);
15u16 IO_CONCAT(__IO_PREFIX,inw)(unsigned long);
16u32 IO_CONCAT(__IO_PREFIX,inl)(unsigned long);
17
18void IO_CONCAT(__IO_PREFIX,outb)(u8, unsigned long);
19void IO_CONCAT(__IO_PREFIX,outw)(u16, unsigned long);
20void IO_CONCAT(__IO_PREFIX,outl)(u32, unsigned long);
21
22u8 IO_CONCAT(__IO_PREFIX,inb_p)(unsigned long);
23u16 IO_CONCAT(__IO_PREFIX,inw_p)(unsigned long);
24u32 IO_CONCAT(__IO_PREFIX,inl_p)(unsigned long);
25void IO_CONCAT(__IO_PREFIX,outb_p)(u8, unsigned long);
26void IO_CONCAT(__IO_PREFIX,outw_p)(u16, unsigned long);
27void IO_CONCAT(__IO_PREFIX,outl_p)(u32, unsigned long);
28
29void IO_CONCAT(__IO_PREFIX,insb)(unsigned long, void *dst, unsigned long count);
30void IO_CONCAT(__IO_PREFIX,insw)(unsigned long, void *dst, unsigned long count);
31void IO_CONCAT(__IO_PREFIX,insl)(unsigned long, void *dst, unsigned long count);
32void IO_CONCAT(__IO_PREFIX,outsb)(unsigned long, const void *src, unsigned long count);
33void IO_CONCAT(__IO_PREFIX,outsw)(unsigned long, const void *src, unsigned long count);
34void IO_CONCAT(__IO_PREFIX,outsl)(unsigned long, const void *src, unsigned long count);
35
36void *IO_CONCAT(__IO_PREFIX,ioremap)(unsigned long offset, unsigned long size);
37void IO_CONCAT(__IO_PREFIX,iounmap)(void *addr);
38
39void __iomem *IO_CONCAT(__IO_PREFIX,ioport_map)(unsigned long addr, unsigned int size); 14void __iomem *IO_CONCAT(__IO_PREFIX,ioport_map)(unsigned long addr, unsigned int size);
40void IO_CONCAT(__IO_PREFIX,ioport_unmap)(void __iomem *addr); 15void IO_CONCAT(__IO_PREFIX,ioport_unmap)(void __iomem *addr);
41void IO_CONCAT(__IO_PREFIX,mem_init)(void); 16void IO_CONCAT(__IO_PREFIX,mem_init)(void);
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index a0b0cf79cf8a..dd5d6e5bf204 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -23,27 +23,6 @@ struct sh_machine_vector {
23 void (*mv_init_irq)(void); 23 void (*mv_init_irq)(void);
24 24
25#ifdef CONFIG_HAS_IOPORT 25#ifdef CONFIG_HAS_IOPORT
26 u8 (*mv_inb)(unsigned long);
27 u16 (*mv_inw)(unsigned long);
28 u32 (*mv_inl)(unsigned long);
29 void (*mv_outb)(u8, unsigned long);
30 void (*mv_outw)(u16, unsigned long);
31 void (*mv_outl)(u32, unsigned long);
32
33 u8 (*mv_inb_p)(unsigned long);
34 u16 (*mv_inw_p)(unsigned long);
35 u32 (*mv_inl_p)(unsigned long);
36 void (*mv_outb_p)(u8, unsigned long);
37 void (*mv_outw_p)(u16, unsigned long);
38 void (*mv_outl_p)(u32, unsigned long);
39
40 void (*mv_insb)(unsigned long, void *dst, unsigned long count);
41 void (*mv_insw)(unsigned long, void *dst, unsigned long count);
42 void (*mv_insl)(unsigned long, void *dst, unsigned long count);
43 void (*mv_outsb)(unsigned long, const void *src, unsigned long count);
44 void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
45 void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
46
47 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size); 26 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
48 void (*mv_ioport_unmap)(void __iomem *); 27 void (*mv_ioport_unmap)(void __iomem *);
49#endif 28#endif
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index f6edc10aa0d3..de167d3a1a80 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -40,8 +40,8 @@
40#include <asm/system.h> 40#include <asm/system.h>
41 41
42#define user_mode(regs) (((regs)->sr & 0x40000000)==0) 42#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
43#define user_stack_pointer(regs) ((unsigned long)(regs)->regs[15]) 43#define user_stack_pointer(_regs) ((unsigned long)(_regs)->regs[15])
44#define kernel_stack_pointer(regs) ((unsigned long)(regs)->regs[15]) 44#define kernel_stack_pointer(_regs) ((unsigned long)(_regs)->regs[15])
45#define instruction_pointer(regs) ((unsigned long)(regs)->pc) 45#define instruction_pointer(regs) ((unsigned long)(regs)->pc)
46 46
47extern void show_regs(struct pt_regs *); 47extern void show_regs(struct pt_regs *);
diff --git a/arch/sh/include/asm/ptrace_32.h b/arch/sh/include/asm/ptrace_32.h
index 35d9e257558c..6c2239cca1a2 100644
--- a/arch/sh/include/asm/ptrace_32.h
+++ b/arch/sh/include/asm/ptrace_32.h
@@ -76,7 +76,7 @@ struct pt_dspregs {
76#ifdef __KERNEL__ 76#ifdef __KERNEL__
77 77
78#define MAX_REG_OFFSET offsetof(struct pt_regs, tra) 78#define MAX_REG_OFFSET offsetof(struct pt_regs, tra)
79#define regs_return_value(regs) ((regs)->regs[0]) 79#define regs_return_value(_regs) ((_regs)->regs[0])
80 80
81#endif /* __KERNEL__ */ 81#endif /* __KERNEL__ */
82 82
diff --git a/arch/sh/include/asm/ptrace_64.h b/arch/sh/include/asm/ptrace_64.h
index d43c1cb0bbe7..bf9be7764d69 100644
--- a/arch/sh/include/asm/ptrace_64.h
+++ b/arch/sh/include/asm/ptrace_64.h
@@ -13,7 +13,7 @@ struct pt_regs {
13#ifdef __KERNEL__ 13#ifdef __KERNEL__
14 14
15#define MAX_REG_OFFSET offsetof(struct pt_regs, tregs[7]) 15#define MAX_REG_OFFSET offsetof(struct pt_regs, tregs[7])
16#define regs_return_value(regs) ((regs)->regs[3]) 16#define regs_return_value(_regs) ((_regs)->regs[3])
17 17
18#endif /* __KERNEL__ */ 18#endif /* __KERNEL__ */
19 19
diff --git a/arch/sh/include/asm/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h
index 9f4dd252c981..c48a9c3420da 100644
--- a/arch/sh/include/asm/unaligned-sh4a.h
+++ b/arch/sh/include/asm/unaligned-sh4a.h
@@ -18,10 +18,20 @@
18 * of spill registers and blowing up when building at low optimization 18 * of spill registers and blowing up when building at low optimization
19 * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777. 19 * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777.
20 */ 20 */
21#include <linux/unaligned/packed_struct.h>
21#include <linux/types.h> 22#include <linux/types.h>
22#include <asm/byteorder.h> 23#include <asm/byteorder.h>
23 24
24static __always_inline u32 __get_unaligned_cpu32(const u8 *p) 25static inline u16 sh4a_get_unaligned_cpu16(const u8 *p)
26{
27#ifdef __LITTLE_ENDIAN
28 return p[0] | p[1] << 8;
29#else
30 return p[0] << 8 | p[1];
31#endif
32}
33
34static __always_inline u32 sh4a_get_unaligned_cpu32(const u8 *p)
25{ 35{
26 unsigned long unaligned; 36 unsigned long unaligned;
27 37
@@ -34,218 +44,148 @@ static __always_inline u32 __get_unaligned_cpu32(const u8 *p)
34 return unaligned; 44 return unaligned;
35} 45}
36 46
37struct __una_u16 { u16 x __attribute__((packed)); };
38struct __una_u32 { u32 x __attribute__((packed)); };
39struct __una_u64 { u64 x __attribute__((packed)); };
40
41static inline u16 __get_unaligned_cpu16(const u8 *p)
42{
43#ifdef __LITTLE_ENDIAN
44 return p[0] | p[1] << 8;
45#else
46 return p[0] << 8 | p[1];
47#endif
48}
49
50/* 47/*
51 * Even though movua.l supports auto-increment on the read side, it can 48 * Even though movua.l supports auto-increment on the read side, it can
52 * only store to r0 due to instruction encoding constraints, so just let 49 * only store to r0 due to instruction encoding constraints, so just let
53 * the compiler sort it out on its own. 50 * the compiler sort it out on its own.
54 */ 51 */
55static inline u64 __get_unaligned_cpu64(const u8 *p) 52static inline u64 sh4a_get_unaligned_cpu64(const u8 *p)
56{ 53{
57#ifdef __LITTLE_ENDIAN 54#ifdef __LITTLE_ENDIAN
58 return (u64)__get_unaligned_cpu32(p + 4) << 32 | 55 return (u64)sh4a_get_unaligned_cpu32(p + 4) << 32 |
59 __get_unaligned_cpu32(p); 56 sh4a_get_unaligned_cpu32(p);
60#else 57#else
61 return (u64)__get_unaligned_cpu32(p) << 32 | 58 return (u64)sh4a_get_unaligned_cpu32(p) << 32 |
62 __get_unaligned_cpu32(p + 4); 59 sh4a_get_unaligned_cpu32(p + 4);
63#endif 60#endif
64} 61}
65 62
66static inline u16 get_unaligned_le16(const void *p) 63static inline u16 get_unaligned_le16(const void *p)
67{ 64{
68 return le16_to_cpu(__get_unaligned_cpu16(p)); 65 return le16_to_cpu(sh4a_get_unaligned_cpu16(p));
69} 66}
70 67
71static inline u32 get_unaligned_le32(const void *p) 68static inline u32 get_unaligned_le32(const void *p)
72{ 69{
73 return le32_to_cpu(__get_unaligned_cpu32(p)); 70 return le32_to_cpu(sh4a_get_unaligned_cpu32(p));
74} 71}
75 72
76static inline u64 get_unaligned_le64(const void *p) 73static inline u64 get_unaligned_le64(const void *p)
77{ 74{
78 return le64_to_cpu(__get_unaligned_cpu64(p)); 75 return le64_to_cpu(sh4a_get_unaligned_cpu64(p));
79} 76}
80 77
81static inline u16 get_unaligned_be16(const void *p) 78static inline u16 get_unaligned_be16(const void *p)
82{ 79{
83 return be16_to_cpu(__get_unaligned_cpu16(p)); 80 return be16_to_cpu(sh4a_get_unaligned_cpu16(p));
84} 81}
85 82
86static inline u32 get_unaligned_be32(const void *p) 83static inline u32 get_unaligned_be32(const void *p)
87{ 84{
88 return be32_to_cpu(__get_unaligned_cpu32(p)); 85 return be32_to_cpu(sh4a_get_unaligned_cpu32(p));
89} 86}
90 87
91static inline u64 get_unaligned_be64(const void *p) 88static inline u64 get_unaligned_be64(const void *p)
92{ 89{
93 return be64_to_cpu(__get_unaligned_cpu64(p)); 90 return be64_to_cpu(sh4a_get_unaligned_cpu64(p));
94} 91}
95 92
96static inline void __put_le16_noalign(u8 *p, u16 val) 93static inline void nonnative_put_le16(u16 val, u8 *p)
97{ 94{
98 *p++ = val; 95 *p++ = val;
99 *p++ = val >> 8; 96 *p++ = val >> 8;
100} 97}
101 98
102static inline void __put_le32_noalign(u8 *p, u32 val) 99static inline void nonnative_put_le32(u32 val, u8 *p)
103{ 100{
104 __put_le16_noalign(p, val); 101 nonnative_put_le16(val, p);
105 __put_le16_noalign(p + 2, val >> 16); 102 nonnative_put_le16(val >> 16, p + 2);
106} 103}
107 104
108static inline void __put_le64_noalign(u8 *p, u64 val) 105static inline void nonnative_put_le64(u64 val, u8 *p)
109{ 106{
110 __put_le32_noalign(p, val); 107 nonnative_put_le32(val, p);
111 __put_le32_noalign(p + 4, val >> 32); 108 nonnative_put_le32(val >> 32, p + 4);
112} 109}
113 110
114static inline void __put_be16_noalign(u8 *p, u16 val) 111static inline void nonnative_put_be16(u16 val, u8 *p)
115{ 112{
116 *p++ = val >> 8; 113 *p++ = val >> 8;
117 *p++ = val; 114 *p++ = val;
118} 115}
119 116
120static inline void __put_be32_noalign(u8 *p, u32 val) 117static inline void nonnative_put_be32(u32 val, u8 *p)
121{ 118{
122 __put_be16_noalign(p, val >> 16); 119 nonnative_put_be16(val >> 16, p);
123 __put_be16_noalign(p + 2, val); 120 nonnative_put_be16(val, p + 2);
124} 121}
125 122
126static inline void __put_be64_noalign(u8 *p, u64 val) 123static inline void nonnative_put_be64(u64 val, u8 *p)
127{ 124{
128 __put_be32_noalign(p, val >> 32); 125 nonnative_put_be32(val >> 32, p);
129 __put_be32_noalign(p + 4, val); 126 nonnative_put_be32(val, p + 4);
130} 127}
131 128
132static inline void put_unaligned_le16(u16 val, void *p) 129static inline void put_unaligned_le16(u16 val, void *p)
133{ 130{
134#ifdef __LITTLE_ENDIAN 131#ifdef __LITTLE_ENDIAN
135 ((struct __una_u16 *)p)->x = val; 132 __put_unaligned_cpu16(val, p);
136#else 133#else
137 __put_le16_noalign(p, val); 134 nonnative_put_le16(val, p);
138#endif 135#endif
139} 136}
140 137
141static inline void put_unaligned_le32(u32 val, void *p) 138static inline void put_unaligned_le32(u32 val, void *p)
142{ 139{
143#ifdef __LITTLE_ENDIAN 140#ifdef __LITTLE_ENDIAN
144 ((struct __una_u32 *)p)->x = val; 141 __put_unaligned_cpu32(val, p);
145#else 142#else
146 __put_le32_noalign(p, val); 143 nonnative_put_le32(val, p);
147#endif 144#endif
148} 145}
149 146
150static inline void put_unaligned_le64(u64 val, void *p) 147static inline void put_unaligned_le64(u64 val, void *p)
151{ 148{
152#ifdef __LITTLE_ENDIAN 149#ifdef __LITTLE_ENDIAN
153 ((struct __una_u64 *)p)->x = val; 150 __put_unaligned_cpu64(val, p);
154#else 151#else
155 __put_le64_noalign(p, val); 152 nonnative_put_le64(val, p);
156#endif 153#endif
157} 154}
158 155
159static inline void put_unaligned_be16(u16 val, void *p) 156static inline void put_unaligned_be16(u16 val, void *p)
160{ 157{
161#ifdef __BIG_ENDIAN 158#ifdef __BIG_ENDIAN
162 ((struct __una_u16 *)p)->x = val; 159 __put_unaligned_cpu16(val, p);
163#else 160#else
164 __put_be16_noalign(p, val); 161 nonnative_put_be16(val, p);
165#endif 162#endif
166} 163}
167 164
168static inline void put_unaligned_be32(u32 val, void *p) 165static inline void put_unaligned_be32(u32 val, void *p)
169{ 166{
170#ifdef __BIG_ENDIAN 167#ifdef __BIG_ENDIAN
171 ((struct __una_u32 *)p)->x = val; 168 __put_unaligned_cpu32(val, p);
172#else 169#else
173 __put_be32_noalign(p, val); 170 nonnative_put_be32(val, p);
174#endif 171#endif
175} 172}
176 173
177static inline void put_unaligned_be64(u64 val, void *p) 174static inline void put_unaligned_be64(u64 val, void *p)
178{ 175{
179#ifdef __BIG_ENDIAN 176#ifdef __BIG_ENDIAN
180 ((struct __una_u64 *)p)->x = val; 177 __put_unaligned_cpu64(val, p);
181#else 178#else
182 __put_be64_noalign(p, val); 179 nonnative_put_be64(val, p);
183#endif 180#endif
184} 181}
185 182
186/* 183/*
187 * Cause a link-time error if we try an unaligned access other than 184 * While it's a bit non-obvious, even though the generic le/be wrappers
188 * 1,2,4 or 8 bytes long 185 * use the __get/put_xxx prefixing, they actually wrap in to the
186 * non-prefixed get/put_xxx variants as provided above.
189 */ 187 */
190extern void __bad_unaligned_access_size(void); 188#include <linux/unaligned/generic.h>
191
192#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({ \
193 __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \
194 __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)), \
195 __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)), \
196 __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)), \
197 __bad_unaligned_access_size())))); \
198 }))
199
200#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({ \
201 __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \
202 __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)), \
203 __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)), \
204 __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)), \
205 __bad_unaligned_access_size())))); \
206 }))
207
208#define __put_unaligned_le(val, ptr) ({ \
209 void *__gu_p = (ptr); \
210 switch (sizeof(*(ptr))) { \
211 case 1: \
212 *(u8 *)__gu_p = (__force u8)(val); \
213 break; \
214 case 2: \
215 put_unaligned_le16((__force u16)(val), __gu_p); \
216 break; \
217 case 4: \
218 put_unaligned_le32((__force u32)(val), __gu_p); \
219 break; \
220 case 8: \
221 put_unaligned_le64((__force u64)(val), __gu_p); \
222 break; \
223 default: \
224 __bad_unaligned_access_size(); \
225 break; \
226 } \
227 (void)0; })
228
229#define __put_unaligned_be(val, ptr) ({ \
230 void *__gu_p = (ptr); \
231 switch (sizeof(*(ptr))) { \
232 case 1: \
233 *(u8 *)__gu_p = (__force u8)(val); \
234 break; \
235 case 2: \
236 put_unaligned_be16((__force u16)(val), __gu_p); \
237 break; \
238 case 4: \
239 put_unaligned_be32((__force u32)(val), __gu_p); \
240 break; \
241 case 8: \
242 put_unaligned_be64((__force u64)(val), __gu_p); \
243 break; \
244 default: \
245 __bad_unaligned_access_size(); \
246 break; \
247 } \
248 (void)0; })
249 189
250#ifdef __LITTLE_ENDIAN 190#ifdef __LITTLE_ENDIAN
251# define get_unaligned __get_unaligned_le 191# define get_unaligned __get_unaligned_le
diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h
index 40f0c2d3690c..a9cdac469927 100644
--- a/arch/sh/include/mach-sdk7786/mach/fpga.h
+++ b/arch/sh/include/mach-sdk7786/mach/fpga.h
@@ -14,11 +14,16 @@
14#define INTTESTR 0x040 14#define INTTESTR 0x040
15#define SYSSR 0x050 15#define SYSSR 0x050
16#define NRGPR 0x060 16#define NRGPR 0x060
17
17#define NMISR 0x070 18#define NMISR 0x070
19#define NMISR_MAN_NMI BIT(0)
20#define NMISR_AUX_NMI BIT(1)
21#define NMISR_MASK (NMISR_MAN_NMI | NMISR_AUX_NMI)
18 22
19#define NMIMR 0x080 23#define NMIMR 0x080
20#define NMIMR_MAN_NMIM BIT(0) /* Manual NMI mask */ 24#define NMIMR_MAN_NMIM BIT(0) /* Manual NMI mask */
21#define NMIMR_AUX_NMIM BIT(1) /* Auxiliary NMI mask */ 25#define NMIMR_AUX_NMIM BIT(1) /* Auxiliary NMI mask */
26#define NMIMR_MASK (NMIMR_MAN_NMIM | NMIMR_AUX_NMIM)
22 27
23#define INTBSR 0x090 28#define INTBSR 0x090
24#define INTBMR 0x0a0 29#define INTBMR 0x0a0
@@ -126,6 +131,9 @@
126extern void __iomem *sdk7786_fpga_base; 131extern void __iomem *sdk7786_fpga_base;
127extern void sdk7786_fpga_init(void); 132extern void sdk7786_fpga_init(void);
128 133
134/* arch/sh/boards/mach-sdk7786/nmi.c */
135extern void sdk7786_nmi_init(void);
136
129#define SDK7786_FPGA_REGADDR(reg) (sdk7786_fpga_base + (reg)) 137#define SDK7786_FPGA_REGADDR(reg) (sdk7786_fpga_base + (reg))
130 138
131/* 139/*
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index cf6522179523..77f7ae1d4647 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -20,6 +20,11 @@ obj-y := debugtraps.o dma-nommu.o dumpstack.o \
20 syscalls_$(BITS).o time.o topology.o traps.o \ 20 syscalls_$(BITS).o time.o topology.o traps.o \
21 traps_$(BITS).o unwinder.o 21 traps_$(BITS).o unwinder.o
22 22
23ifndef CONFIG_GENERIC_IOMAP
24obj-y += iomap.o
25obj-$(CONFIG_HAS_IOPORT) += ioport.o
26endif
27
23obj-y += cpu/ 28obj-y += cpu/
24obj-$(CONFIG_VSYSCALL) += vsyscall/ 29obj-$(CONFIG_VSYSCALL) += vsyscall/
25obj-$(CONFIG_SMP) += smp.o 30obj-$(CONFIG_SMP) += smp.o
@@ -39,7 +44,6 @@ obj-$(CONFIG_DUMP_CODE) += disassemble.o
39obj-$(CONFIG_HIBERNATION) += swsusp.o 44obj-$(CONFIG_HIBERNATION) += swsusp.o
40obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o 45obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o
41obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_callchain.o 46obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_callchain.o
42obj-$(CONFIG_HAS_IOPORT) += io_generic.o
43 47
44obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o 48obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
45obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o 49obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 4edcb60a1355..d49c2135fd48 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -20,4 +20,4 @@ obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
20obj-$(CONFIG_SH_FPU) += fpu.o 20obj-$(CONFIG_SH_FPU) += fpu.o
21obj-$(CONFIG_SH_FPU_EMU) += fpu.o 21obj-$(CONFIG_SH_FPU_EMU) += fpu.o
22 22
23obj-y += irq/ init.o clock.o hwblk.o 23obj-y += irq/ init.o clock.o hwblk.o proc.o
diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c
new file mode 100644
index 000000000000..e80a936f409a
--- /dev/null
+++ b/arch/sh/kernel/cpu/proc.c
@@ -0,0 +1,148 @@
1#include <linux/seq_file.h>
2#include <linux/kernel.h>
3#include <linux/module.h>
4#include <asm/machvec.h>
5#include <asm/processor.h>
6
7static const char *cpu_name[] = {
8 [CPU_SH7201] = "SH7201",
9 [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
10 [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
11 [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
12 [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
13 [CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
14 [CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720",
15 [CPU_SH7721] = "SH7721", [CPU_SH7729] = "SH7729",
16 [CPU_SH7750] = "SH7750", [CPU_SH7750S] = "SH7750S",
17 [CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751",
18 [CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760",
19 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
20 [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
21 [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
22 [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
23 [CPU_SH7786] = "SH7786", [CPU_SH7757] = "SH7757",
24 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
25 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
26 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
27 [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
28 [CPU_SH_NONE] = "Unknown"
29};
30
31const char *get_cpu_subtype(struct sh_cpuinfo *c)
32{
33 return cpu_name[c->type];
34}
35EXPORT_SYMBOL(get_cpu_subtype);
36
37#ifdef CONFIG_PROC_FS
38/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
39static const char *cpu_flags[] = {
40 "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
41 "ptea", "llsc", "l2", "op32", "pteaex", NULL
42};
43
44static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
45{
46 unsigned long i;
47
48 seq_printf(m, "cpu flags\t:");
49
50 if (!c->flags) {
51 seq_printf(m, " %s\n", cpu_flags[0]);
52 return;
53 }
54
55 for (i = 0; cpu_flags[i]; i++)
56 if ((c->flags & (1 << i)))
57 seq_printf(m, " %s", cpu_flags[i+1]);
58
59 seq_printf(m, "\n");
60}
61
62static void show_cacheinfo(struct seq_file *m, const char *type,
63 struct cache_info info)
64{
65 unsigned int cache_size;
66
67 cache_size = info.ways * info.sets * info.linesz;
68
69 seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
70 type, cache_size >> 10, info.ways);
71}
72
73/*
74 * Get CPU information for use by the procfs.
75 */
76static int show_cpuinfo(struct seq_file *m, void *v)
77{
78 struct sh_cpuinfo *c = v;
79 unsigned int cpu = c - cpu_data;
80
81 if (!cpu_online(cpu))
82 return 0;
83
84 if (cpu == 0)
85 seq_printf(m, "machine\t\t: %s\n", get_system_type());
86 else
87 seq_printf(m, "\n");
88
89 seq_printf(m, "processor\t: %d\n", cpu);
90 seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
91 seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
92 if (c->cut_major == -1)
93 seq_printf(m, "cut\t\t: unknown\n");
94 else if (c->cut_minor == -1)
95 seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
96 else
97 seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
98
99 show_cpuflags(m, c);
100
101 seq_printf(m, "cache type\t: ");
102
103 /*
104 * Check for what type of cache we have, we support both the
105 * unified cache on the SH-2 and SH-3, as well as the harvard
106 * style cache on the SH-4.
107 */
108 if (c->icache.flags & SH_CACHE_COMBINED) {
109 seq_printf(m, "unified\n");
110 show_cacheinfo(m, "cache", c->icache);
111 } else {
112 seq_printf(m, "split (harvard)\n");
113 show_cacheinfo(m, "icache", c->icache);
114 show_cacheinfo(m, "dcache", c->dcache);
115 }
116
117 /* Optional secondary cache */
118 if (c->flags & CPU_HAS_L2_CACHE)
119 show_cacheinfo(m, "scache", c->scache);
120
121 seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
122
123 seq_printf(m, "bogomips\t: %lu.%02lu\n",
124 c->loops_per_jiffy/(500000/HZ),
125 (c->loops_per_jiffy/(5000/HZ)) % 100);
126
127 return 0;
128}
129
130static void *c_start(struct seq_file *m, loff_t *pos)
131{
132 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
133}
134static void *c_next(struct seq_file *m, void *v, loff_t *pos)
135{
136 ++*pos;
137 return c_start(m, pos);
138}
139static void c_stop(struct seq_file *m, void *v)
140{
141}
142const struct seq_operations cpuinfo_op = {
143 .start = c_start,
144 .next = c_next,
145 .stop = c_stop,
146 .show = show_cpuinfo,
147};
148#endif /* CONFIG_PROC_FS */
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index 0c9f24d7a02f..5b7f12e58a8d 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -14,24 +14,18 @@
14 */ 14 */
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/io.h>
17#include <asm/clock.h> 18#include <asm/clock.h>
18#include <asm/freq.h> 19#include <asm/freq.h>
19#include <asm/io.h> 20#include <asm/processor.h>
20 21
21static const int pll1rate[] = {1,2}; 22static const int pll1rate[] = {1,2};
22static const int pfc_divisors[] = {1,2,0,4}; 23static const int pfc_divisors[] = {1,2,0,4};
23 24static unsigned int pll2_mult;
24#if (CONFIG_SH_CLK_MD == 1) || (CONFIG_SH_CLK_MD == 2)
25#define PLL2 (4)
26#elif (CONFIG_SH_CLK_MD == 5) || (CONFIG_SH_CLK_MD == 6)
27#define PLL2 (2)
28#else
29#error "Illigal Clock Mode!"
30#endif
31 25
32static void master_clk_init(struct clk *clk) 26static void master_clk_init(struct clk *clk)
33{ 27{
34 clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; 28 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
35} 29}
36 30
37static struct clk_ops sh7619_master_clk_ops = { 31static struct clk_ops sh7619_master_clk_ops = {
@@ -70,6 +64,14 @@ static struct clk_ops *sh7619_clk_ops[] = {
70 64
71void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 65void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
72{ 66{
67 if (test_mode_pin(MODE_PIN2 | MODE_PIN0) ||
68 test_mode_pin(MODE_PIN2 | MODE_PIN1))
69 pll2_mult = 2;
70 else if (test_mode_pin(MODE_PIN0) || test_mode_pin(MODE_PIN1))
71 pll2_mult = 4;
72
73 BUG_ON(!pll2_mult);
74
73 if (idx < ARRAY_SIZE(sh7619_clk_ops)) 75 if (idx < ARRAY_SIZE(sh7619_clk_ops))
74 *ops = sh7619_clk_ops[idx]; 76 *ops = sh7619_clk_ops[idx];
75} 77}
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index c509c40cba4b..1174e2d96c03 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -22,19 +22,12 @@ static const int pll1rate[]={1,2,3,4,6,8};
22static const int pfc_divisors[]={1,2,3,4,6,8,12}; 22static const int pfc_divisors[]={1,2,3,4,6,8,12};
23#define ifc_divisors pfc_divisors 23#define ifc_divisors pfc_divisors
24 24
25#if (CONFIG_SH_CLK_MD == 0) 25static unsigned int pll2_mult;
26#define PLL2 (4)
27#elif (CONFIG_SH_CLK_MD == 2)
28#define PLL2 (2)
29#elif (CONFIG_SH_CLK_MD == 3)
30#define PLL2 (1)
31#else
32#error "Illegal Clock Mode!"
33#endif
34 26
35static void master_clk_init(struct clk *clk) 27static void master_clk_init(struct clk *clk)
36{ 28{
37 clk->rate = 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 29 clk->rate = 10000000 * pll2_mult *
30 pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
38} 31}
39 32
40static struct clk_ops sh7201_master_clk_ops = { 33static struct clk_ops sh7201_master_clk_ops = {
@@ -80,6 +73,13 @@ static struct clk_ops *sh7201_clk_ops[] = {
80 73
81void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 74void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
82{ 75{
76 if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
77 pll2_mult = 1;
78 else if (test_mode_pin(MODE_PIN1))
79 pll2_mult = 2;
80 else
81 pll2_mult = 4;
82
83 if (idx < ARRAY_SIZE(sh7201_clk_ops)) 83 if (idx < ARRAY_SIZE(sh7201_clk_ops))
84 *ops = sh7201_clk_ops[idx]; 84 *ops = sh7201_clk_ops[idx];
85} 85}
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index 7e75d8f79502..95a008e8b735 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -25,21 +25,11 @@ static const int pll1rate[]={8,12,16,0};
25static const int pfc_divisors[]={1,2,3,4,6,8,12}; 25static const int pfc_divisors[]={1,2,3,4,6,8,12};
26#define ifc_divisors pfc_divisors 26#define ifc_divisors pfc_divisors
27 27
28#if (CONFIG_SH_CLK_MD == 0) 28static unsigned int pll2_mult;
29#define PLL2 (1)
30#elif (CONFIG_SH_CLK_MD == 1)
31#define PLL2 (2)
32#elif (CONFIG_SH_CLK_MD == 2)
33#define PLL2 (4)
34#elif (CONFIG_SH_CLK_MD == 3)
35#define PLL2 (4)
36#else
37#error "Illegal Clock Mode!"
38#endif
39 29
40static void master_clk_init(struct clk *clk) 30static void master_clk_init(struct clk *clk)
41{ 31{
42 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * PLL2 ; 32 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
43} 33}
44 34
45static struct clk_ops sh7203_master_clk_ops = { 35static struct clk_ops sh7203_master_clk_ops = {
@@ -79,6 +69,13 @@ static struct clk_ops *sh7203_clk_ops[] = {
79 69
80void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 70void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
81{ 71{
72 if (test_mode_pin(MODE_PIN1))
73 pll2_mult = 4;
74 else if (test_mode_pin(MODE_PIN0))
75 pll2_mult = 2;
76 else
77 pll2_mult = 1;
78
82 if (idx < ARRAY_SIZE(sh7203_clk_ops)) 79 if (idx < ARRAY_SIZE(sh7203_clk_ops))
83 *ops = sh7203_clk_ops[idx]; 80 *ops = sh7203_clk_ops[idx];
84} 81}
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index b27a5e2687ab..3c314d7cd6e6 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -22,19 +22,11 @@ static const int pll1rate[]={1,2,3,4,6,8};
22static const int pfc_divisors[]={1,2,3,4,6,8,12}; 22static const int pfc_divisors[]={1,2,3,4,6,8,12};
23#define ifc_divisors pfc_divisors 23#define ifc_divisors pfc_divisors
24 24
25#if (CONFIG_SH_CLK_MD == 2) 25static unsigned int pll2_mult;
26#define PLL2 (4)
27#elif (CONFIG_SH_CLK_MD == 6)
28#define PLL2 (2)
29#elif (CONFIG_SH_CLK_MD == 7)
30#define PLL2 (1)
31#else
32#error "Illigal Clock Mode!"
33#endif
34 26
35static void master_clk_init(struct clk *clk) 27static void master_clk_init(struct clk *clk)
36{ 28{
37 clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 29 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
38} 30}
39 31
40static struct clk_ops sh7206_master_clk_ops = { 32static struct clk_ops sh7206_master_clk_ops = {
@@ -79,7 +71,13 @@ static struct clk_ops *sh7206_clk_ops[] = {
79 71
80void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 72void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
81{ 73{
74 if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
75 pll2_mult = 1;
76 else if (test_mode_pin(MODE_PIN2 | MODE_PIN1))
77 pll2_mult = 2;
78 else if (test_mode_pin(MODE_PIN1))
79 pll2_mult = 4;
80
82 if (idx < ARRAY_SIZE(sh7206_clk_ops)) 81 if (idx < ARRAY_SIZE(sh7206_clk_ops))
83 *ops = sh7206_clk_ops[idx]; 82 *ops = sh7206_clk_ops[idx];
84} 83}
85
diff --git a/arch/sh/kernel/cpu/sh4/perf_event.c b/arch/sh/kernel/cpu/sh4/perf_event.c
index dbf3b4bb71fe..748955df018d 100644
--- a/arch/sh/kernel/cpu/sh4/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4/perf_event.c
@@ -250,4 +250,4 @@ static int __init sh7750_pmu_init(void)
250 250
251 return register_sh_pmu(&sh7750_pmu); 251 return register_sh_pmu(&sh7750_pmu);
252} 252}
253arch_initcall(sh7750_pmu_init); 253early_initcall(sh7750_pmu_init);
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c
index 580276525731..17e6bebfede0 100644
--- a/arch/sh/kernel/cpu/sh4a/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4a/perf_event.c
@@ -284,4 +284,4 @@ static int __init sh4a_pmu_init(void)
284 284
285 return register_sh_pmu(&sh4a_pmu); 285 return register_sh_pmu(&sh4a_pmu);
286} 286}
287arch_initcall(sh4a_pmu_init); 287early_initcall(sh4a_pmu_init);
diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c
deleted file mode 100644
index 447d78f666f9..000000000000
--- a/arch/sh/kernel/io_generic.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/*
2 * arch/sh/kernel/io_generic.c
3 *
4 * Copyright (C) 2000 Niibe Yutaka
5 * Copyright (C) 2005 - 2007 Paul Mundt
6 *
7 * Generic I/O routine. These can be used where a machine specific version
8 * is not required.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/module.h>
15#include <linux/io.h>
16#include <asm/machvec.h>
17
18#ifdef CONFIG_CPU_SH3
19/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a
20 * workaround. */
21/* I'm not sure SH7709 has this kind of bug */
22#define dummy_read() __raw_readb(0xba000000)
23#else
24#define dummy_read()
25#endif
26
27unsigned long generic_io_base = 0;
28
29u8 generic_inb(unsigned long port)
30{
31 return __raw_readb(__ioport_map(port, 1));
32}
33
34u16 generic_inw(unsigned long port)
35{
36 return __raw_readw(__ioport_map(port, 2));
37}
38
39u32 generic_inl(unsigned long port)
40{
41 return __raw_readl(__ioport_map(port, 4));
42}
43
44u8 generic_inb_p(unsigned long port)
45{
46 unsigned long v = generic_inb(port);
47
48 ctrl_delay();
49 return v;
50}
51
52u16 generic_inw_p(unsigned long port)
53{
54 unsigned long v = generic_inw(port);
55
56 ctrl_delay();
57 return v;
58}
59
60u32 generic_inl_p(unsigned long port)
61{
62 unsigned long v = generic_inl(port);
63
64 ctrl_delay();
65 return v;
66}
67
68/*
69 * insb/w/l all read a series of bytes/words/longs from a fixed port
70 * address. However as the port address doesn't change we only need to
71 * convert the port address to real address once.
72 */
73
74void generic_insb(unsigned long port, void *dst, unsigned long count)
75{
76 __raw_readsb(__ioport_map(port, 1), dst, count);
77 dummy_read();
78}
79
80void generic_insw(unsigned long port, void *dst, unsigned long count)
81{
82 __raw_readsw(__ioport_map(port, 2), dst, count);
83 dummy_read();
84}
85
86void generic_insl(unsigned long port, void *dst, unsigned long count)
87{
88 __raw_readsl(__ioport_map(port, 4), dst, count);
89 dummy_read();
90}
91
92void generic_outb(u8 b, unsigned long port)
93{
94 __raw_writeb(b, __ioport_map(port, 1));
95}
96
97void generic_outw(u16 b, unsigned long port)
98{
99 __raw_writew(b, __ioport_map(port, 2));
100}
101
102void generic_outl(u32 b, unsigned long port)
103{
104 __raw_writel(b, __ioport_map(port, 4));
105}
106
107void generic_outb_p(u8 b, unsigned long port)
108{
109 generic_outb(b, port);
110 ctrl_delay();
111}
112
113void generic_outw_p(u16 b, unsigned long port)
114{
115 generic_outw(b, port);
116 ctrl_delay();
117}
118
119void generic_outl_p(u32 b, unsigned long port)
120{
121 generic_outl(b, port);
122 ctrl_delay();
123}
124
125/*
126 * outsb/w/l all write a series of bytes/words/longs to a fixed port
127 * address. However as the port address doesn't change we only need to
128 * convert the port address to real address once.
129 */
130void generic_outsb(unsigned long port, const void *src, unsigned long count)
131{
132 __raw_writesb(__ioport_map(port, 1), src, count);
133 dummy_read();
134}
135
136void generic_outsw(unsigned long port, const void *src, unsigned long count)
137{
138 __raw_writesw(__ioport_map(port, 2), src, count);
139 dummy_read();
140}
141
142void generic_outsl(unsigned long port, const void *src, unsigned long count)
143{
144 __raw_writesl(__ioport_map(port, 4), src, count);
145 dummy_read();
146}
147
148void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
149{
150#ifdef P1SEG
151 if (PXSEG(addr) >= P1SEG)
152 return (void __iomem *)addr;
153#endif
154
155 return (void __iomem *)(addr + generic_io_base);
156}
157
158void generic_ioport_unmap(void __iomem *addr)
159{
160}
161
162#ifndef CONFIG_GENERIC_IOMAP
163void __iomem *ioport_map(unsigned long port, unsigned int nr)
164{
165 void __iomem *ret;
166
167 ret = __ioport_map_trapped(port, nr);
168 if (ret)
169 return ret;
170
171 return __ioport_map(port, nr);
172}
173EXPORT_SYMBOL(ioport_map);
174
175void ioport_unmap(void __iomem *addr)
176{
177 sh_mv.mv_ioport_unmap(addr);
178}
179EXPORT_SYMBOL(ioport_unmap);
180#endif /* CONFIG_GENERIC_IOMAP */
diff --git a/arch/sh/kernel/iomap.c b/arch/sh/kernel/iomap.c
new file mode 100644
index 000000000000..2e8e8b9b9cef
--- /dev/null
+++ b/arch/sh/kernel/iomap.c
@@ -0,0 +1,165 @@
1/*
2 * arch/sh/kernel/iomap.c
3 *
4 * Copyright (C) 2000 Niibe Yutaka
5 * Copyright (C) 2005 - 2007 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/module.h>
12#include <linux/io.h>
13
14unsigned int ioread8(void __iomem *addr)
15{
16 return readb(addr);
17}
18EXPORT_SYMBOL(ioread8);
19
20unsigned int ioread16(void __iomem *addr)
21{
22 return readw(addr);
23}
24EXPORT_SYMBOL(ioread16);
25
26unsigned int ioread16be(void __iomem *addr)
27{
28 return be16_to_cpu(__raw_readw(addr));
29}
30EXPORT_SYMBOL(ioread16be);
31
32unsigned int ioread32(void __iomem *addr)
33{
34 return readl(addr);
35}
36EXPORT_SYMBOL(ioread32);
37
38unsigned int ioread32be(void __iomem *addr)
39{
40 return be32_to_cpu(__raw_readl(addr));
41}
42EXPORT_SYMBOL(ioread32be);
43
44void iowrite8(u8 val, void __iomem *addr)
45{
46 writeb(val, addr);
47}
48EXPORT_SYMBOL(iowrite8);
49
50void iowrite16(u16 val, void __iomem *addr)
51{
52 writew(val, addr);
53}
54EXPORT_SYMBOL(iowrite16);
55
56void iowrite16be(u16 val, void __iomem *addr)
57{
58 __raw_writew(cpu_to_be16(val), addr);
59}
60EXPORT_SYMBOL(iowrite16be);
61
62void iowrite32(u32 val, void __iomem *addr)
63{
64 writel(val, addr);
65}
66EXPORT_SYMBOL(iowrite32);
67
68void iowrite32be(u32 val, void __iomem *addr)
69{
70 __raw_writel(cpu_to_be32(val), addr);
71}
72EXPORT_SYMBOL(iowrite32be);
73
74/*
75 * These are the "repeat MMIO read/write" functions.
76 * Note the "__raw" accesses, since we don't want to
77 * convert to CPU byte order. We write in "IO byte
78 * order" (we also don't have IO barriers).
79 */
80static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
81{
82 while (--count >= 0) {
83 u8 data = __raw_readb(addr);
84 *dst = data;
85 dst++;
86 }
87}
88
89static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
90{
91 while (--count >= 0) {
92 u16 data = __raw_readw(addr);
93 *dst = data;
94 dst++;
95 }
96}
97
98static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
99{
100 while (--count >= 0) {
101 u32 data = __raw_readl(addr);
102 *dst = data;
103 dst++;
104 }
105}
106
107static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
108{
109 while (--count >= 0) {
110 __raw_writeb(*src, addr);
111 src++;
112 }
113}
114
115static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
116{
117 while (--count >= 0) {
118 __raw_writew(*src, addr);
119 src++;
120 }
121}
122
123static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
124{
125 while (--count >= 0) {
126 __raw_writel(*src, addr);
127 src++;
128 }
129}
130
131void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
132{
133 mmio_insb(addr, dst, count);
134}
135EXPORT_SYMBOL(ioread8_rep);
136
137void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
138{
139 mmio_insw(addr, dst, count);
140}
141EXPORT_SYMBOL(ioread16_rep);
142
143void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
144{
145 mmio_insl(addr, dst, count);
146}
147EXPORT_SYMBOL(ioread32_rep);
148
149void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
150{
151 mmio_outsb(addr, src, count);
152}
153EXPORT_SYMBOL(iowrite8_rep);
154
155void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
156{
157 mmio_outsw(addr, src, count);
158}
159EXPORT_SYMBOL(iowrite16_rep);
160
161void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
162{
163 mmio_outsl(addr, src, count);
164}
165EXPORT_SYMBOL(iowrite32_rep);
diff --git a/arch/sh/kernel/ioport.c b/arch/sh/kernel/ioport.c
new file mode 100644
index 000000000000..e3ad6103e7c1
--- /dev/null
+++ b/arch/sh/kernel/ioport.c
@@ -0,0 +1,43 @@
1/*
2 * arch/sh/kernel/ioport.c
3 *
4 * Copyright (C) 2000 Niibe Yutaka
5 * Copyright (C) 2005 - 2007 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/module.h>
12#include <linux/io.h>
13
14const unsigned long sh_io_port_base __read_mostly = -1;
15EXPORT_SYMBOL(sh_io_port_base);
16
17void __iomem *__ioport_map(unsigned long addr, unsigned int size)
18{
19 if (sh_mv.mv_ioport_map)
20 return sh_mv.mv_ioport_map(addr, size);
21
22 return (void __iomem *)(addr + sh_io_port_base);
23}
24EXPORT_SYMBOL(__ioport_map);
25
26void __iomem *ioport_map(unsigned long port, unsigned int nr)
27{
28 void __iomem *ret;
29
30 ret = __ioport_map_trapped(port, nr);
31 if (ret)
32 return ret;
33
34 return __ioport_map(port, nr);
35}
36EXPORT_SYMBOL(ioport_map);
37
38void ioport_unmap(void __iomem *addr)
39{
40 if (sh_mv.mv_ioport_unmap)
41 sh_mv.mv_ioport_unmap(addr);
42}
43EXPORT_SYMBOL(ioport_unmap);
diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
index 9f9bb63616ad..3d722e49db08 100644
--- a/arch/sh/kernel/machvec.c
+++ b/arch/sh/kernel/machvec.c
@@ -118,28 +118,6 @@ void __init sh_mv_setup(void)
118 sh_mv.mv_##elem = generic_##elem; \ 118 sh_mv.mv_##elem = generic_##elem; \
119} while (0) 119} while (0)
120 120
121#ifdef CONFIG_HAS_IOPORT
122
123#ifdef P2SEG
124 __set_io_port_base(P2SEG);
125#else
126 __set_io_port_base(0);
127#endif
128
129 mv_set(inb); mv_set(inw); mv_set(inl);
130 mv_set(outb); mv_set(outw); mv_set(outl);
131
132 mv_set(inb_p); mv_set(inw_p); mv_set(inl_p);
133 mv_set(outb_p); mv_set(outw_p); mv_set(outl_p);
134
135 mv_set(insb); mv_set(insw); mv_set(insl);
136 mv_set(outsb); mv_set(outsw); mv_set(outsl);
137
138 mv_set(ioport_map);
139 mv_set(ioport_unmap);
140
141#endif
142
143 mv_set(irq_demux); 121 mv_set(irq_demux);
144 mv_set(mode_pins); 122 mv_set(mode_pins);
145 mv_set(mem_init); 123 mv_set(mem_init);
diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c
index 5a4b33435650..2ee21a47b5af 100644
--- a/arch/sh/kernel/perf_event.c
+++ b/arch/sh/kernel/perf_event.c
@@ -389,7 +389,7 @@ int __cpuinit register_sh_pmu(struct sh_pmu *_pmu)
389 389
390 WARN_ON(_pmu->num_events > MAX_HWEVENTS); 390 WARN_ON(_pmu->num_events > MAX_HWEVENTS);
391 391
392 perf_pmu_register(&pmu); 392 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
393 perf_cpu_notifier(sh_pmu_notifier); 393 perf_cpu_notifier(sh_pmu_notifier);
394 return 0; 394 return 0;
395} 395}
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index d6b018c7ebdc..4f267160c515 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -12,7 +12,6 @@
12#include <linux/initrd.h> 12#include <linux/initrd.h>
13#include <linux/bootmem.h> 13#include <linux/bootmem.h>
14#include <linux/console.h> 14#include <linux/console.h>
15#include <linux/seq_file.h>
16#include <linux/root_dev.h> 15#include <linux/root_dev.h>
17#include <linux/utsname.h> 16#include <linux/utsname.h>
18#include <linux/nodemask.h> 17#include <linux/nodemask.h>
@@ -319,146 +318,3 @@ int test_mode_pin(int pin)
319{ 318{
320 return sh_mv.mv_mode_pins() & pin; 319 return sh_mv.mv_mode_pins() & pin;
321} 320}
322
323static const char *cpu_name[] = {
324 [CPU_SH7201] = "SH7201",
325 [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
326 [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
327 [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
328 [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
329 [CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
330 [CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720",
331 [CPU_SH7721] = "SH7721", [CPU_SH7729] = "SH7729",
332 [CPU_SH7750] = "SH7750", [CPU_SH7750S] = "SH7750S",
333 [CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751",
334 [CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760",
335 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
336 [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
337 [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
338 [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
339 [CPU_SH7786] = "SH7786", [CPU_SH7757] = "SH7757",
340 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
341 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
342 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
343 [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
344 [CPU_SH_NONE] = "Unknown"
345};
346
347const char *get_cpu_subtype(struct sh_cpuinfo *c)
348{
349 return cpu_name[c->type];
350}
351EXPORT_SYMBOL(get_cpu_subtype);
352
353#ifdef CONFIG_PROC_FS
354/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
355static const char *cpu_flags[] = {
356 "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
357 "ptea", "llsc", "l2", "op32", "pteaex", NULL
358};
359
360static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
361{
362 unsigned long i;
363
364 seq_printf(m, "cpu flags\t:");
365
366 if (!c->flags) {
367 seq_printf(m, " %s\n", cpu_flags[0]);
368 return;
369 }
370
371 for (i = 0; cpu_flags[i]; i++)
372 if ((c->flags & (1 << i)))
373 seq_printf(m, " %s", cpu_flags[i+1]);
374
375 seq_printf(m, "\n");
376}
377
378static void show_cacheinfo(struct seq_file *m, const char *type,
379 struct cache_info info)
380{
381 unsigned int cache_size;
382
383 cache_size = info.ways * info.sets * info.linesz;
384
385 seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
386 type, cache_size >> 10, info.ways);
387}
388
389/*
390 * Get CPU information for use by the procfs.
391 */
392static int show_cpuinfo(struct seq_file *m, void *v)
393{
394 struct sh_cpuinfo *c = v;
395 unsigned int cpu = c - cpu_data;
396
397 if (!cpu_online(cpu))
398 return 0;
399
400 if (cpu == 0)
401 seq_printf(m, "machine\t\t: %s\n", get_system_type());
402 else
403 seq_printf(m, "\n");
404
405 seq_printf(m, "processor\t: %d\n", cpu);
406 seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
407 seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
408 if (c->cut_major == -1)
409 seq_printf(m, "cut\t\t: unknown\n");
410 else if (c->cut_minor == -1)
411 seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
412 else
413 seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
414
415 show_cpuflags(m, c);
416
417 seq_printf(m, "cache type\t: ");
418
419 /*
420 * Check for what type of cache we have, we support both the
421 * unified cache on the SH-2 and SH-3, as well as the harvard
422 * style cache on the SH-4.
423 */
424 if (c->icache.flags & SH_CACHE_COMBINED) {
425 seq_printf(m, "unified\n");
426 show_cacheinfo(m, "cache", c->icache);
427 } else {
428 seq_printf(m, "split (harvard)\n");
429 show_cacheinfo(m, "icache", c->icache);
430 show_cacheinfo(m, "dcache", c->dcache);
431 }
432
433 /* Optional secondary cache */
434 if (c->flags & CPU_HAS_L2_CACHE)
435 show_cacheinfo(m, "scache", c->scache);
436
437 seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
438
439 seq_printf(m, "bogomips\t: %lu.%02lu\n",
440 c->loops_per_jiffy/(500000/HZ),
441 (c->loops_per_jiffy/(5000/HZ)) % 100);
442
443 return 0;
444}
445
446static void *c_start(struct seq_file *m, loff_t *pos)
447{
448 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
449}
450static void *c_next(struct seq_file *m, void *v, loff_t *pos)
451{
452 ++*pos;
453 return c_start(m, pos);
454}
455static void c_stop(struct seq_file *m, void *v)
456{
457}
458const struct seq_operations cpuinfo_op = {
459 .start = c_start,
460 .next = c_next,
461 .stop = c_stop,
462 .show = show_cpuinfo,
463};
464#endif /* CONFIG_PROC_FS */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 11:32:10 -0500