3 files changed, 25 insertions, 14 deletions

diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 64dc1ad59801..7f7b52f9beba 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -227,7 +227,7 @@ endchoice
 
 choice
         prompt "HugeTLB page size"
-        depends on HUGETLB_PAGE && (CPU_SH4 || CPU_SH5) && MMU
+        depends on HUGETLB_PAGE
         default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
         default HUGETLB_PAGE_SIZE_64K
 
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index a98c7d8984fa..b7f235c74d66 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -26,7 +26,7 @@
 #define MAX_DCACHE_PAGES        64      /* XXX: Tune for ways */
 #define MAX_ICACHE_PAGES        32
 
-static void __flush_cache_4096(unsigned long addr, unsigned long phys,
+static void __flush_cache_one(unsigned long addr, unsigned long phys,
                                unsigned long exec_offset);
 
 /*
@@ -72,6 +72,7 @@ static void __uses_jump_to_uncached sh4_flush_icache_range(void *args)
 
         for (v = start; v < end; v += L1_CACHE_BYTES) {
                 unsigned long icacheaddr;
+                int j, n;
 
                 __ocbwb(v);
 
@@ -79,8 +80,10 @@ static void __uses_jump_to_uncached sh4_flush_icache_range(void *args)
                                 cpu_data->icache.entry_mask);
 
                 /* Clear i-cache line valid-bit */
+                n = boot_cpu_data.icache.n_aliases;
                 for (i = 0; i < cpu_data->icache.ways; i++) {
-                        __raw_writel(0, icacheaddr);
+                        for (j = 0; j < n; j++)
+                                __raw_writel(0, icacheaddr + (j * PAGE_SIZE));
                         icacheaddr += cpu_data->icache.way_incr;
                 }
         }
@@ -89,8 +92,7 @@ static void __uses_jump_to_uncached sh4_flush_icache_range(void *args)
         local_irq_restore(flags);
 }
 
-static inline void flush_cache_4096(unsigned long start,
-                                    unsigned long phys)
+static inline void flush_cache_one(unsigned long start, unsigned long phys)
 {
         unsigned long flags, exec_offset = 0;
 
@@ -103,8 +105,7 @@ static inline void flush_cache_4096(unsigned long start,
                 exec_offset = 0x20000000;
 
         local_irq_save(flags);
-        __flush_cache_4096(start | SH_CACHE_ASSOC,
-                           P1SEGADDR(phys), exec_offset);
+        __flush_cache_one(start | SH_CACHE_ASSOC, P1SEGADDR(phys), exec_offset);
         local_irq_restore(flags);
 }
 
@@ -129,8 +130,8 @@ static void sh4_flush_dcache_page(void *arg)
 
                 /* Loop all the D-cache */
                 n = boot_cpu_data.dcache.n_aliases;
-                for (i = 0; i < n; i++, addr += 4096)
-                        flush_cache_4096(addr, phys);
+                for (i = 0; i < n; i++, addr += PAGE_SIZE)
+                        flush_cache_one(addr, phys);
         }
 
         wmb();
@@ -318,11 +319,11 @@ static void sh4_flush_cache_page(void *args)
         /* We only need to flush D-cache when we have alias */
         if ((address^phys) & alias_mask) {
                 /* Loop 4K of the D-cache */
-                flush_cache_4096(
+                flush_cache_one(
                         CACHE_OC_ADDRESS_ARRAY | (address & alias_mask),
                         phys);
                 /* Loop another 4K of the D-cache */
-                flush_cache_4096(
+                flush_cache_one(
                         CACHE_OC_ADDRESS_ARRAY | (phys & alias_mask),
                         phys);
         }
@@ -337,7 +338,7 @@ static void sh4_flush_cache_page(void *args)
                  * kernel has never executed the code through its identity
                  * translation.
                  */
-                flush_cache_4096(
+                flush_cache_one(
                         CACHE_IC_ADDRESS_ARRAY | (address & alias_mask),
                         phys);
         }
@@ -393,7 +394,7 @@ static void sh4_flush_cache_range(void *args)
 }
 
 /**
- * __flush_cache_4096
+ * __flush_cache_one
  *
  * @addr:  address in memory mapped cache array
  * @phys:  P1 address to flush (has to match tags if addr has 'A' bit
@@ -406,7 +407,7 @@ static void sh4_flush_cache_range(void *args)
  * operation (purge/write-back) is selected by the lower 2 bits of
  * 'phys'.
  */
-static void __flush_cache_4096(unsigned long addr, unsigned long phys,
+static void __flush_cache_one(unsigned long addr, unsigned long phys,
                                unsigned long exec_offset)
 {
         int way_count;
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index 5e1091be9dc4..a2dc7f9ecc51 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -265,6 +265,8 @@ static void __init emit_cache_params(void)
 
 void __init cpu_cache_init(void)
 {
+        unsigned int cache_disabled = !(__raw_readl(CCR) & CCR_CACHE_ENABLE);
+
         compute_alias(&boot_cpu_data.icache);
         compute_alias(&boot_cpu_data.dcache);
         compute_alias(&boot_cpu_data.scache);
@@ -273,6 +275,13 @@ void __init cpu_cache_init(void)
         __flush_purge_region            = noop__flush_region;
         __flush_invalidate_region       = noop__flush_region;
 
+        /*
+         * No flushing is necessary in the disabled cache case so we can
+         * just keep the noop functions in local_flush_..() and __flush_..()
+         */
+        if (unlikely(cache_disabled))
+                goto skip;
+
         if (boot_cpu_data.family == CPU_FAMILY_SH2) {
                 extern void __weak sh2_cache_init(void);
 
@@ -312,5 +321,6 @@ void __init cpu_cache_init(void)
                 sh5_cache_init();
         }
 
+skip:
         emit_cache_params();
 }