12 files changed, 96 insertions, 36 deletions

diff --git a/arch/sh/mm/consistent.c b/arch/sh/mm/consistent.c
index 902967e3f841..c86a08540258 100644
--- a/arch/sh/mm/consistent.c
+++ b/arch/sh/mm/consistent.c
@@ -16,6 +16,7 @@
 #include <linux/dma-debug.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/gfp.h>
 #include <asm/cacheflush.h>
 #include <asm/addrspace.h>
 
diff --git a/arch/sh/mm/hugetlbpage.c b/arch/sh/mm/hugetlbpage.c
index 9304117039c4..9163db3e8d15 100644
--- a/arch/sh/mm/hugetlbpage.c
+++ b/arch/sh/mm/hugetlbpage.c
@@ -13,7 +13,6 @@
 #include <linux/mm.h>
 #include <linux/hugetlb.h>
 #include <linux/pagemap.h>
-#include <linux/slab.h>
 #include <linux/sysctl.h>
 
 #include <asm/mman.h>
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 68028e8f26ce..c505de61a5ca 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -10,6 +10,7 @@
 #include <linux/mm.h>
 #include <linux/swap.h>
 #include <linux/init.h>
+#include <linux/gfp.h>
 #include <linux/bootmem.h>
 #include <linux/proc_fs.h>
 #include <linux/pagemap.h>
diff --git a/arch/sh/mm/ioremap.c b/arch/sh/mm/ioremap.c
index 1ab2385ecefe..0c99ec2e7ed8 100644
--- a/arch/sh/mm/ioremap.c
+++ b/arch/sh/mm/ioremap.c
@@ -14,6 +14,7 @@
  */
 #include <linux/vmalloc.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <linux/mm.h>
 #include <linux/pci.h>
 #include <linux/io.h>
diff --git a/arch/sh/mm/ioremap_fixed.c b/arch/sh/mm/ioremap_fixed.c
index 7f682e5dafcf..efbe84af9983 100644
--- a/arch/sh/mm/ioremap_fixed.c
+++ b/arch/sh/mm/ioremap_fixed.c
@@ -15,7 +15,6 @@
 #include <linux/io.h>
 #include <linux/bootmem.h>
 #include <linux/proc_fs.h>
-#include <linux/slab.h>
 #include <asm/fixmap.h>
 #include <asm/page.h>
 #include <asm/pgalloc.h>
diff --git a/arch/sh/mm/pgtable.c b/arch/sh/mm/pgtable.c
index 6f21fb1d8726..26e03a1f7ca4 100644
--- a/arch/sh/mm/pgtable.c
+++ b/arch/sh/mm/pgtable.c
@@ -1,4 +1,5 @@
 #include <linux/mm.h>
+#include <linux/slab.h>
 
 #define PGALLOC_GFP GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO
 
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index 3cc21933063b..e43ec600afcf 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -15,7 +15,6 @@
 #include <linux/sysdev.h>
 #include <linux/cpu.h>
 #include <linux/module.h>
-#include <linux/slab.h>
 #include <linux/bitops.h>
 #include <linux/debugfs.h>
 #include <linux/fs.h>
diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c
index bdd0982b56ee..b71db6af8060 100644
--- a/arch/sh/mm/tlb-pteaex.c
+++ b/arch/sh/mm/tlb-pteaex.c
@@ -77,3 +77,31 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
         __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
         back_to_cached();
 }
+
+void local_flush_tlb_all(void)
+{
+        unsigned long flags, status;
+        int i;
+
+        /*
+         * Flush all the TLB.
+         */
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        status = __raw_readl(MMUCR);
+        status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
+
+        if (status == 0)
+                status = MMUCR_URB_NENTRIES;
+
+        for (i = 0; i < status; i++)
+                __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
+
+        for (i = 0; i < 4; i++)
+                __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
+
+        back_to_cached();
+        ctrl_barrier();
+        local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c
index 4f5f7cbdd508..7a940dbfc2e9 100644
--- a/arch/sh/mm/tlb-sh3.c
+++ b/arch/sh/mm/tlb-sh3.c
@@ -77,3 +77,22 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
         for (i = 0; i < ways; i++)
                 __raw_writel(data, addr + (i << 8));
 }
+
+void local_flush_tlb_all(void)
+{
+        unsigned long flags, status;
+
+        /*
+         * Flush all the TLB.
+         *
+         * Write to the MMU control register's bit:
+         *      TF-bit for SH-3, TI-bit for SH-4.
+         *      It's same position, bit #2.
+         */
+        local_irq_save(flags);
+        status = __raw_readl(MMUCR);
+        status |= 0x04;
+        __raw_writel(status, MMUCR);
+        ctrl_barrier();
+        local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c
index ccac77f504a8..cfdf7930d294 100644
--- a/arch/sh/mm/tlb-sh4.c
+++ b/arch/sh/mm/tlb-sh4.c
@@ -80,3 +80,31 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
         __raw_writel(data, addr);
         back_to_cached();
 }
+
+void local_flush_tlb_all(void)
+{
+        unsigned long flags, status;
+        int i;
+
+        /*
+         * Flush all the TLB.
+         */
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        status = __raw_readl(MMUCR);
+        status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
+
+        if (status == 0)
+                status = MMUCR_URB_NENTRIES;
+
+        for (i = 0; i < status; i++)
+                __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
+
+        for (i = 0; i < 4; i++)
+                __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
+
+        back_to_cached();
+        ctrl_barrier();
+        local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlb-urb.c b/arch/sh/mm/tlb-urb.c
index bb5b9098956d..c92ce20db39b 100644
--- a/arch/sh/mm/tlb-urb.c
+++ b/arch/sh/mm/tlb-urb.c
@@ -24,13 +24,9 @@ void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
 
         local_irq_save(flags);
 
-        /* Load the entry into the TLB */
-        __update_tlb(vma, addr, pte);
-
-        /* ... and wire it up. */
         status = __raw_readl(MMUCR);
         urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
-        status &= ~MMUCR_URB;
+        status &= ~MMUCR_URC;
 
         /*
          * Make sure we're not trying to wire the last TLB entry slot.
@@ -39,7 +35,23 @@ void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
 
         urb = urb % MMUCR_URB_NENTRIES;
 
+        /*
+         * Insert this entry into the highest non-wired TLB slot (via
+         * the URC field).
+         */
+        status |= (urb << MMUCR_URC_SHIFT);
+        __raw_writel(status, MMUCR);
+        ctrl_barrier();
+
+        /* Load the entry into the TLB */
+        __update_tlb(vma, addr, pte);
+
+        /* ... and wire it up. */
+        status = __raw_readl(MMUCR);
+
+        status &= ~MMUCR_URB;
         status |= (urb << MMUCR_URB_SHIFT);
+
         __raw_writel(status, MMUCR);
         ctrl_barrier();
 
diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c
index 77dc5efa7127..3fbe03ce8fe3 100644
--- a/arch/sh/mm/tlbflush_32.c
+++ b/arch/sh/mm/tlbflush_32.c
@@ -119,31 +119,3 @@ void local_flush_tlb_mm(struct mm_struct *mm)
                 local_irq_restore(flags);
         }
 }
-
-void local_flush_tlb_all(void)
-{
-        unsigned long flags, status;
-        int i;
-
-        /*
-         * Flush all the TLB.
-         */
-        local_irq_save(flags);
-        jump_to_uncached();
-
-        status = __raw_readl(MMUCR);
-        status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
-
-        if (status == 0)
-                status = MMUCR_URB_NENTRIES;
-
-        for (i = 0; i < status; i++)
-                __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
-
-        for (i = 0; i < 4; i++)
-                __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
-
-        back_to_cached();
-        ctrl_barrier();
-        local_irq_restore(flags);
-}