13 files changed, 277 insertions, 166 deletions

diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 5fd218430b19..9c131cac91a4 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -145,25 +145,39 @@ choice
 
 config PAGE_SIZE_4KB
         bool "4kB"
-        depends on !X2TLB
+        depends on !MMU || !X2TLB
         help
           This is the default page size used by all SuperH CPUs.
 
 config PAGE_SIZE_8KB
         bool "8kB"
-        depends on X2TLB
+        depends on !MMU || X2TLB
         help
           This enables 8kB pages as supported by SH-X2 and later MMUs.
 
+config PAGE_SIZE_16KB
+        bool "16kB"
+        depends on !MMU
+        help
+          This enables 16kB pages on MMU-less SH systems.
+
 config PAGE_SIZE_64KB
         bool "64kB"
-        depends on CPU_SH4 || CPU_SH5
+        depends on !MMU || CPU_SH4 || CPU_SH5
         help
           This enables support for 64kB pages, possible on all SH-4
           CPUs and later.
 
 endchoice
 
+config ENTRY_OFFSET
+        hex
+        default "0x00001000" if PAGE_SIZE_4KB
+        default "0x00002000" if PAGE_SIZE_8KB
+        default "0x00004000" if PAGE_SIZE_16KB
+        default "0x00010000" if PAGE_SIZE_64KB
+        default "0x00000000"
+
 choice
         prompt "HugeTLB page size"
         depends on HUGETLB_PAGE && (CPU_SH4 || CPU_SH5) && MMU
@@ -223,7 +237,6 @@ choice
 
 config CACHE_WRITEBACK
         bool "Write-back"
-        depends on CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
 
 config CACHE_WRITETHROUGH
         bool "Write-through"
diff --git a/arch/sh/mm/Makefile_32 b/arch/sh/mm/Makefile_32
index e295db60b91b..70e0906023cc 100644
--- a/arch/sh/mm/Makefile_32
+++ b/arch/sh/mm/Makefile_32
@@ -5,12 +5,15 @@
 obj-y                   := init.o extable_32.o consistent.o
 
 ifndef CONFIG_CACHE_OFF
-obj-$(CONFIG_CPU_SH2)           += cache-sh2.o
-obj-$(CONFIG_CPU_SH3)           += cache-sh3.o
-obj-$(CONFIG_CPU_SH4)           += cache-sh4.o
-obj-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o
+cache-$(CONFIG_CPU_SH2)         := cache-sh2.o
+cache-$(CONFIG_CPU_SH2A)        := cache-sh2a.o
+cache-$(CONFIG_CPU_SH3)         := cache-sh3.o
+cache-$(CONFIG_CPU_SH4)         := cache-sh4.o
+cache-$(CONFIG_SH7705_CACHE_32KB)       += cache-sh7705.o
 endif
 
+obj-y                   += $(cache-y)
+
 mmu-y                   := tlb-nommu.o pg-nommu.o
 mmu-$(CONFIG_MMU)       := fault_32.o tlbflush_32.o ioremap_32.o
 
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index c5b56d52b7d2..0e189ccd4a77 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -120,7 +120,7 @@ static const struct file_operations cache_debugfs_fops = {
         .open           = cache_debugfs_open,
         .read           = seq_read,
         .llseek         = seq_lseek,
-        .release        = seq_release,
+        .release        = single_release,
 };
 
 static int __init cache_debugfs_init(void)
diff --git a/arch/sh/mm/cache-sh2.c b/arch/sh/mm/cache-sh2.c
index 6614033f6be9..c4e80d2b764b 100644
--- a/arch/sh/mm/cache-sh2.c
+++ b/arch/sh/mm/cache-sh2.c
@@ -2,6 +2,7 @@
  * arch/sh/mm/cache-sh2.c
  *
  * Copyright (C) 2002 Paul Mundt
+ * Copyright (C) 2008 Yoshinori Sato
  *
  * Released under the terms of the GNU GPL v2.0.
  */
@@ -24,8 +25,15 @@ void __flush_wback_region(void *start, int size)
         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
                 & ~(L1_CACHE_BYTES-1);
         for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                /* FIXME cache purge */
-                ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
+                unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0);
+                int way;
+                for (way = 0; way < 4; way++) {
+                        unsigned long data =  ctrl_inl(addr | (way << 12));
+                        if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
+                                data &= ~SH_CACHE_UPDATED;
+                                ctrl_outl(data, addr | (way << 12));
+                        }
+                }
         }
 }
 
@@ -37,21 +45,40 @@ void __flush_purge_region(void *start, int size)
         begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
                 & ~(L1_CACHE_BYTES-1);
-        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
-        }
+
+        for (v = begin; v < end; v+=L1_CACHE_BYTES)
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
 }
 
 void __flush_invalidate_region(void *start, int size)
 {
+#ifdef CONFIG_CACHE_WRITEBACK
+        /*
+         * SH-2 does not support individual line invalidation, only a
+         * global invalidate.
+         */
+        unsigned long ccr;
+        unsigned long flags;
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        ccr = ctrl_inl(CCR);
+        ccr |= CCR_CACHE_INVALIDATE;
+        ctrl_outl(ccr, CCR);
+
+        back_to_cached();
+        local_irq_restore(flags);
+#else
         unsigned long v;
         unsigned long begin, end;
 
         begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
                 & ~(L1_CACHE_BYTES-1);
-        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
-        }
-}
 
+        for (v = begin; v < end; v+=L1_CACHE_BYTES)
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
+#endif
+}
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
new file mode 100644
index 000000000000..62c0c5f35120
--- /dev/null
+++ b/arch/sh/mm/cache-sh2a.c
@@ -0,0 +1,129 @@
+/*
+ * arch/sh/mm/cache-sh2a.c
+ *
+ * Copyright (C) 2008 Yoshinori Sato
+ *
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+
+#include <asm/cache.h>
+#include <asm/addrspace.h>
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+
+void __flush_wback_region(void *start, int size)
+{
+        unsigned long v;
+        unsigned long begin, end;
+        unsigned long flags;
+
+        begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
+        end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+                & ~(L1_CACHE_BYTES-1);
+
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0);
+                int way;
+                for (way = 0; way < 4; way++) {
+                        unsigned long data =  ctrl_inl(addr | (way << 11));
+                        if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
+                                data &= ~SH_CACHE_UPDATED;
+                                ctrl_outl(data, addr | (way << 11));
+                        }
+                }
+        }
+
+        back_to_cached();
+        local_irq_restore(flags);
+}
+
+void __flush_purge_region(void *start, int size)
+{
+        unsigned long v;
+        unsigned long begin, end;
+        unsigned long flags;
+
+        begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
+        end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+                & ~(L1_CACHE_BYTES-1);
+
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
+        }
+        back_to_cached();
+        local_irq_restore(flags);
+}
+
+void __flush_invalidate_region(void *start, int size)
+{
+        unsigned long v;
+        unsigned long begin, end;
+        unsigned long flags;
+
+        begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
+        end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+                & ~(L1_CACHE_BYTES-1);
+        local_irq_save(flags);
+        jump_to_uncached();
+
+#ifdef CONFIG_CACHE_WRITEBACK
+        ctrl_outl(ctrl_inl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
+        /* I-cache invalidate */
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
+        }
+#else
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
+        }
+#endif
+        back_to_cached();
+        local_irq_restore(flags);
+}
+
+/* WBack O-Cache and flush I-Cache */
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+        unsigned long v;
+        unsigned long flags;
+
+        start = start & ~(L1_CACHE_BYTES-1);
+        end = (end + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);
+
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        for (v = start; v < end; v+=L1_CACHE_BYTES) {
+                unsigned long addr = (v & 0x000007f0);
+                int way;
+                /* O-Cache writeback */
+                for (way = 0; way < 4; way++) {
+                        unsigned long data =  ctrl_inl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
+                        if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
+                                data &= ~SH_CACHE_UPDATED;
+                                ctrl_outl(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
+                        }
+                }
+                /* I-Cache invalidate */
+                ctrl_outl(addr,
+                          CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008);
+        }
+
+        back_to_cached();
+        local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 43d7ff6b6ec7..1fdc8d90254a 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -4,6 +4,7 @@
  * Copyright (C) 1999, 2000, 2002  Niibe Yutaka
  * Copyright (C) 2001 - 2007  Paul Mundt
  * Copyright (C) 2003  Richard Curnow
+ * Copyright (c) 2007 STMicroelectronics (R&D) Ltd.
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -22,6 +23,7 @@
  * entirety.
  */
 #define MAX_DCACHE_PAGES        64      /* XXX: Tune for ways */
+#define MAX_ICACHE_PAGES        32
 
 static void __flush_dcache_segment_1way(unsigned long start,
                                         unsigned long extent);
@@ -178,42 +180,45 @@ void __flush_invalidate_region(void *start, int size)
 /*
  * Write back the range of D-cache, and purge the I-cache.
  *
- * Called from kernel/module.c:sys_init_module and routine for a.out format.
+ * Called from kernel/module.c:sys_init_module and routine for a.out format,
+ * signal handler code and kprobes code
  */
 void flush_icache_range(unsigned long start, unsigned long end)
 {
-        flush_cache_all();
-}
-
-/*
- * Write back the D-cache and purge the I-cache for signal trampoline.
- * .. which happens to be the same behavior as flush_icache_range().
- * So, we simply flush out a line.
- */
-void __uses_jump_to_uncached flush_cache_sigtramp(unsigned long addr)
-{
-        unsigned long v, index;
-        unsigned long flags;
+        int icacheaddr;
+        unsigned long flags, v;
         int i;
 
-        v = addr & ~(L1_CACHE_BYTES-1);
-        asm volatile("ocbwb     %0"
-                     : /* no output */
-                     : "m" (__m(v)));
-
-        index = CACHE_IC_ADDRESS_ARRAY |
-                        (v & boot_cpu_data.icache.entry_mask);
-
-        local_irq_save(flags);
-        jump_to_uncached();
-
-        for (i = 0; i < boot_cpu_data.icache.ways;
-             i++, index += boot_cpu_data.icache.way_incr)
-                ctrl_outl(0, index);    /* Clear out Valid-bit */
-
-        back_to_cached();
-        wmb();
-        local_irq_restore(flags);
+       /* If there are too many pages then just blow the caches */
+        if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
+                flush_cache_all();
+       } else {
+               /* selectively flush d-cache then invalidate the i-cache */
+               /* this is inefficient, so only use for small ranges */
+               start &= ~(L1_CACHE_BYTES-1);
+               end += L1_CACHE_BYTES-1;
+               end &= ~(L1_CACHE_BYTES-1);
+
+               local_irq_save(flags);
+               jump_to_uncached();
+
+               for (v = start; v < end; v+=L1_CACHE_BYTES) {
+                       asm volatile("ocbwb     %0"
+                                    : /* no output */
+                                    : "m" (__m(v)));
+
+                       icacheaddr = CACHE_IC_ADDRESS_ARRAY | (
+                                       v & cpu_data->icache.entry_mask);
+
+                       for (i = 0; i < cpu_data->icache.ways;
+                               i++, icacheaddr += cpu_data->icache.way_incr)
+                                       /* Clear i-cache line valid-bit */
+                                       ctrl_outl(0, icacheaddr);
+               }
+
+                back_to_cached();
+                local_irq_restore(flags);
+        }
 }
 
 static inline void flush_cache_4096(unsigned long start,
diff --git a/arch/sh/mm/consistent.c b/arch/sh/mm/consistent.c
index d3c33fc5b1c2..b2ce014401b5 100644
--- a/arch/sh/mm/consistent.c
+++ b/arch/sh/mm/consistent.c
@@ -10,6 +10,7 @@
  * for more details.
  */
 #include <linux/mm.h>
+#include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <asm/cacheflush.h>
 #include <asm/addrspace.h>
@@ -27,21 +28,10 @@ void *dma_alloc_coherent(struct device *dev, size_t size,
                            dma_addr_t *dma_handle, gfp_t gfp)
 {
         void *ret, *ret_nocache;
-        struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
         int order = get_order(size);
 
-        if (mem) {
-                int page = bitmap_find_free_region(mem->bitmap, mem->size,
-                                                     order);
-                if (page >= 0) {
-                        *dma_handle = mem->device_base + (page << PAGE_SHIFT);
-                        ret = mem->virt_base + (page << PAGE_SHIFT);
-                        memset(ret, 0, size);
-                        return ret;
-                }
-                if (mem->flags & DMA_MEMORY_EXCLUSIVE)
-                        return NULL;
-        }
+        if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
+                return ret;
 
         ret = (void *)__get_free_pages(gfp, order);
         if (!ret)
@@ -71,11 +61,7 @@ void dma_free_coherent(struct device *dev, size_t size,
         struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
         int order = get_order(size);
 
-        if (mem && vaddr >= mem->virt_base && vaddr < (mem->virt_base + (mem->size << PAGE_SHIFT))) {
-                int page = (vaddr - mem->virt_base) >> PAGE_SHIFT;
-
-                bitmap_release_region(mem->bitmap, page, order);
-        } else {
+        if (!dma_release_from_coherent(dev, order, vaddr)) {
                 WARN_ON(irqs_disabled());       /* for portability */
                 BUG_ON(mem && mem->flags & DMA_MEMORY_EXCLUSIVE);
                 free_pages((unsigned long)phys_to_virt(dma_handle), order);
@@ -84,83 +70,6 @@ void dma_free_coherent(struct device *dev, size_t size,
 }
 EXPORT_SYMBOL(dma_free_coherent);
 
-int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
-                                dma_addr_t device_addr, size_t size, int flags)
-{
-        void __iomem *mem_base = NULL;
-        int pages = size >> PAGE_SHIFT;
-        int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
-
-        if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0)
-                goto out;
-        if (!size)
-                goto out;
-        if (dev->dma_mem)
-                goto out;
-
-        /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */
-
-        mem_base = ioremap_nocache(bus_addr, size);
-        if (!mem_base)
-                goto out;
-
-        dev->dma_mem = kmalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
-        if (!dev->dma_mem)
-                goto out;
-        dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
-        if (!dev->dma_mem->bitmap)
-                goto free1_out;
-
-        dev->dma_mem->virt_base = mem_base;
-        dev->dma_mem->device_base = device_addr;
-        dev->dma_mem->size = pages;
-        dev->dma_mem->flags = flags;
-
-        if (flags & DMA_MEMORY_MAP)
-                return DMA_MEMORY_MAP;
-
-        return DMA_MEMORY_IO;
-
- free1_out:
-        kfree(dev->dma_mem);
- out:
-        if (mem_base)
-                iounmap(mem_base);
-        return 0;
-}
-EXPORT_SYMBOL(dma_declare_coherent_memory);
-
-void dma_release_declared_memory(struct device *dev)
-{
-        struct dma_coherent_mem *mem = dev->dma_mem;
-
-        if (!mem)
-                return;
-        dev->dma_mem = NULL;
-        iounmap(mem->virt_base);
-        kfree(mem->bitmap);
-        kfree(mem);
-}
-EXPORT_SYMBOL(dma_release_declared_memory);
-
-void *dma_mark_declared_memory_occupied(struct device *dev,
-                                        dma_addr_t device_addr, size_t size)
-{
-        struct dma_coherent_mem *mem = dev->dma_mem;
-        int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1) >> PAGE_SHIFT;
-        int pos, err;
-
-        if (!mem)
-                return ERR_PTR(-EINVAL);
-
-        pos = (device_addr - mem->device_base) >> PAGE_SHIFT;
-        err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages));
-        if (err != 0)
-                return ERR_PTR(err);
-        return mem->virt_base + (pos << PAGE_SHIFT);
-}
-EXPORT_SYMBOL(dma_mark_declared_memory_occupied);
-
 void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                     enum dma_data_direction direction)
 {
@@ -185,3 +94,32 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
         }
 }
 EXPORT_SYMBOL(dma_cache_sync);
+
+int platform_resource_setup_memory(struct platform_device *pdev,
+                                   char *name, unsigned long memsize)
+{
+        struct resource *r;
+        dma_addr_t dma_handle;
+        void *buf;
+
+        r = pdev->resource + pdev->num_resources - 1;
+        if (r->flags) {
+                pr_warning("%s: unable to find empty space for resource\n",
+                        name);
+                return -EINVAL;
+        }
+
+        buf = dma_alloc_coherent(NULL, memsize, &dma_handle, GFP_KERNEL);
+        if (!buf) {
+                pr_warning("%s: unable to allocate memory\n", name);
+                return -ENOMEM;
+        }
+
+        memset(buf, 0, memsize);
+
+        r->flags = IORESOURCE_MEM;
+        r->start = dma_handle;
+        r->end = r->start + memsize - 1;
+        r->name = name;
+        return 0;
+}
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index d1fa27594c6e..0c776fdfbdda 100644
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -37,16 +37,12 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
         int fault;
         siginfo_t info;
 
-        trace_hardirqs_on();
-        local_irq_enable();
-
 #ifdef CONFIG_SH_KGDB
         if (kgdb_nofault && kgdb_bus_err_hook)
                 kgdb_bus_err_hook();
 #endif
 
         tsk = current;
-        mm = tsk->mm;
         si_code = SEGV_MAPERR;
 
         if (unlikely(address >= TASK_SIZE)) {
@@ -88,6 +84,14 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
                 return;
         }
 
+        /* Only enable interrupts if they were on before the fault */
+        if ((regs->sr & SR_IMASK) != SR_IMASK) {
+                trace_hardirqs_on();
+                local_irq_enable();
+        }
+
+        mm = tsk->mm;
+
         /*
          * If we're in an interrupt or have no user
          * context, we must not take the fault..
diff --git a/arch/sh/mm/fault_64.c b/arch/sh/mm/fault_64.c
index 399d53710d2f..bd63b961b2a9 100644
--- a/arch/sh/mm/fault_64.c
+++ b/arch/sh/mm/fault_64.c
@@ -39,7 +39,7 @@
 #include <asm/uaccess.h>
 #include <asm/pgalloc.h>
 #include <asm/mmu_context.h>
-#include <asm/cpu/registers.h>
+#include <cpu/registers.h>
 
 /* Callable from fault.c, so not static */
 inline void __do_tlb_refill(unsigned long address,
diff --git a/arch/sh/mm/pg-sh4.c b/arch/sh/mm/pg-sh4.c
index 8c7a9ca79879..38870e0fc182 100644
--- a/arch/sh/mm/pg-sh4.c
+++ b/arch/sh/mm/pg-sh4.c
@@ -111,7 +111,7 @@ EXPORT_SYMBOL(copy_user_highpage);
 /*
  * For SH-4, we have our own implementation for ptep_get_and_clear
  */
-inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
         pte_t pte = *ptep;
 
diff --git a/arch/sh/mm/pg-sh7705.c b/arch/sh/mm/pg-sh7705.c
index 7f885b7f8aff..eaf25147194c 100644
--- a/arch/sh/mm/pg-sh7705.c
+++ b/arch/sh/mm/pg-sh7705.c
@@ -118,7 +118,7 @@ void copy_user_page(void *to, void *from, unsigned long address, struct page *pg
  * For SH7705, we have our own implementation for ptep_get_and_clear
  * Copied from pg-sh4.c
  */
-inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
         pte_t pte = *ptep;
 
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index 46911bcbf17b..cef727669c87 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -385,7 +385,7 @@ static const struct file_operations pmb_debugfs_fops = {
         .open           = pmb_debugfs_open,
         .read           = seq_read,
         .llseek         = seq_lseek,
-        .release        = seq_release,
+        .release        = single_release,
 };
 
 static int __init pmb_debugfs_init(void)
diff --git a/arch/sh/mm/tlb-sh5.c b/arch/sh/mm/tlb-sh5.c
index f34274a1ded3..dae131243bcc 100644
--- a/arch/sh/mm/tlb-sh5.c
+++ b/arch/sh/mm/tlb-sh5.c
@@ -15,9 +15,7 @@
 #include <asm/mmu_context.h>
 
 /**
- * sh64_tlb_init
- *
- * Perform initial setup for the DTLB and ITLB.
+ * sh64_tlb_init - Perform initial setup for the DTLB and ITLB.
  */
 int __init sh64_tlb_init(void)
 {
@@ -46,9 +44,7 @@ int __init sh64_tlb_init(void)
 }
 
 /**
- * sh64_next_free_dtlb_entry
- *
- * Find the next available DTLB entry
+ * sh64_next_free_dtlb_entry - Find the next available DTLB entry
  */
 unsigned long long sh64_next_free_dtlb_entry(void)
 {
@@ -56,9 +52,7 @@ unsigned long long sh64_next_free_dtlb_entry(void)
 }
 
 /**
- * sh64_get_wired_dtlb_entry
- *
- * Allocate a wired (locked-in) entry in the DTLB
+ * sh64_get_wired_dtlb_entry - Allocate a wired (locked-in) entry in the DTLB
  */
 unsigned long long sh64_get_wired_dtlb_entry(void)
 {
@@ -71,12 +65,10 @@ unsigned long long sh64_get_wired_dtlb_entry(void)
 }
 
 /**
- * sh64_put_wired_dtlb_entry
+ * sh64_put_wired_dtlb_entry - Free a wired (locked-in) entry in the DTLB.
  *
  * @entry:      Address of TLB slot.
  *
- * Free a wired (locked-in) entry in the DTLB.
- *
  * Works like a stack, last one to allocate must be first one to free.
  */
 int sh64_put_wired_dtlb_entry(unsigned long long entry)
@@ -115,7 +107,7 @@ int sh64_put_wired_dtlb_entry(unsigned long long entry)
 }
 
 /**
- * sh64_setup_tlb_slot
+ * sh64_setup_tlb_slot - Load up a translation in a wired slot.
  *
  * @config_addr:        Address of TLB slot.
  * @eaddr:              Virtual address.
@@ -154,7 +146,7 @@ inline void sh64_setup_tlb_slot(unsigned long long config_addr,
 }
 
 /**
- * sh64_teardown_tlb_slot
+ * sh64_teardown_tlb_slot - Teardown a translation.
  *
  * @config_addr:        Address of TLB slot.
  *