10 files changed, 52 insertions, 52 deletions

diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index 48ce82ee9fd2..690ed010d002 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -36,7 +36,7 @@ static int cache_seq_show(struct seq_file *file, void *iter)
          */
         jump_to_uncached();
 
-        ccr = ctrl_inl(CCR);
+        ccr = __raw_readl(CCR);
         if ((ccr & CCR_CACHE_ENABLE) == 0) {
                 back_to_cached();
 
@@ -89,7 +89,7 @@ static int cache_seq_show(struct seq_file *file, void *iter)
                 for (addr = addrstart, line = 0;
                      addr < addrstart + waysize;
                      addr += cache->linesz, line++) {
-                        unsigned long data = ctrl_inl(addr);
+                        unsigned long data = __raw_readl(addr);
 
                         /* Check the V bit, ignore invalid cachelines */
                         if ((data & 1) == 0)
diff --git a/arch/sh/mm/cache-sh2.c b/arch/sh/mm/cache-sh2.c
index 699a71f46327..defcf719f2e8 100644
--- a/arch/sh/mm/cache-sh2.c
+++ b/arch/sh/mm/cache-sh2.c
@@ -28,10 +28,10 @@ static void sh2__flush_wback_region(void *start, int size)
                 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0);
                 int way;
                 for (way = 0; way < 4; way++) {
-                        unsigned long data =  ctrl_inl(addr | (way << 12));
+                        unsigned long data =  __raw_readl(addr | (way << 12));
                         if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
                                 data &= ~SH_CACHE_UPDATED;
-                                ctrl_outl(data, addr | (way << 12));
+                                __raw_writel(data, addr | (way << 12));
                         }
                 }
         }
@@ -47,7 +47,7 @@ static void sh2__flush_purge_region(void *start, int size)
                 & ~(L1_CACHE_BYTES-1);
 
         for (v = begin; v < end; v+=L1_CACHE_BYTES)
-                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                __raw_writel((v & CACHE_PHYSADDR_MASK),
                           CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
 }
 
@@ -63,9 +63,9 @@ static void sh2__flush_invalidate_region(void *start, int size)
         local_irq_save(flags);
         jump_to_uncached();
 
-        ccr = ctrl_inl(CCR);
+        ccr = __raw_readl(CCR);
         ccr |= CCR_CACHE_INVALIDATE;
-        ctrl_outl(ccr, CCR);
+        __raw_writel(ccr, CCR);
 
         back_to_cached();
         local_irq_restore(flags);
@@ -78,7 +78,7 @@ static void sh2__flush_invalidate_region(void *start, int size)
                 & ~(L1_CACHE_BYTES-1);
 
         for (v = begin; v < end; v+=L1_CACHE_BYTES)
-                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                __raw_writel((v & CACHE_PHYSADDR_MASK),
                           CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
 #endif
 }
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
index 975899d83564..1f51225426a2 100644
--- a/arch/sh/mm/cache-sh2a.c
+++ b/arch/sh/mm/cache-sh2a.c
@@ -32,10 +32,10 @@ static void sh2a__flush_wback_region(void *start, int size)
                 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0);
                 int way;
                 for (way = 0; way < 4; way++) {
-                        unsigned long data =  ctrl_inl(addr | (way << 11));
+                        unsigned long data =  __raw_readl(addr | (way << 11));
                         if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
                                 data &= ~SH_CACHE_UPDATED;
-                                ctrl_outl(data, addr | (way << 11));
+                                __raw_writel(data, addr | (way << 11));
                         }
                 }
         }
@@ -58,7 +58,7 @@ static void sh2a__flush_purge_region(void *start, int size)
         jump_to_uncached();
 
         for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                __raw_writel((v & CACHE_PHYSADDR_MASK),
                           CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
         }
         back_to_cached();
@@ -78,17 +78,17 @@ static void sh2a__flush_invalidate_region(void *start, int size)
         jump_to_uncached();
 
 #ifdef CONFIG_CACHE_WRITEBACK
-        ctrl_outl(ctrl_inl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
+        __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
         /* I-cache invalidate */
         for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                __raw_writel((v & CACHE_PHYSADDR_MASK),
                           CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
         }
 #else
         for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                __raw_writel((v & CACHE_PHYSADDR_MASK),
                           CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
-                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                __raw_writel((v & CACHE_PHYSADDR_MASK),
                           CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
         }
 #endif
@@ -115,14 +115,14 @@ static void sh2a_flush_icache_range(void *args)
                 int way;
                 /* O-Cache writeback */
                 for (way = 0; way < 4; way++) {
-                        unsigned long data =  ctrl_inl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
+                        unsigned long data =  __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
                         if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
                                 data &= ~SH_CACHE_UPDATED;
-                                ctrl_outl(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
+                                __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
                         }
                 }
                 /* I-Cache invalidate */
-                ctrl_outl(addr,
+                __raw_writel(addr,
                           CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008);
         }
 
diff --git a/arch/sh/mm/cache-sh3.c b/arch/sh/mm/cache-sh3.c
index faef80c98134..e37523f65195 100644
--- a/arch/sh/mm/cache-sh3.c
+++ b/arch/sh/mm/cache-sh3.c
@@ -50,12 +50,12 @@ static void sh3__flush_wback_region(void *start, int size)
                         p = __pa(v);
                         addr = addrstart | (v & current_cpu_data.dcache.entry_mask);
                         local_irq_save(flags);
-                        data = ctrl_inl(addr);
+                        data = __raw_readl(addr);
 
                         if ((data & CACHE_PHYSADDR_MASK) ==
                             (p & CACHE_PHYSADDR_MASK)) {
                                 data &= ~SH_CACHE_UPDATED;
-                                ctrl_outl(data, addr);
+                                __raw_writel(data, addr);
                                 local_irq_restore(flags);
                                 break;
                         }
@@ -86,7 +86,7 @@ static void sh3__flush_purge_region(void *start, int size)
                 data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */
                 addr = CACHE_OC_ADDRESS_ARRAY |
                         (v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC;
-                ctrl_outl(data, addr);
+                __raw_writel(data, addr);
         }
 }
 
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 87115b3ee70e..2cfae81914aa 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -132,9 +132,9 @@ static void flush_icache_all(void)
         jump_to_uncached();
 
         /* Flush I-cache */
-        ccr = ctrl_inl(CCR);
+        ccr = __raw_readl(CCR);
         ccr |= CCR_CACHE_ICI;
-        ctrl_outl(ccr, CCR);
+        __raw_writel(ccr, CCR);
 
         /*
          * back_to_cached() will take care of the barrier for us, don't add
@@ -377,9 +377,9 @@ extern void __weak sh4__flush_region_init(void);
 void __init sh4_cache_init(void)
 {
         printk("PVR=%08x CVR=%08x PRR=%08x\n",
-                ctrl_inl(CCN_PVR),
-                ctrl_inl(CCN_CVR),
-                ctrl_inl(CCN_PRR));
+                __raw_readl(CCN_PVR),
+                __raw_readl(CCN_CVR),
+                __raw_readl(CCN_PRR));
 
         local_flush_icache_range        = sh4_flush_icache_range;
         local_flush_dcache_page         = sh4_flush_dcache_page;
diff --git a/arch/sh/mm/cache-sh7705.c b/arch/sh/mm/cache-sh7705.c
index 870293ee539e..f498da1cce7a 100644
--- a/arch/sh/mm/cache-sh7705.c
+++ b/arch/sh/mm/cache-sh7705.c
@@ -48,10 +48,10 @@ static inline void cache_wback_all(void)
                         unsigned long data;
                         int v = SH_CACHE_UPDATED | SH_CACHE_VALID;
 
-                        data = ctrl_inl(addr);
+                        data = __raw_readl(addr);
 
                         if ((data & v) == v)
-                                ctrl_outl(data & ~v, addr);
+                                __raw_writel(data & ~v, addr);
 
                 }
 
@@ -115,10 +115,10 @@ static void __flush_dcache_page(unsigned long phys)
                      addr += current_cpu_data.dcache.linesz) {
                         unsigned long data;
 
-                        data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
+                        data = __raw_readl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
                         if (data == phys) {
                                 data &= ~(SH_CACHE_VALID | SH_CACHE_UPDATED);
-                                ctrl_outl(data, addr);
+                                __raw_writel(data, addr);
                         }
                 }
 
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index 3d5eece7e6d0..3c9bf5b5c36f 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -112,7 +112,7 @@ static void pmb_free(struct pmb_entry *pmbe)
 static void __set_pmb_entry(unsigned long vpn, unsigned long ppn,
                             unsigned long flags, int pos)
 {
-        ctrl_outl(vpn | PMB_V, mk_pmb_addr(pos));
+        __raw_writel(vpn | PMB_V, mk_pmb_addr(pos));
 
 #ifdef CONFIG_CACHE_WRITETHROUGH
         /*
@@ -124,7 +124,7 @@ static void __set_pmb_entry(unsigned long vpn, unsigned long ppn,
                 flags |= PMB_WT;
 #endif
 
-        ctrl_outl(ppn | flags | PMB_V, mk_pmb_data(pos));
+        __raw_writel(ppn | flags | PMB_V, mk_pmb_data(pos));
 }
 
 static void set_pmb_entry(struct pmb_entry *pmbe)
@@ -146,10 +146,10 @@ static void clear_pmb_entry(struct pmb_entry *pmbe)
 
         /* Clear V-bit */
         addr = mk_pmb_addr(entry);
-        ctrl_outl(ctrl_inl(addr) & ~PMB_V, addr);
+        __raw_writel(__raw_readl(addr) & ~PMB_V, addr);
 
         addr = mk_pmb_data(entry);
-        ctrl_outl(ctrl_inl(addr) & ~PMB_V, addr);
+        __raw_writel(__raw_readl(addr) & ~PMB_V, addr);
 
         back_to_cached();
 }
@@ -395,7 +395,7 @@ int pmb_init(void)
                 unsigned long vpn, ppn, flags;
 
                 addr = PMB_DATA + (i << PMB_E_SHIFT);
-                data = ctrl_inl(addr);
+                data = __raw_readl(addr);
                 if (!(data & PMB_V))
                         continue;
 
@@ -408,7 +408,7 @@ int pmb_init(void)
                         data &= ~(PMB_C | PMB_WT);
 #endif
                 }
-                ctrl_outl(data, addr);
+                __raw_writel(data, addr);
 
                 ppn = data & PMB_PFN_MASK;
 
@@ -416,7 +416,7 @@ int pmb_init(void)
                 flags |= data & PMB_SZ_MASK;
 
                 addr = PMB_ADDR + (i << PMB_E_SHIFT);
-                data = ctrl_inl(addr);
+                data = __raw_readl(addr);
 
                 vpn = data & PMB_PFN_MASK;
 
@@ -424,12 +424,12 @@ int pmb_init(void)
                 WARN_ON(IS_ERR(pmbe));
         }
 
-        ctrl_outl(0, PMB_IRMCR);
+        __raw_writel(0, PMB_IRMCR);
 
         /* Flush out the TLB */
-        i =  ctrl_inl(MMUCR);
+        i =  __raw_readl(MMUCR);
         i |= MMUCR_TI;
-        ctrl_outl(i, MMUCR);
+        __raw_writel(i, MMUCR);
 
         back_to_cached();
 
@@ -454,8 +454,8 @@ static int pmb_seq_show(struct seq_file *file, void *iter)
                 unsigned int size;
                 char *sz_str = NULL;
 
-                addr = ctrl_inl(mk_pmb_addr(i));
-                data = ctrl_inl(mk_pmb_data(i));
+                addr = __raw_readl(mk_pmb_addr(i));
+                data = __raw_readl(mk_pmb_data(i));
 
                 size = data & PMB_SZ_MASK;
                 sz_str = (size == PMB_SZ_16M)  ? " 16MB":
diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c
index ace8e6d2f59d..4f5f7cbdd508 100644
--- a/arch/sh/mm/tlb-sh3.c
+++ b/arch/sh/mm/tlb-sh3.c
@@ -41,14 +41,14 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 
         /* Set PTEH register */
         vpn = (address & MMU_VPN_MASK) | get_asid();
-        ctrl_outl(vpn, MMU_PTEH);
+        __raw_writel(vpn, MMU_PTEH);
 
         pteval = pte_val(pte);
 
         /* Set PTEL register */
         pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
         /* conveniently, we want all the software flags to be 0 anyway */
-        ctrl_outl(pteval, MMU_PTEL);
+        __raw_writel(pteval, MMU_PTEL);
 
         /* Load the TLB */
         asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
@@ -75,5 +75,5 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
         }
 
         for (i = 0; i < ways; i++)
-                ctrl_outl(data, addr + (i << 8));
+                __raw_writel(data, addr + (i << 8));
 }
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c
index 624c1daa9f3f..ccac77f504a8 100644
--- a/arch/sh/mm/tlb-sh4.c
+++ b/arch/sh/mm/tlb-sh4.c
@@ -29,7 +29,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 
         /* Set PTEH register */
         vpn = (address & MMU_VPN_MASK) | get_asid();
-        ctrl_outl(vpn, MMU_PTEH);
+        __raw_writel(vpn, MMU_PTEH);
 
         pteval = pte.pte_low;
 
@@ -41,13 +41,13 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
          * the protection bits (with the exception of the compat-mode SZ
          * and PR bits, which are cleared) being written out in PTEL.
          */
-        ctrl_outl(pte.pte_high, MMU_PTEA);
+        __raw_writel(pte.pte_high, MMU_PTEA);
 #else
         if (cpu_data->flags & CPU_HAS_PTEA) {
                 /* The last 3 bits and the first one of pteval contains
                  * the PTEA timing control and space attribute bits
                  */
-                ctrl_outl(copy_ptea_attributes(pteval), MMU_PTEA);
+                __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
         }
 #endif
 
@@ -57,7 +57,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
         pteval |= _PAGE_WT;
 #endif
         /* conveniently, we want all the software flags to be 0 anyway */
-        ctrl_outl(pteval, MMU_PTEL);
+        __raw_writel(pteval, MMU_PTEL);
 
         /* Load the TLB */
         asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
@@ -77,6 +77,6 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
         addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
         data = page | asid; /* VALID bit is off */
         jump_to_uncached();
-        ctrl_outl(data, addr);
+        __raw_writel(data, addr);
         back_to_cached();
 }
diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c
index 6f45c1f8a7fe..004bb3f25b5f 100644
--- a/arch/sh/mm/tlbflush_32.c
+++ b/arch/sh/mm/tlbflush_32.c
@@ -132,9 +132,9 @@ void local_flush_tlb_all(void)
          *      It's same position, bit #2.
          */
         local_irq_save(flags);
-        status = ctrl_inl(MMUCR);
+        status = __raw_readl(MMUCR);
         status |= 0x04;
-        ctrl_outl(status, MMUCR);
+        __raw_writel(status, MMUCR);
         ctrl_barrier();
         local_irq_restore(flags);
 }