5 files changed, 178 insertions, 28 deletions

diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 56d0a7daa34b..9c131cac91a4 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -237,7 +237,6 @@ choice
 
 config CACHE_WRITEBACK
         bool "Write-back"
-        depends on CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
 
 config CACHE_WRITETHROUGH
         bool "Write-through"
diff --git a/arch/sh/mm/Makefile_32 b/arch/sh/mm/Makefile_32
index e295db60b91b..70e0906023cc 100644
--- a/arch/sh/mm/Makefile_32
+++ b/arch/sh/mm/Makefile_32
@@ -5,12 +5,15 @@
 obj-y                   := init.o extable_32.o consistent.o
 
 ifndef CONFIG_CACHE_OFF
-obj-$(CONFIG_CPU_SH2)           += cache-sh2.o
-obj-$(CONFIG_CPU_SH3)           += cache-sh3.o
-obj-$(CONFIG_CPU_SH4)           += cache-sh4.o
-obj-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o
+cache-$(CONFIG_CPU_SH2)         := cache-sh2.o
+cache-$(CONFIG_CPU_SH2A)        := cache-sh2a.o
+cache-$(CONFIG_CPU_SH3)         := cache-sh3.o
+cache-$(CONFIG_CPU_SH4)         := cache-sh4.o
+cache-$(CONFIG_SH7705_CACHE_32KB)       += cache-sh7705.o
 endif
 
+obj-y                   += $(cache-y)
+
 mmu-y                   := tlb-nommu.o pg-nommu.o
 mmu-$(CONFIG_MMU)       := fault_32.o tlbflush_32.o ioremap_32.o
 
diff --git a/arch/sh/mm/cache-sh2.c b/arch/sh/mm/cache-sh2.c
index 6614033f6be9..c4e80d2b764b 100644
--- a/arch/sh/mm/cache-sh2.c
+++ b/arch/sh/mm/cache-sh2.c
@@ -2,6 +2,7 @@
  * arch/sh/mm/cache-sh2.c
  *
  * Copyright (C) 2002 Paul Mundt
+ * Copyright (C) 2008 Yoshinori Sato
  *
  * Released under the terms of the GNU GPL v2.0.
  */
@@ -24,8 +25,15 @@ void __flush_wback_region(void *start, int size)
         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
                 & ~(L1_CACHE_BYTES-1);
         for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                /* FIXME cache purge */
-                ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
+                unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0);
+                int way;
+                for (way = 0; way < 4; way++) {
+                        unsigned long data =  ctrl_inl(addr | (way << 12));
+                        if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
+                                data &= ~SH_CACHE_UPDATED;
+                                ctrl_outl(data, addr | (way << 12));
+                        }
+                }
         }
 }
 
@@ -37,21 +45,40 @@ void __flush_purge_region(void *start, int size)
         begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
                 & ~(L1_CACHE_BYTES-1);
-        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
-        }
+
+        for (v = begin; v < end; v+=L1_CACHE_BYTES)
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
 }
 
 void __flush_invalidate_region(void *start, int size)
 {
+#ifdef CONFIG_CACHE_WRITEBACK
+        /*
+         * SH-2 does not support individual line invalidation, only a
+         * global invalidate.
+         */
+        unsigned long ccr;
+        unsigned long flags;
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        ccr = ctrl_inl(CCR);
+        ccr |= CCR_CACHE_INVALIDATE;
+        ctrl_outl(ccr, CCR);
+
+        back_to_cached();
+        local_irq_restore(flags);
+#else
         unsigned long v;
         unsigned long begin, end;
 
         begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
                 & ~(L1_CACHE_BYTES-1);
-        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
-        }
-}
 
+        for (v = begin; v < end; v+=L1_CACHE_BYTES)
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
+#endif
+}
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
new file mode 100644
index 000000000000..62c0c5f35120
--- /dev/null
+++ b/arch/sh/mm/cache-sh2a.c
@@ -0,0 +1,129 @@
+/*
+ * arch/sh/mm/cache-sh2a.c
+ *
+ * Copyright (C) 2008 Yoshinori Sato
+ *
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+
+#include <asm/cache.h>
+#include <asm/addrspace.h>
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+
+void __flush_wback_region(void *start, int size)
+{
+        unsigned long v;
+        unsigned long begin, end;
+        unsigned long flags;
+
+        begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
+        end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+                & ~(L1_CACHE_BYTES-1);
+
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0);
+                int way;
+                for (way = 0; way < 4; way++) {
+                        unsigned long data =  ctrl_inl(addr | (way << 11));
+                        if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
+                                data &= ~SH_CACHE_UPDATED;
+                                ctrl_outl(data, addr | (way << 11));
+                        }
+                }
+        }
+
+        back_to_cached();
+        local_irq_restore(flags);
+}
+
+void __flush_purge_region(void *start, int size)
+{
+        unsigned long v;
+        unsigned long begin, end;
+        unsigned long flags;
+
+        begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
+        end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+                & ~(L1_CACHE_BYTES-1);
+
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
+        }
+        back_to_cached();
+        local_irq_restore(flags);
+}
+
+void __flush_invalidate_region(void *start, int size)
+{
+        unsigned long v;
+        unsigned long begin, end;
+        unsigned long flags;
+
+        begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
+        end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+                & ~(L1_CACHE_BYTES-1);
+        local_irq_save(flags);
+        jump_to_uncached();
+
+#ifdef CONFIG_CACHE_WRITEBACK
+        ctrl_outl(ctrl_inl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
+        /* I-cache invalidate */
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
+        }
+#else
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
+        }
+#endif
+        back_to_cached();
+        local_irq_restore(flags);
+}
+
+/* WBack O-Cache and flush I-Cache */
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+        unsigned long v;
+        unsigned long flags;
+
+        start = start & ~(L1_CACHE_BYTES-1);
+        end = (end + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);
+
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        for (v = start; v < end; v+=L1_CACHE_BYTES) {
+                unsigned long addr = (v & 0x000007f0);
+                int way;
+                /* O-Cache writeback */
+                for (way = 0; way < 4; way++) {
+                        unsigned long data =  ctrl_inl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
+                        if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
+                                data &= ~SH_CACHE_UPDATED;
+                                ctrl_outl(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
+                        }
+                }
+                /* I-Cache invalidate */
+                ctrl_outl(addr,
+                          CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008);
+        }
+
+        back_to_cached();
+        local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlb-sh5.c b/arch/sh/mm/tlb-sh5.c
index f34274a1ded3..dae131243bcc 100644
--- a/arch/sh/mm/tlb-sh5.c
+++ b/arch/sh/mm/tlb-sh5.c
@@ -15,9 +15,7 @@
 #include <asm/mmu_context.h>
 
 /**
- * sh64_tlb_init
- *
- * Perform initial setup for the DTLB and ITLB.
+ * sh64_tlb_init - Perform initial setup for the DTLB and ITLB.
  */
 int __init sh64_tlb_init(void)
 {
@@ -46,9 +44,7 @@ int __init sh64_tlb_init(void)
 }
 
 /**
- * sh64_next_free_dtlb_entry
- *
- * Find the next available DTLB entry
+ * sh64_next_free_dtlb_entry - Find the next available DTLB entry
  */
 unsigned long long sh64_next_free_dtlb_entry(void)
 {
@@ -56,9 +52,7 @@ unsigned long long sh64_next_free_dtlb_entry(void)
 }
 
 /**
- * sh64_get_wired_dtlb_entry
- *
- * Allocate a wired (locked-in) entry in the DTLB
+ * sh64_get_wired_dtlb_entry - Allocate a wired (locked-in) entry in the DTLB
  */
 unsigned long long sh64_get_wired_dtlb_entry(void)
 {
@@ -71,12 +65,10 @@ unsigned long long sh64_get_wired_dtlb_entry(void)
 }
 
 /**
- * sh64_put_wired_dtlb_entry
+ * sh64_put_wired_dtlb_entry - Free a wired (locked-in) entry in the DTLB.
  *
  * @entry:      Address of TLB slot.
  *
- * Free a wired (locked-in) entry in the DTLB.
- *
  * Works like a stack, last one to allocate must be first one to free.
  */
 int sh64_put_wired_dtlb_entry(unsigned long long entry)
@@ -115,7 +107,7 @@ int sh64_put_wired_dtlb_entry(unsigned long long entry)
 }
 
 /**
- * sh64_setup_tlb_slot
+ * sh64_setup_tlb_slot - Load up a translation in a wired slot.
  *
  * @config_addr:        Address of TLB slot.
  * @eaddr:              Virtual address.
@@ -154,7 +146,7 @@ inline void sh64_setup_tlb_slot(unsigned long long config_addr,
 }
 
 /**
- * sh64_teardown_tlb_slot
+ * sh64_teardown_tlb_slot - Teardown a translation.
  *
  * @config_addr:        Address of TLB slot.
  *