diff options
Diffstat (limited to 'arch/sh/mm/tlbflush_32.c')
-rw-r--r-- | arch/sh/mm/tlbflush_32.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c index 004bb3f25b5f..77dc5efa7127 100644 --- a/arch/sh/mm/tlbflush_32.c +++ b/arch/sh/mm/tlbflush_32.c | |||
@@ -123,18 +123,27 @@ void local_flush_tlb_mm(struct mm_struct *mm) | |||
123 | void local_flush_tlb_all(void) | 123 | void local_flush_tlb_all(void) |
124 | { | 124 | { |
125 | unsigned long flags, status; | 125 | unsigned long flags, status; |
126 | int i; | ||
126 | 127 | ||
127 | /* | 128 | /* |
128 | * Flush all the TLB. | 129 | * Flush all the TLB. |
129 | * | ||
130 | * Write to the MMU control register's bit: | ||
131 | * TF-bit for SH-3, TI-bit for SH-4. | ||
132 | * It's same position, bit #2. | ||
133 | */ | 130 | */ |
134 | local_irq_save(flags); | 131 | local_irq_save(flags); |
132 | jump_to_uncached(); | ||
133 | |||
135 | status = __raw_readl(MMUCR); | 134 | status = __raw_readl(MMUCR); |
136 | status |= 0x04; | 135 | status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT); |
137 | __raw_writel(status, MMUCR); | 136 | |
137 | if (status == 0) | ||
138 | status = MMUCR_URB_NENTRIES; | ||
139 | |||
140 | for (i = 0; i < status; i++) | ||
141 | __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); | ||
142 | |||
143 | for (i = 0; i < 4; i++) | ||
144 | __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); | ||
145 | |||
146 | back_to_cached(); | ||
138 | ctrl_barrier(); | 147 | ctrl_barrier(); |
139 | local_irq_restore(flags); | 148 | local_irq_restore(flags); |
140 | } | 149 | } |