1 files changed, 28 insertions, 27 deletions

diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c
index f74cf667c8fa..2d1dd6044307 100644
--- a/arch/sh/mm/tlb-sh4.c
+++ b/arch/sh/mm/tlb-sh4.c
@@ -4,27 +4,14 @@
  * SH-4 specific TLB operations
  *
  * Copyright (C) 1999  Niibe Yutaka
- * Copyright (C) 2002  Paul Mundt
+ * Copyright (C) 2002 - 2007 Paul Mundt
  *
  * Released under the terms of the GNU GPL v2.0.
  */
-#include <linux/signal.h>
-#include <linux/sched.h>
 #include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/mman.h>
 #include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/smp_lock.h>
-#include <linux/interrupt.h>
-
+#include <linux/io.h>
 #include <asm/system.h>
-#include <asm/io.h>
-#include <asm/uaccess.h>
-#include <asm/pgalloc.h>
 #include <asm/mmu_context.h>
 #include <asm/cacheflush.h>
 
@@ -34,22 +21,27 @@ void update_mmu_cache(struct vm_area_struct * vma,
         unsigned long flags;
         unsigned long pteval;
         unsigned long vpn;
-        struct page *page;
-        unsigned long pfn;
 
         /* Ptrace may call this routine. */
         if (vma && current->active_mm != vma->vm_mm)
                 return;
 
-        pfn = pte_pfn(pte);
-        if (pfn_valid(pfn)) {
-                page = pfn_to_page(pfn);
-                if (!test_bit(PG_mapped, &page->flags)) {
-                        unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
-                        __flush_wback_region((void *)P1SEGADDR(phys), PAGE_SIZE);
-                        __set_bit(PG_mapped, &page->flags);
+#ifndef CONFIG_CACHE_OFF
+        {
+                unsigned long pfn = pte_pfn(pte);
+
+                if (pfn_valid(pfn)) {
+                        struct page *page = pfn_to_page(pfn);
+
+                        if (!test_bit(PG_mapped, &page->flags)) {
+                                unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
+                                __flush_wback_region((void *)P1SEGADDR(phys),
+                                                     PAGE_SIZE);
+                                __set_bit(PG_mapped, &page->flags);
+                        }
                 }
         }
+#endif
 
         local_irq_save(flags);
 
@@ -57,16 +49,26 @@ void update_mmu_cache(struct vm_area_struct * vma,
         vpn = (address & MMU_VPN_MASK) | get_asid();
         ctrl_outl(vpn, MMU_PTEH);
 
-        pteval = pte_val(pte);
+        pteval = pte.pte_low;
 
         /* Set PTEA register */
+#ifdef CONFIG_X2TLB
+        /*
+         * For the extended mode TLB this is trivial, only the ESZ and
+         * EPR bits need to be written out to PTEA, with the remainder of
+         * the protection bits (with the exception of the compat-mode SZ
+         * and PR bits, which are cleared) being written out in PTEL.
+         */
+        ctrl_outl(pte.pte_high, MMU_PTEA);
+#else
         if (cpu_data->flags & CPU_HAS_PTEA)
                 /* TODO: make this look less hacky */
                 ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA);
+#endif
 
         /* Set PTEL register */
         pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
-#ifdef CONFIG_SH_WRITETHROUGH
+#ifdef CONFIG_CACHE_WRITETHROUGH
         pteval |= _PAGE_WT;
 #endif
         /* conveniently, we want all the software flags to be 0 anyway */
@@ -93,4 +95,3 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
         ctrl_outl(data, addr);
         back_to_P1();
 }
-