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-rw-r--r--arch/sh/mm/tlb-sh4.c37
1 files changed, 11 insertions, 26 deletions
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c
index f0c7b7397fa6..8cf550e2570f 100644
--- a/arch/sh/mm/tlb-sh4.c
+++ b/arch/sh/mm/tlb-sh4.c
@@ -15,34 +15,16 @@
15#include <asm/mmu_context.h> 15#include <asm/mmu_context.h>
16#include <asm/cacheflush.h> 16#include <asm/cacheflush.h>
17 17
18void update_mmu_cache(struct vm_area_struct * vma, 18void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
19 unsigned long address, pte_t pte)
20{ 19{
21 unsigned long flags; 20 unsigned long flags, pteval, vpn;
22 unsigned long pteval;
23 unsigned long vpn;
24 21
25 /* Ptrace may call this routine. */ 22 /*
23 * Handle debugger faulting in for debugee.
24 */
26 if (vma && current->active_mm != vma->vm_mm) 25 if (vma && current->active_mm != vma->vm_mm)
27 return; 26 return;
28 27
29#ifndef CONFIG_CACHE_OFF
30 {
31 unsigned long pfn = pte_pfn(pte);
32
33 if (pfn_valid(pfn)) {
34 struct page *page = pfn_to_page(pfn);
35
36 if (!test_bit(PG_mapped, &page->flags)) {
37 unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
38 __flush_wback_region((void *)P1SEGADDR(phys),
39 PAGE_SIZE);
40 __set_bit(PG_mapped, &page->flags);
41 }
42 }
43 }
44#endif
45
46 local_irq_save(flags); 28 local_irq_save(flags);
47 29
48 /* Set PTEH register */ 30 /* Set PTEH register */
@@ -61,9 +43,12 @@ void update_mmu_cache(struct vm_area_struct * vma,
61 */ 43 */
62 ctrl_outl(pte.pte_high, MMU_PTEA); 44 ctrl_outl(pte.pte_high, MMU_PTEA);
63#else 45#else
64 if (cpu_data->flags & CPU_HAS_PTEA) 46 if (cpu_data->flags & CPU_HAS_PTEA) {
65 /* TODO: make this look less hacky */ 47 /* The last 3 bits and the first one of pteval contains
66 ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA); 48 * the PTEA timing control and space attribute bits
49 */
50 ctrl_outl(copy_ptea_attributes(pteval), MMU_PTEA);
51 }
67#endif 52#endif
68 53
69 /* Set PTEL register */ 54 /* Set PTEL register */