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-rw-r--r--arch/sh/mm/tlb-sh4.c66
1 files changed, 66 insertions, 0 deletions
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c
index 8cf550e2570f..4c6234743318 100644
--- a/arch/sh/mm/tlb-sh4.c
+++ b/arch/sh/mm/tlb-sh4.c
@@ -81,3 +81,69 @@ void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid,
81 ctrl_outl(data, addr); 81 ctrl_outl(data, addr);
82 back_to_cached(); 82 back_to_cached();
83} 83}
84
85/*
86 * Load the entry for 'addr' into the TLB and wire the entry.
87 */
88void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
89{
90 unsigned long status, flags;
91 int urb;
92
93 local_irq_save(flags);
94
95 /* Load the entry into the TLB */
96 __update_tlb(vma, addr, pte);
97
98 /* ... and wire it up. */
99 status = ctrl_inl(MMUCR);
100 urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
101 status &= ~MMUCR_URB;
102
103 /*
104 * Make sure we're not trying to wire the last TLB entry slot.
105 */
106 BUG_ON(!--urb);
107
108 urb = urb % MMUCR_URB_NENTRIES;
109
110 status |= (urb << MMUCR_URB_SHIFT);
111 ctrl_outl(status, MMUCR);
112 ctrl_barrier();
113
114 local_irq_restore(flags);
115}
116
117/*
118 * Unwire the last wired TLB entry.
119 *
120 * It should also be noted that it is not possible to wire and unwire
121 * TLB entries in an arbitrary order. If you wire TLB entry N, followed
122 * by entry N+1, you must unwire entry N+1 first, then entry N. In this
123 * respect, it works like a stack or LIFO queue.
124 */
125void tlb_unwire_entry(void)
126{
127 unsigned long status, flags;
128 int urb;
129
130 local_irq_save(flags);
131
132 status = ctrl_inl(MMUCR);
133 urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
134 status &= ~MMUCR_URB;
135
136 /*
137 * Make sure we're not trying to unwire a TLB entry when none
138 * have been wired.
139 */
140 BUG_ON(urb++ == MMUCR_URB_NENTRIES);
141
142 urb = urb % MMUCR_URB_NENTRIES;
143
144 status |= (urb << MMUCR_URB_SHIFT);
145 ctrl_outl(status, MMUCR);
146 ctrl_barrier();
147
148 local_irq_restore(flags);
149}