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-rw-r--r--arch/sh/mm/tlb-sh3.c27
1 files changed, 5 insertions, 22 deletions
diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c
index 17cb7c3adf22..ace8e6d2f59d 100644
--- a/arch/sh/mm/tlb-sh3.c
+++ b/arch/sh/mm/tlb-sh3.c
@@ -27,32 +27,16 @@
27#include <asm/mmu_context.h> 27#include <asm/mmu_context.h>
28#include <asm/cacheflush.h> 28#include <asm/cacheflush.h>
29 29
30void update_mmu_cache(struct vm_area_struct * vma, 30void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
31 unsigned long address, pte_t pte)
32{ 31{
33 unsigned long flags; 32 unsigned long flags, pteval, vpn;
34 unsigned long pteval;
35 unsigned long vpn;
36 33
37 /* Ptrace may call this routine. */ 34 /*
35 * Handle debugger faulting in for debugee.
36 */
38 if (vma && current->active_mm != vma->vm_mm) 37 if (vma && current->active_mm != vma->vm_mm)
39 return; 38 return;
40 39
41#if defined(CONFIG_SH7705_CACHE_32KB)
42 {
43 struct page *page = pte_page(pte);
44 unsigned long pfn = pte_pfn(pte);
45
46 if (pfn_valid(pfn) && !test_bit(PG_mapped, &page->flags)) {
47 unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
48
49 __flush_wback_region((void *)P1SEGADDR(phys),
50 PAGE_SIZE);
51 __set_bit(PG_mapped, &page->flags);
52 }
53 }
54#endif
55
56 local_irq_save(flags); 40 local_irq_save(flags);
57 41
58 /* Set PTEH register */ 42 /* Set PTEH register */
@@ -93,4 +77,3 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
93 for (i = 0; i < ways; i++) 77 for (i = 0; i < ways; i++)
94 ctrl_outl(data, addr + (i << 8)); 78 ctrl_outl(data, addr + (i << 8));
95} 79}
96