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-rw-r--r--arch/sh/mm/tlb-pteaex.c28
1 files changed, 5 insertions, 23 deletions
diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c
index 2aab3ea934d7..409b7c2b4b9d 100644
--- a/arch/sh/mm/tlb-pteaex.c
+++ b/arch/sh/mm/tlb-pteaex.c
@@ -16,34 +16,16 @@
16#include <asm/mmu_context.h> 16#include <asm/mmu_context.h>
17#include <asm/cacheflush.h> 17#include <asm/cacheflush.h>
18 18
19void update_mmu_cache(struct vm_area_struct * vma, 19void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
20 unsigned long address, pte_t pte)
21{ 20{
22 unsigned long flags; 21 unsigned long flags, pteval, vpn;
23 unsigned long pteval;
24 unsigned long vpn;
25 22
26 /* Ptrace may call this routine. */ 23 /*
24 * Handle debugger faulting in for debugee.
25 */
27 if (vma && current->active_mm != vma->vm_mm) 26 if (vma && current->active_mm != vma->vm_mm)
28 return; 27 return;
29 28
30#ifndef CONFIG_CACHE_OFF
31 {
32 unsigned long pfn = pte_pfn(pte);
33
34 if (pfn_valid(pfn)) {
35 struct page *page = pfn_to_page(pfn);
36
37 if (!test_bit(PG_mapped, &page->flags)) {
38 unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
39 __flush_wback_region((void *)P1SEGADDR(phys),
40 PAGE_SIZE);
41 __set_bit(PG_mapped, &page->flags);
42 }
43 }
44 }
45#endif
46
47 local_irq_save(flags); 29 local_irq_save(flags);
48 30
49 /* Set PTEH register */ 31 /* Set PTEH register */