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-rw-r--r--arch/sh/mm/flush-sh4.c81
1 files changed, 27 insertions, 54 deletions
diff --git a/arch/sh/mm/flush-sh4.c b/arch/sh/mm/flush-sh4.c
index 99c50dc7551e..cef402678f42 100644
--- a/arch/sh/mm/flush-sh4.c
+++ b/arch/sh/mm/flush-sh4.c
@@ -19,28 +19,19 @@ static void sh4__flush_wback_region(void *start, int size)
19 cnt = (end - v) / L1_CACHE_BYTES; 19 cnt = (end - v) / L1_CACHE_BYTES;
20 20
21 while (cnt >= 8) { 21 while (cnt >= 8) {
22 asm volatile("ocbwb @%0" : : "r" (v)); 22 __ocbwb(v); v += L1_CACHE_BYTES;
23 v += L1_CACHE_BYTES; 23 __ocbwb(v); v += L1_CACHE_BYTES;
24 asm volatile("ocbwb @%0" : : "r" (v)); 24 __ocbwb(v); v += L1_CACHE_BYTES;
25 v += L1_CACHE_BYTES; 25 __ocbwb(v); v += L1_CACHE_BYTES;
26 asm volatile("ocbwb @%0" : : "r" (v)); 26 __ocbwb(v); v += L1_CACHE_BYTES;
27 v += L1_CACHE_BYTES; 27 __ocbwb(v); v += L1_CACHE_BYTES;
28 asm volatile("ocbwb @%0" : : "r" (v)); 28 __ocbwb(v); v += L1_CACHE_BYTES;
29 v += L1_CACHE_BYTES; 29 __ocbwb(v); v += L1_CACHE_BYTES;
30 asm volatile("ocbwb @%0" : : "r" (v));
31 v += L1_CACHE_BYTES;
32 asm volatile("ocbwb @%0" : : "r" (v));
33 v += L1_CACHE_BYTES;
34 asm volatile("ocbwb @%0" : : "r" (v));
35 v += L1_CACHE_BYTES;
36 asm volatile("ocbwb @%0" : : "r" (v));
37 v += L1_CACHE_BYTES;
38 cnt -= 8; 30 cnt -= 8;
39 } 31 }
40 32
41 while (cnt) { 33 while (cnt) {
42 asm volatile("ocbwb @%0" : : "r" (v)); 34 __ocbwb(v); v += L1_CACHE_BYTES;
43 v += L1_CACHE_BYTES;
44 cnt--; 35 cnt--;
45 } 36 }
46} 37}
@@ -62,27 +53,18 @@ static void sh4__flush_purge_region(void *start, int size)
62 cnt = (end - v) / L1_CACHE_BYTES; 53 cnt = (end - v) / L1_CACHE_BYTES;
63 54
64 while (cnt >= 8) { 55 while (cnt >= 8) {
65 asm volatile("ocbp @%0" : : "r" (v)); 56 __ocbp(v); v += L1_CACHE_BYTES;
66 v += L1_CACHE_BYTES; 57 __ocbp(v); v += L1_CACHE_BYTES;
67 asm volatile("ocbp @%0" : : "r" (v)); 58 __ocbp(v); v += L1_CACHE_BYTES;
68 v += L1_CACHE_BYTES; 59 __ocbp(v); v += L1_CACHE_BYTES;
69 asm volatile("ocbp @%0" : : "r" (v)); 60 __ocbp(v); v += L1_CACHE_BYTES;
70 v += L1_CACHE_BYTES; 61 __ocbp(v); v += L1_CACHE_BYTES;
71 asm volatile("ocbp @%0" : : "r" (v)); 62 __ocbp(v); v += L1_CACHE_BYTES;
72 v += L1_CACHE_BYTES; 63 __ocbp(v); v += L1_CACHE_BYTES;
73 asm volatile("ocbp @%0" : : "r" (v));
74 v += L1_CACHE_BYTES;
75 asm volatile("ocbp @%0" : : "r" (v));
76 v += L1_CACHE_BYTES;
77 asm volatile("ocbp @%0" : : "r" (v));
78 v += L1_CACHE_BYTES;
79 asm volatile("ocbp @%0" : : "r" (v));
80 v += L1_CACHE_BYTES;
81 cnt -= 8; 64 cnt -= 8;
82 } 65 }
83 while (cnt) { 66 while (cnt) {
84 asm volatile("ocbp @%0" : : "r" (v)); 67 __ocbp(v); v += L1_CACHE_BYTES;
85 v += L1_CACHE_BYTES;
86 cnt--; 68 cnt--;
87 } 69 }
88} 70}
@@ -101,28 +83,19 @@ static void sh4__flush_invalidate_region(void *start, int size)
101 cnt = (end - v) / L1_CACHE_BYTES; 83 cnt = (end - v) / L1_CACHE_BYTES;
102 84
103 while (cnt >= 8) { 85 while (cnt >= 8) {
104 asm volatile("ocbi @%0" : : "r" (v)); 86 __ocbi(v); v += L1_CACHE_BYTES;
105 v += L1_CACHE_BYTES; 87 __ocbi(v); v += L1_CACHE_BYTES;
106 asm volatile("ocbi @%0" : : "r" (v)); 88 __ocbi(v); v += L1_CACHE_BYTES;
107 v += L1_CACHE_BYTES; 89 __ocbi(v); v += L1_CACHE_BYTES;
108 asm volatile("ocbi @%0" : : "r" (v)); 90 __ocbi(v); v += L1_CACHE_BYTES;
109 v += L1_CACHE_BYTES; 91 __ocbi(v); v += L1_CACHE_BYTES;
110 asm volatile("ocbi @%0" : : "r" (v)); 92 __ocbi(v); v += L1_CACHE_BYTES;
111 v += L1_CACHE_BYTES; 93 __ocbi(v); v += L1_CACHE_BYTES;
112 asm volatile("ocbi @%0" : : "r" (v));
113 v += L1_CACHE_BYTES;
114 asm volatile("ocbi @%0" : : "r" (v));
115 v += L1_CACHE_BYTES;
116 asm volatile("ocbi @%0" : : "r" (v));
117 v += L1_CACHE_BYTES;
118 asm volatile("ocbi @%0" : : "r" (v));
119 v += L1_CACHE_BYTES;
120 cnt -= 8; 94 cnt -= 8;
121 } 95 }
122 96
123 while (cnt) { 97 while (cnt) {
124 asm volatile("ocbi @%0" : : "r" (v)); 98 __ocbi(v); v += L1_CACHE_BYTES;
125 v += L1_CACHE_BYTES;
126 cnt--; 99 cnt--;
127 } 100 }
128} 101}