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Diffstat (limited to 'arch/sh/mm/cache-sh4.c')
-rw-r--r--arch/sh/mm/cache-sh4.c27
1 files changed, 10 insertions, 17 deletions
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 560ddb6bc8a7..2cfae81914aa 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -36,7 +36,7 @@ static void __flush_cache_one(unsigned long addr, unsigned long phys,
36 * Called from kernel/module.c:sys_init_module and routine for a.out format, 36 * Called from kernel/module.c:sys_init_module and routine for a.out format,
37 * signal handler code and kprobes code 37 * signal handler code and kprobes code
38 */ 38 */
39static void __uses_jump_to_uncached sh4_flush_icache_range(void *args) 39static void sh4_flush_icache_range(void *args)
40{ 40{
41 struct flusher_data *data = args; 41 struct flusher_data *data = args;
42 unsigned long start, end; 42 unsigned long start, end;
@@ -109,6 +109,7 @@ static inline void flush_cache_one(unsigned long start, unsigned long phys)
109static void sh4_flush_dcache_page(void *arg) 109static void sh4_flush_dcache_page(void *arg)
110{ 110{
111 struct page *page = arg; 111 struct page *page = arg;
112 unsigned long addr = (unsigned long)page_address(page);
112#ifndef CONFIG_SMP 113#ifndef CONFIG_SMP
113 struct address_space *mapping = page_mapping(page); 114 struct address_space *mapping = page_mapping(page);
114 115
@@ -116,22 +117,14 @@ static void sh4_flush_dcache_page(void *arg)
116 set_bit(PG_dcache_dirty, &page->flags); 117 set_bit(PG_dcache_dirty, &page->flags);
117 else 118 else
118#endif 119#endif
119 { 120 flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
120 unsigned long phys = page_to_phys(page); 121 (addr & shm_align_mask), page_to_phys(page));
121 unsigned long addr = CACHE_OC_ADDRESS_ARRAY;
122 int i, n;
123
124 /* Loop all the D-cache */
125 n = boot_cpu_data.dcache.n_aliases;
126 for (i = 0; i < n; i++, addr += PAGE_SIZE)
127 flush_cache_one(addr, phys);
128 }
129 122
130 wmb(); 123 wmb();
131} 124}
132 125
133/* TODO: Selective icache invalidation through IC address array.. */ 126/* TODO: Selective icache invalidation through IC address array.. */
134static void __uses_jump_to_uncached flush_icache_all(void) 127static void flush_icache_all(void)
135{ 128{
136 unsigned long flags, ccr; 129 unsigned long flags, ccr;
137 130
@@ -139,9 +132,9 @@ static void __uses_jump_to_uncached flush_icache_all(void)
139 jump_to_uncached(); 132 jump_to_uncached();
140 133
141 /* Flush I-cache */ 134 /* Flush I-cache */
142 ccr = ctrl_inl(CCR); 135 ccr = __raw_readl(CCR);
143 ccr |= CCR_CACHE_ICI; 136 ccr |= CCR_CACHE_ICI;
144 ctrl_outl(ccr, CCR); 137 __raw_writel(ccr, CCR);
145 138
146 /* 139 /*
147 * back_to_cached() will take care of the barrier for us, don't add 140 * back_to_cached() will take care of the barrier for us, don't add
@@ -384,9 +377,9 @@ extern void __weak sh4__flush_region_init(void);
384void __init sh4_cache_init(void) 377void __init sh4_cache_init(void)
385{ 378{
386 printk("PVR=%08x CVR=%08x PRR=%08x\n", 379 printk("PVR=%08x CVR=%08x PRR=%08x\n",
387 ctrl_inl(CCN_PVR), 380 __raw_readl(CCN_PVR),
388 ctrl_inl(CCN_CVR), 381 __raw_readl(CCN_CVR),
389 ctrl_inl(CCN_PRR)); 382 __raw_readl(CCN_PRR));
390 383
391 local_flush_icache_range = sh4_flush_icache_range; 384 local_flush_icache_range = sh4_flush_icache_range;
392 local_flush_dcache_page = sh4_flush_dcache_page; 385 local_flush_dcache_page = sh4_flush_dcache_page;