diff options
Diffstat (limited to 'arch/sh/mm/cache-sh2a.c')
| -rw-r--r-- | arch/sh/mm/cache-sh2a.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c index 975899d83564..1f51225426a2 100644 --- a/arch/sh/mm/cache-sh2a.c +++ b/arch/sh/mm/cache-sh2a.c | |||
| @@ -32,10 +32,10 @@ static void sh2a__flush_wback_region(void *start, int size) | |||
| 32 | unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0); | 32 | unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0); |
| 33 | int way; | 33 | int way; |
| 34 | for (way = 0; way < 4; way++) { | 34 | for (way = 0; way < 4; way++) { |
| 35 | unsigned long data = ctrl_inl(addr | (way << 11)); | 35 | unsigned long data = __raw_readl(addr | (way << 11)); |
| 36 | if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { | 36 | if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { |
| 37 | data &= ~SH_CACHE_UPDATED; | 37 | data &= ~SH_CACHE_UPDATED; |
| 38 | ctrl_outl(data, addr | (way << 11)); | 38 | __raw_writel(data, addr | (way << 11)); |
| 39 | } | 39 | } |
| 40 | } | 40 | } |
| 41 | } | 41 | } |
| @@ -58,7 +58,7 @@ static void sh2a__flush_purge_region(void *start, int size) | |||
| 58 | jump_to_uncached(); | 58 | jump_to_uncached(); |
| 59 | 59 | ||
| 60 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { | 60 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { |
| 61 | ctrl_outl((v & CACHE_PHYSADDR_MASK), | 61 | __raw_writel((v & CACHE_PHYSADDR_MASK), |
| 62 | CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); | 62 | CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); |
| 63 | } | 63 | } |
| 64 | back_to_cached(); | 64 | back_to_cached(); |
| @@ -78,17 +78,17 @@ static void sh2a__flush_invalidate_region(void *start, int size) | |||
| 78 | jump_to_uncached(); | 78 | jump_to_uncached(); |
| 79 | 79 | ||
| 80 | #ifdef CONFIG_CACHE_WRITEBACK | 80 | #ifdef CONFIG_CACHE_WRITEBACK |
| 81 | ctrl_outl(ctrl_inl(CCR) | CCR_OCACHE_INVALIDATE, CCR); | 81 | __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR); |
| 82 | /* I-cache invalidate */ | 82 | /* I-cache invalidate */ |
| 83 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { | 83 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { |
| 84 | ctrl_outl((v & CACHE_PHYSADDR_MASK), | 84 | __raw_writel((v & CACHE_PHYSADDR_MASK), |
| 85 | CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); | 85 | CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); |
| 86 | } | 86 | } |
| 87 | #else | 87 | #else |
| 88 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { | 88 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { |
| 89 | ctrl_outl((v & CACHE_PHYSADDR_MASK), | 89 | __raw_writel((v & CACHE_PHYSADDR_MASK), |
| 90 | CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); | 90 | CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); |
| 91 | ctrl_outl((v & CACHE_PHYSADDR_MASK), | 91 | __raw_writel((v & CACHE_PHYSADDR_MASK), |
| 92 | CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); | 92 | CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); |
| 93 | } | 93 | } |
| 94 | #endif | 94 | #endif |
| @@ -115,14 +115,14 @@ static void sh2a_flush_icache_range(void *args) | |||
| 115 | int way; | 115 | int way; |
| 116 | /* O-Cache writeback */ | 116 | /* O-Cache writeback */ |
| 117 | for (way = 0; way < 4; way++) { | 117 | for (way = 0; way < 4; way++) { |
| 118 | unsigned long data = ctrl_inl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11)); | 118 | unsigned long data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11)); |
| 119 | if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { | 119 | if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { |
| 120 | data &= ~SH_CACHE_UPDATED; | 120 | data &= ~SH_CACHE_UPDATED; |
| 121 | ctrl_outl(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11)); | 121 | __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11)); |
| 122 | } | 122 | } |
| 123 | } | 123 | } |
| 124 | /* I-Cache invalidate */ | 124 | /* I-Cache invalidate */ |
| 125 | ctrl_outl(addr, | 125 | __raw_writel(addr, |
| 126 | CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008); | 126 | CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008); |
| 127 | } | 127 | } |
| 128 | 128 | ||
