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-rw-r--r--arch/sh/kernel/cpu/Makefile2
-rw-r--r--arch/sh/kernel/cpu/hwblk.c159
-rw-r--r--arch/sh/kernel/cpu/sh4/sq.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile6
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c77
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c209
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c201
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c106
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c117
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c121
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c38
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c39
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c64
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c7
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c2
-rw-r--r--arch/sh/kernel/cpu/shmobile/Makefile1
-rw-r--r--arch/sh/kernel/cpu/shmobile/cpuidle.c3
-rw-r--r--arch/sh/kernel/cpu/shmobile/pm_runtime.c319
-rw-r--r--arch/sh/kernel/entry-common.S1
-rw-r--r--arch/sh/kernel/signal_32.c4
-rw-r--r--arch/sh/kernel/signal_64.c4
-rw-r--r--arch/sh/kernel/time.c2
25 files changed, 252 insertions, 1244 deletions
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index ae95935d93cd..fa58bfd30d82 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -18,4 +18,4 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
18obj-$(CONFIG_SH_ADC) += adc.o 18obj-$(CONFIG_SH_ADC) += adc.o
19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o 19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
20 20
21obj-y += irq/ init.o clock.o fpu.o hwblk.o proc.o 21obj-y += irq/ init.o clock.o fpu.o proc.o
diff --git a/arch/sh/kernel/cpu/hwblk.c b/arch/sh/kernel/cpu/hwblk.c
deleted file mode 100644
index 3e985aae5d91..000000000000
--- a/arch/sh/kernel/cpu/hwblk.c
+++ /dev/null
@@ -1,159 +0,0 @@
1#include <linux/clk.h>
2#include <linux/compiler.h>
3#include <linux/io.h>
4#include <linux/spinlock.h>
5#include <asm/suspend.h>
6#include <asm/hwblk.h>
7#include <asm/clock.h>
8
9static DEFINE_SPINLOCK(hwblk_lock);
10
11static void hwblk_area_mod_cnt(struct hwblk_info *info,
12 int area, int counter, int value, int goal)
13{
14 struct hwblk_area *hap = info->areas + area;
15
16 hap->cnt[counter] += value;
17
18 if (hap->cnt[counter] != goal)
19 return;
20
21 if (hap->flags & HWBLK_AREA_FLAG_PARENT)
22 hwblk_area_mod_cnt(info, hap->parent, counter, value, goal);
23}
24
25
26static int __hwblk_mod_cnt(struct hwblk_info *info, int hwblk,
27 int counter, int value, int goal)
28{
29 struct hwblk *hp = info->hwblks + hwblk;
30
31 hp->cnt[counter] += value;
32 if (hp->cnt[counter] == goal)
33 hwblk_area_mod_cnt(info, hp->area, counter, value, goal);
34
35 return hp->cnt[counter];
36}
37
38static void hwblk_mod_cnt(struct hwblk_info *info, int hwblk,
39 int counter, int value, int goal)
40{
41 unsigned long flags;
42
43 spin_lock_irqsave(&hwblk_lock, flags);
44 __hwblk_mod_cnt(info, hwblk, counter, value, goal);
45 spin_unlock_irqrestore(&hwblk_lock, flags);
46}
47
48void hwblk_cnt_inc(struct hwblk_info *info, int hwblk, int counter)
49{
50 hwblk_mod_cnt(info, hwblk, counter, 1, 1);
51}
52
53void hwblk_cnt_dec(struct hwblk_info *info, int hwblk, int counter)
54{
55 hwblk_mod_cnt(info, hwblk, counter, -1, 0);
56}
57
58void hwblk_enable(struct hwblk_info *info, int hwblk)
59{
60 struct hwblk *hp = info->hwblks + hwblk;
61 unsigned long tmp;
62 unsigned long flags;
63 int ret;
64
65 spin_lock_irqsave(&hwblk_lock, flags);
66
67 ret = __hwblk_mod_cnt(info, hwblk, HWBLK_CNT_USAGE, 1, 1);
68 if (ret == 1) {
69 tmp = __raw_readl(hp->mstp);
70 tmp &= ~(1 << hp->bit);
71 __raw_writel(tmp, hp->mstp);
72 }
73
74 spin_unlock_irqrestore(&hwblk_lock, flags);
75}
76
77void hwblk_disable(struct hwblk_info *info, int hwblk)
78{
79 struct hwblk *hp = info->hwblks + hwblk;
80 unsigned long tmp;
81 unsigned long flags;
82 int ret;
83
84 spin_lock_irqsave(&hwblk_lock, flags);
85
86 ret = __hwblk_mod_cnt(info, hwblk, HWBLK_CNT_USAGE, -1, 0);
87 if (ret == 0) {
88 tmp = __raw_readl(hp->mstp);
89 tmp |= 1 << hp->bit;
90 __raw_writel(tmp, hp->mstp);
91 }
92
93 spin_unlock_irqrestore(&hwblk_lock, flags);
94}
95
96struct hwblk_info *hwblk_info;
97
98int __init hwblk_register(struct hwblk_info *info)
99{
100 hwblk_info = info;
101 return 0;
102}
103
104int __init __weak arch_hwblk_init(void)
105{
106 return 0;
107}
108
109int __weak arch_hwblk_sleep_mode(void)
110{
111 return SUSP_SH_SLEEP;
112}
113
114int __init hwblk_init(void)
115{
116 return arch_hwblk_init();
117}
118
119/* allow clocks to enable and disable hardware blocks */
120static int sh_hwblk_clk_enable(struct clk *clk)
121{
122 if (!hwblk_info)
123 return -ENOENT;
124
125 hwblk_enable(hwblk_info, clk->arch_flags);
126 return 0;
127}
128
129static void sh_hwblk_clk_disable(struct clk *clk)
130{
131 if (hwblk_info)
132 hwblk_disable(hwblk_info, clk->arch_flags);
133}
134
135static struct clk_ops sh_hwblk_clk_ops = {
136 .enable = sh_hwblk_clk_enable,
137 .disable = sh_hwblk_clk_disable,
138 .recalc = followparent_recalc,
139};
140
141int __init sh_hwblk_clk_register(struct clk *clks, int nr)
142{
143 struct clk *clkp;
144 int ret = 0;
145 int k;
146
147 for (k = 0; !ret && (k < nr); k++) {
148 clkp = clks + k;
149
150 /* skip over clocks using hwblk 0 (HWBLK_UNKNOWN) */
151 if (!clkp->arch_flags)
152 continue;
153
154 clkp->ops = &sh_hwblk_clk_ops;
155 ret |= clk_register(clkp);
156 }
157
158 return ret;
159}
diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c
index a8140f0bbf6c..0a47bd3e7bee 100644
--- a/arch/sh/kernel/cpu/sh4/sq.c
+++ b/arch/sh/kernel/cpu/sh4/sq.c
@@ -337,7 +337,7 @@ static struct kobj_type ktype_percpu_entry = {
337 .default_attrs = sq_sysfs_attrs, 337 .default_attrs = sq_sysfs_attrs,
338}; 338};
339 339
340static int __devinit sq_dev_add(struct device *dev) 340static int sq_dev_add(struct device *dev, struct subsys_interface *sif)
341{ 341{
342 unsigned int cpu = dev->id; 342 unsigned int cpu = dev->id;
343 struct kobject *kobj; 343 struct kobject *kobj;
@@ -355,7 +355,7 @@ static int __devinit sq_dev_add(struct device *dev)
355 return error; 355 return error;
356} 356}
357 357
358static int __devexit sq_dev_remove(struct device *dev) 358static int sq_dev_remove(struct device *dev, struct subsys_interface *sif)
359{ 359{
360 unsigned int cpu = dev->id; 360 unsigned int cpu = dev->id;
361 struct kobject *kobj = sq_kobject[cpu]; 361 struct kobject *kobj = sq_kobject[cpu];
@@ -365,10 +365,10 @@ static int __devexit sq_dev_remove(struct device *dev)
365} 365}
366 366
367static struct subsys_interface sq_interface = { 367static struct subsys_interface sq_interface = {
368 .name = "sq" 368 .name = "sq",
369 .subsys = &cpu_subsys, 369 .subsys = &cpu_subsys,
370 .add_dev = sq_dev_add, 370 .add_dev = sq_dev_add,
371 .remove_dev = __devexit_p(sq_dev_remove), 371 .remove_dev = sq_dev_remove,
372}; 372};
373 373
374static int __init sq_api_init(void) 374static int __init sq_api_init(void)
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index c57fb287011e..0b22d108f4c5 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -27,9 +27,9 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
27clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
28clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
29clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o 29clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o hwblk-sh7722.o 30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o hwblk-sh7723.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o hwblk-sh7724.o 32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o 33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
35 35
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index c9a48088ad47..212c72ef959c 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -22,8 +22,8 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <linux/sh_clk.h>
25#include <asm/clock.h> 26#include <asm/clock.h>
26#include <asm/hwblk.h>
27#include <cpu/sh7722.h> 27#include <cpu/sh7722.h>
28 28
29/* SH7722 registers */ 29/* SH7722 registers */
@@ -33,6 +33,9 @@
33#define SCLKBCR 0xa415000c 33#define SCLKBCR 0xa415000c
34#define IRDACLKCR 0xa4150018 34#define IRDACLKCR 0xa4150018
35#define PLLCR 0xa4150024 35#define PLLCR 0xa4150024
36#define MSTPCR0 0xa4150030
37#define MSTPCR1 0xa4150034
38#define MSTPCR2 0xa4150038
36#define DLLFRQ 0xa4150050 39#define DLLFRQ 0xa4150050
37 40
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 41/* Fixed 32 KHz root clock for RTC and Power Management purposes */
@@ -148,31 +151,31 @@ struct clk div6_clks[DIV6_NR] = {
148}; 151};
149 152
150static struct clk mstp_clks[HWBLK_NR] = { 153static struct clk mstp_clks[HWBLK_NR] = {
151 SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT), 154 [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
152 SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 155 [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0), 156 [HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
154 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 157 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
155 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 158 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
156 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0), 159 [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
157 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 160 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
158 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 161 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
159 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 162 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
160 163
161 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0), 164 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
162 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 165 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
163 166
164 SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0), 167 [HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
165 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 168 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
166 SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0), 169 [HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
167 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 170 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
168 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0), 171 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
169 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 172 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
170 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), 173 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
171 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0), 174 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
172 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0), 175 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
173 SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0), 176 [HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
174 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 177 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
175 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0), 178 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0),
176}; 179};
177 180
178static struct clk_lookup lookups[] = { 181static struct clk_lookup lookups[] = {
@@ -205,27 +208,27 @@ static struct clk_lookup lookups[] = {
205 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU]), 208 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU]),
206 209
207 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 210 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
208 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 211 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
209 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), 212 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
210 213
211 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]), 214 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
212 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]), 215 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
213 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]), 216 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
214 217
215 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]), 218 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
216 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 219 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
217 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]), 220 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI]),
218 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 221 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
219 CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]), 222 CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
220 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 223 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
221 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]), 224 CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
222 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 225 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
223 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), 226 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
224 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), 227 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
225 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]), 228 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]),
226 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]), 229 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
227 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 230 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
228 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 231 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
229}; 232};
230 233
231int __init arch_clk_init(void) 234int __init arch_clk_init(void)
@@ -258,7 +261,7 @@ int __init arch_clk_init(void)
258 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 261 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
259 262
260 if (!ret) 263 if (!ret)
261 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 264 ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
262 265
263 return ret; 266 return ret;
264} 267}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 3cc3827380e3..2f8c9179da47 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -23,8 +23,8 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26#include <linux/sh_clk.h>
26#include <asm/clock.h> 27#include <asm/clock.h>
27#include <asm/hwblk.h>
28#include <cpu/sh7723.h> 28#include <cpu/sh7723.h>
29 29
30/* SH7723 registers */ 30/* SH7723 registers */
@@ -34,6 +34,9 @@
34#define SCLKBCR 0xa415000c 34#define SCLKBCR 0xa415000c
35#define IRDACLKCR 0xa4150018 35#define IRDACLKCR 0xa4150018
36#define PLLCR 0xa4150024 36#define PLLCR 0xa4150024
37#define MSTPCR0 0xa4150030
38#define MSTPCR1 0xa4150034
39#define MSTPCR2 0xa4150038
37#define DLLFRQ 0xa4150050 40#define DLLFRQ 0xa4150050
38 41
39/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 42/* Fixed 32 KHz root clock for RTC and Power Management purposes */
@@ -149,55 +152,55 @@ struct clk div6_clks[DIV6_NR] = {
149 152
150static struct clk mstp_clks[] = { 153static struct clk mstp_clks[] = {
151 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 154 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
152 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 155 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 156 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
154 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 157 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
155 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 158 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
156 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 159 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
157 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 160 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
158 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 161 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
159 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 162 [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),
160 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 163 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
161 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 164 [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
162 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 165 [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
163 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 166 [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
164 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 167 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
165 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 168 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
166 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 169 [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),
167 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 170 [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
168 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0), 171 [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
169 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 172 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
170 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 173 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
171 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 174 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
172 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 175 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
173 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 176 [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
174 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 177 [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
175 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 178 [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
176 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 179 [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),
177 SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0), 180 [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0),
178 181
179 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0), 182 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
180 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 183 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
181 184
182 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0), 185 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0),
183 SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0), 186 [HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
184 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 187 [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
185 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 188 [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
186 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 189 [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
187 SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 190 [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT),
188 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 191 [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
189 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 192 [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
190 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 193 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
191 SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0), 194 [HWBLK_USB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 11, 0),
192 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 195 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 10, 0),
193 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0), 196 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
194 SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0), 197 [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
195 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 198 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
196 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0), 199 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
197 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0), 200 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
198 SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0), 201 [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
199 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 202 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
200 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 203 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
201}; 204};
202 205
203static struct clk_lookup lookups[] = { 206static struct clk_lookup lookups[] = {
@@ -229,80 +232,17 @@ static struct clk_lookup lookups[] = {
229 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), 232 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
230 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 233 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
231 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 234 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
232 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 235 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
233 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 236 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
234 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 237 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
235 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 238 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
236 {
237 /* TMU0 */
238 .dev_id = "sh_tmu.0",
239 .con_id = "tmu_fck",
240 .clk = &mstp_clks[HWBLK_TMU0],
241 }, {
242 /* TMU1 */
243 .dev_id = "sh_tmu.1",
244 .con_id = "tmu_fck",
245 .clk = &mstp_clks[HWBLK_TMU0],
246 }, {
247 /* TMU2 */
248 .dev_id = "sh_tmu.2",
249 .con_id = "tmu_fck",
250 .clk = &mstp_clks[HWBLK_TMU0],
251 },
252 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 239 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
253 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 240 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
254 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 241 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
255 {
256 /* TMU3 */
257 .dev_id = "sh_tmu.3",
258 .con_id = "tmu_fck",
259 .clk = &mstp_clks[HWBLK_TMU1],
260 }, {
261 /* TMU4 */
262 .dev_id = "sh_tmu.4",
263 .con_id = "tmu_fck",
264 .clk = &mstp_clks[HWBLK_TMU1],
265 }, {
266 /* TMU5 */
267 .dev_id = "sh_tmu.5",
268 .con_id = "tmu_fck",
269 .clk = &mstp_clks[HWBLK_TMU1],
270 },
271 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), 242 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
272 { 243 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]),
273 /* SCIF0 */ 244 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]),
274 .dev_id = "sh-sci.0", 245 CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[HWBLK_MERAM]),
275 .con_id = "sci_fck",
276 .clk = &mstp_clks[HWBLK_SCIF0],
277 }, {
278 /* SCIF1 */
279 .dev_id = "sh-sci.1",
280 .con_id = "sci_fck",
281 .clk = &mstp_clks[HWBLK_SCIF1],
282 }, {
283 /* SCIF2 */
284 .dev_id = "sh-sci.2",
285 .con_id = "sci_fck",
286 .clk = &mstp_clks[HWBLK_SCIF2],
287 }, {
288 /* SCIF3 */
289 .dev_id = "sh-sci.3",
290 .con_id = "sci_fck",
291 .clk = &mstp_clks[HWBLK_SCIF3],
292 }, {
293 /* SCIF4 */
294 .dev_id = "sh-sci.4",
295 .con_id = "sci_fck",
296 .clk = &mstp_clks[HWBLK_SCIF4],
297 }, {
298 /* SCIF5 */
299 .dev_id = "sh-sci.5",
300 .con_id = "sci_fck",
301 .clk = &mstp_clks[HWBLK_SCIF5],
302 },
303 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
304 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
305 CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
306 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]), 246 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
307 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 247 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
308 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 248 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
@@ -311,19 +251,34 @@ static struct clk_lookup lookups[] = {
311 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 251 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
312 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), 252 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
313 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]), 253 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
314 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 254 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]),
315 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 255 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]),
316 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 256 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
317 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]), 257 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
318 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 258 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
319 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]), 259 CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
320 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]), 260 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
321 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 261 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
322 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), 262 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
323 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]), 263 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]),
324 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]), 264 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
325 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 265 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
326 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 266
267 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU0]),
268 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU0]),
269 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU0]),
270 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
271 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
272 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
273
274 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
275 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
276 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
277 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
278 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
279 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
280
281 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
327}; 282};
328 283
329int __init arch_clk_init(void) 284int __init arch_clk_init(void)
@@ -356,7 +311,7 @@ int __init arch_clk_init(void)
356 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 311 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
357 312
358 if (!ret) 313 if (!ret)
359 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 314 ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
360 315
361 return ret; 316 return ret;
362} 317}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 8668f557e0ac..b3c039a5064a 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -23,8 +23,8 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26#include <linux/sh_clk.h>
26#include <asm/clock.h> 27#include <asm/clock.h>
27#include <asm/hwblk.h>
28#include <cpu/sh7724.h> 28#include <cpu/sh7724.h>
29 29
30/* SH7724 registers */ 30/* SH7724 registers */
@@ -35,6 +35,9 @@
35#define FCLKBCR 0xa415000c 35#define FCLKBCR 0xa415000c
36#define IRDACLKCR 0xa4150018 36#define IRDACLKCR 0xa4150018
37#define PLLCR 0xa4150024 37#define PLLCR 0xa4150024
38#define MSTPCR0 0xa4150030
39#define MSTPCR1 0xa4150034
40#define MSTPCR2 0xa4150038
38#define SPUCLKCR 0xa415003c 41#define SPUCLKCR 0xa415003c
39#define FLLFRQ 0xa4150050 42#define FLLFRQ 0xa4150050
40#define LSTATS 0xa4150060 43#define LSTATS 0xa4150060
@@ -111,13 +114,16 @@ static struct clk div3_clk = {
111 .parent = &pll_clk, 114 .parent = &pll_clk,
112}; 115};
113 116
114/* External input clock (pin name: FSIMCKA/FSIMCKB ) */ 117/* External input clock (pin name: FSIMCKA/FSIMCKB/DV_CLKI ) */
115struct clk sh7724_fsimcka_clk = { 118struct clk sh7724_fsimcka_clk = {
116}; 119};
117 120
118struct clk sh7724_fsimckb_clk = { 121struct clk sh7724_fsimckb_clk = {
119}; 122};
120 123
124struct clk sh7724_dv_clki = {
125};
126
121static struct clk *main_clks[] = { 127static struct clk *main_clks[] = {
122 &r_clk, 128 &r_clk,
123 &extal_clk, 129 &extal_clk,
@@ -126,6 +132,7 @@ static struct clk *main_clks[] = {
126 &div3_clk, 132 &div3_clk,
127 &sh7724_fsimcka_clk, 133 &sh7724_fsimcka_clk,
128 &sh7724_fsimckb_clk, 134 &sh7724_fsimckb_clk,
135 &sh7724_dv_clki,
129}; 136};
130 137
131static void div4_kick(struct clk *clk) 138static void div4_kick(struct clk *clk)
@@ -163,17 +170,20 @@ struct clk div4_clks[DIV4_NR] = {
163 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 170 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
164}; 171};
165 172
166enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR }; 173enum { DIV6_V, DIV6_I, DIV6_S, DIV6_FA, DIV6_FB, DIV6_NR };
167 174
168static struct clk div6_clks[DIV6_NR] = { 175/* Indices are important - they are the actual src selecting values */
169 [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), 176static struct clk *common_parent[] = {
170 [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0), 177 [0] = &div3_clk,
171 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), 178 [1] = NULL,
172}; 179};
173 180
174enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR }; 181static struct clk *vclkcr_parent[8] = {
182 [0] = &div3_clk,
183 [2] = &sh7724_dv_clki,
184 [4] = &extal_clk,
185};
175 186
176/* Indices are important - they are the actual src selecting values */
177static struct clk *fclkacr_parent[] = { 187static struct clk *fclkacr_parent[] = {
178 [0] = &div3_clk, 188 [0] = &div3_clk,
179 [1] = NULL, 189 [1] = NULL,
@@ -188,68 +198,74 @@ static struct clk *fclkbcr_parent[] = {
188 [3] = NULL, 198 [3] = NULL,
189}; 199};
190 200
191static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { 201static struct clk div6_clks[DIV6_NR] = {
192 [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0, 202 [DIV6_V] = SH_CLK_DIV6_EXT(VCLKCR, 0,
203 vclkcr_parent, ARRAY_SIZE(vclkcr_parent), 12, 3),
204 [DIV6_I] = SH_CLK_DIV6_EXT(IRDACLKCR, 0,
205 common_parent, ARRAY_SIZE(common_parent), 6, 1),
206 [DIV6_S] = SH_CLK_DIV6_EXT(SPUCLKCR, CLK_ENABLE_ON_INIT,
207 common_parent, ARRAY_SIZE(common_parent), 6, 1),
208 [DIV6_FA] = SH_CLK_DIV6_EXT(FCLKACR, 0,
193 fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2), 209 fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
194 [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0, 210 [DIV6_FB] = SH_CLK_DIV6_EXT(FCLKBCR, 0,
195 fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2), 211 fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
196}; 212};
197 213
198static struct clk mstp_clks[HWBLK_NR] = { 214static struct clk mstp_clks[HWBLK_NR] = {
199 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 215 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
200 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 216 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
201 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 217 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
202 SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 218 [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
203 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 219 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
204 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 220 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
205 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 221 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
206 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT), 222 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
207 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 223 [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),
208 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 224 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
209 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 225 [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
210 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 226 [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
211 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 227 [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
212 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 228 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
213 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 229 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
214 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 230 [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),
215 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 231 [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
216 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 232 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
217 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 233 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
218 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 234 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
219 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 235 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
220 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 236 [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
221 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 237 [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
222 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 238 [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
223 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 239 [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),
224 240
225 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 241 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0),
226 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 242 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0),
227 SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0), 243 [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
228 SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0), 244 [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
229 245
230 SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0), 246 [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0),
231 SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0), 247 [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0),
232 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0), 248 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0),
233 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 249 [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
234 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 250 [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
235 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 251 [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
236 SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0), 252 [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0),
237 SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0), 253 [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0),
238 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 254 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0),
239 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 255 [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
240 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 256 [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
241 SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0), 257 [HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0),
242 SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0), 258 [HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0),
243 SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0), 259 [HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0),
244 SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0), 260 [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0),
245 SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0), 261 [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
246 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), 262 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
247 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 263 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
248 SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0), 264 [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
249 SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0), 265 [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
250 SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0), 266 [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
251 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 267 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
252 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 268 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
253}; 269};
254 270
255static struct clk_lookup lookups[] = { 271static struct clk_lookup lookups[] = {
@@ -269,8 +285,8 @@ static struct clk_lookup lookups[] = {
269 285
270 /* DIV6 clocks */ 286 /* DIV6 clocks */
271 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 287 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
272 CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]), 288 CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
273 CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]), 289 CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
274 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), 290 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
275 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), 291 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
276 292
@@ -283,7 +299,7 @@ static struct clk_lookup lookups[] = {
283 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), 299 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
284 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 300 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
285 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 301 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
286 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 302 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
287 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 303 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
288 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 304 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
289 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 305 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
@@ -294,26 +310,26 @@ static struct clk_lookup lookups[] = {
294 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]), 310 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
295 311
296 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 312 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
297 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 313 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
298 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 314 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
299 315
300 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]), 316 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
301 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]), 317 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
302 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]), 318 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
303 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]), 319 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
304 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]), 320 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
305 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]), 321 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
306 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]), 322 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
307 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]), 323 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
308 324
309 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]), 325 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]),
310 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]), 326 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]),
311 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 327 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
312 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 328 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
313 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]), 329 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]),
314 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]), 330 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]),
315 CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]), 331 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[HWBLK_MMC]),
316 CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]), 332 CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[HWBLK_ETHER]),
317 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 333 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
318 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), 334 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
319 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 335 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
@@ -321,20 +337,20 @@ static struct clk_lookup lookups[] = {
321 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]), 337 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
322 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]), 338 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
323 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 339 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
324 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 340 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]),
325 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 341 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]),
326 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]), 342 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
327 CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]), 343 CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[HWBLK_CEU1]),
328 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]), 344 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
329 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]), 345 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
330 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]), 346 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
331 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), 347 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
332 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 348 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
333 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]), 349 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
334 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]), 350 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU0]),
335 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]), 351 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
336 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 352 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
337 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 353 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
338}; 354};
339 355
340int __init arch_clk_init(void) 356int __init arch_clk_init(void)
@@ -356,13 +372,10 @@ int __init arch_clk_init(void)
356 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 372 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
357 373
358 if (!ret) 374 if (!ret)
359 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 375 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
360
361 if (!ret)
362 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
363 376
364 if (!ret) 377 if (!ret)
365 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 378 ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
366 379
367 return ret; 380 return ret;
368} 381}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index 19222dae8233..0fbff1422f54 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -129,7 +129,7 @@ static struct clk_lookup lookups[] = {
129 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP110]), 129 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP110]),
130 130
131 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]), 131 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]),
132 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]), 132 CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP102]),
133 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]), 133 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
134}; 134};
135 135
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
deleted file mode 100644
index a288b5d92341..000000000000
--- a/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
3 *
4 * SH7722 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7722.h>
27
28/* SH7722 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7722 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7722_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7722_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_URAM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_XYMEM] = HWBLK(MSTPCR0, 26, CORE_AREA),
48 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
49 [HWBLK_DMAC] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
50 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
51 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
52 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
53 [HWBLK_TMU] = HWBLK(MSTPCR0, 15, CORE_AREA),
54 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
55 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
56 [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
57 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 7, CORE_AREA),
58 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 6, CORE_AREA),
59 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 5, CORE_AREA),
60 [HWBLK_SIO] = HWBLK(MSTPCR0, 3, CORE_AREA),
61 [HWBLK_SIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
62 [HWBLK_SIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
63
64 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
65 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
66
67 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
68 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
69 [HWBLK_SDHI] = HWBLK(MSTPCR2, 18, CORE_AREA),
70 [HWBLK_SIM] = HWBLK(MSTPCR2, 16, CORE_AREA),
71 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
72 [HWBLK_TSIF] = HWBLK(MSTPCR2, 13, SUB_AREA),
73 [HWBLK_USBF] = HWBLK(MSTPCR2, 11, CORE_AREA),
74 [HWBLK_2DG] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
75 [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
76 [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
77 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
78 [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
79 [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
80 [HWBLK_VEU] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
81 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
82 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
83};
84
85static struct hwblk_info sh7722_hwblk_info = {
86 .areas = sh7722_hwblk_area,
87 .nr_areas = ARRAY_SIZE(sh7722_hwblk_area),
88 .hwblks = sh7722_hwblk,
89 .nr_hwblks = ARRAY_SIZE(sh7722_hwblk),
90};
91
92int arch_hwblk_sleep_mode(void)
93{
94 if (!sh7722_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
95 return SUSP_SH_STANDBY | SUSP_SH_SF;
96
97 if (!sh7722_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
98 return SUSP_SH_SLEEP | SUSP_SH_SF;
99
100 return SUSP_SH_SLEEP;
101}
102
103int __init arch_hwblk_init(void)
104{
105 return hwblk_register(&sh7722_hwblk_info);
106}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
deleted file mode 100644
index a7f4684d2032..000000000000
--- a/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
3 *
4 * SH7723 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7723.h>
27
28/* SH7723 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7723 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7723_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7723_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_L2C] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
49 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
50 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
51 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
52 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
53 [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
54 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
55 [HWBLK_SUBC] = HWBLK(MSTPCR0, 16, CORE_AREA),
56 [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59 [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60 [HWBLK_TMU1] = HWBLK(MSTPCR0, 11, CORE_AREA),
61 [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
62 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
63 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
64 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
65 [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
66 [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
67 [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
68 [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
69 [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
70 [HWBLK_MERAM] = HWBLK(MSTPCR0, 0, CORE_AREA),
71
72 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
74
75 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
76 [HWBLK_ADC] = HWBLK(MSTPCR2, 27, CORE_AREA),
77 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
78 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
79 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
80 [HWBLK_ICB] = HWBLK(MSTPCR2, 21, CORE_AREA_BM),
81 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
82 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
83 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
84 [HWBLK_USB] = HWBLK(MSTPCR2, 11, CORE_AREA),
85 [HWBLK_2DG] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
86 [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
87 [HWBLK_VEU2H1] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
88 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
89 [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
90 [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
91 [HWBLK_VEU2H0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
92 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
93 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
94};
95
96static struct hwblk_info sh7723_hwblk_info = {
97 .areas = sh7723_hwblk_area,
98 .nr_areas = ARRAY_SIZE(sh7723_hwblk_area),
99 .hwblks = sh7723_hwblk,
100 .nr_hwblks = ARRAY_SIZE(sh7723_hwblk),
101};
102
103int arch_hwblk_sleep_mode(void)
104{
105 if (!sh7723_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
106 return SUSP_SH_STANDBY | SUSP_SH_SF;
107
108 if (!sh7723_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
109 return SUSP_SH_SLEEP | SUSP_SH_SF;
110
111 return SUSP_SH_SLEEP;
112}
113
114int __init arch_hwblk_init(void)
115{
116 return hwblk_register(&sh7723_hwblk_info);
117}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
deleted file mode 100644
index 1613ad6013c3..000000000000
--- a/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
3 *
4 * SH7724 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7724.h>
27
28/* SH7724 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7724 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7724_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7724_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_RSMEM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48 [HWBLK_L2C] = HWBLK(MSTPCR0, 26, CORE_AREA),
49 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
50 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
51 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
52 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
53 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
54 [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
55 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
56 [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59 [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60 [HWBLK_TMU1] = HWBLK(MSTPCR0, 10, CORE_AREA),
61 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
62 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
63 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
64 [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
65 [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
66 [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
67 [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
68 [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
69
70 [HWBLK_KEYSC] = HWBLK(MSTPCR1, 12, SUB_AREA),
71 [HWBLK_RTC] = HWBLK(MSTPCR1, 11, SUB_AREA),
72 [HWBLK_IIC0] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_IIC1] = HWBLK(MSTPCR1, 8, CORE_AREA),
74
75 [HWBLK_MMC] = HWBLK(MSTPCR2, 29, CORE_AREA),
76 [HWBLK_ETHER] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
77 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 26, CORE_AREA_BM),
78 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
79 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
80 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
81 [HWBLK_USB1] = HWBLK(MSTPCR2, 21, CORE_AREA),
82 [HWBLK_USB0] = HWBLK(MSTPCR2, 20, CORE_AREA),
83 [HWBLK_2DG] = HWBLK(MSTPCR2, 19, CORE_AREA_BM),
84 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
85 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
86 [HWBLK_VEU1] = HWBLK(MSTPCR2, 15, CORE_AREA_BM),
87 [HWBLK_CEU1] = HWBLK(MSTPCR2, 13, CORE_AREA_BM),
88 [HWBLK_BEU1] = HWBLK(MSTPCR2, 12, CORE_AREA_BM),
89 [HWBLK_2DDMAC] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
90 [HWBLK_SPU] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
91 [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
92 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
93 [HWBLK_BEU0] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
94 [HWBLK_CEU0] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
95 [HWBLK_VEU0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
96 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
97 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
98};
99
100static struct hwblk_info sh7724_hwblk_info = {
101 .areas = sh7724_hwblk_area,
102 .nr_areas = ARRAY_SIZE(sh7724_hwblk_area),
103 .hwblks = sh7724_hwblk,
104 .nr_hwblks = ARRAY_SIZE(sh7724_hwblk),
105};
106
107int arch_hwblk_sleep_mode(void)
108{
109 if (!sh7724_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
110 return SUSP_SH_STANDBY | SUSP_SH_SF;
111
112 if (!sh7724_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
113 return SUSP_SH_SLEEP | SUSP_SH_SF;
114
115 return SUSP_SH_SLEEP;
116}
117
118int __init arch_hwblk_init(void)
119{
120 return hwblk_register(&sh7724_hwblk_info);
121}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 278a0e572158..8420d4bc8bfc 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -146,7 +146,7 @@ static struct resource sh7722_dmae_resources[] = {
146 .flags = IORESOURCE_MEM, 146 .flags = IORESOURCE_MEM,
147 }, 147 },
148 { 148 {
149 /* DMA error IRQ */ 149 .name = "error_irq",
150 .start = 78, 150 .start = 78,
151 .end = 78, 151 .end = 78,
152 .flags = IORESOURCE_IRQ, 152 .flags = IORESOURCE_IRQ,
@@ -173,9 +173,6 @@ struct platform_device dma_device = {
173 .dev = { 173 .dev = {
174 .platform_data = &dma_platform_data, 174 .platform_data = &dma_platform_data,
175 }, 175 },
176 .archdata = {
177 .hwblk_id = HWBLK_DMAC,
178 },
179}; 176};
180 177
181/* Serial */ 178/* Serial */
@@ -264,9 +261,6 @@ static struct platform_device rtc_device = {
264 .id = -1, 261 .id = -1,
265 .num_resources = ARRAY_SIZE(rtc_resources), 262 .num_resources = ARRAY_SIZE(rtc_resources),
266 .resource = rtc_resources, 263 .resource = rtc_resources,
267 .archdata = {
268 .hwblk_id = HWBLK_RTC,
269 },
270}; 264};
271 265
272static struct m66592_platdata usbf_platdata = { 266static struct m66592_platdata usbf_platdata = {
@@ -297,9 +291,6 @@ static struct platform_device usbf_device = {
297 }, 291 },
298 .num_resources = ARRAY_SIZE(usbf_resources), 292 .num_resources = ARRAY_SIZE(usbf_resources),
299 .resource = usbf_resources, 293 .resource = usbf_resources,
300 .archdata = {
301 .hwblk_id = HWBLK_USBF,
302 },
303}; 294};
304 295
305static struct resource iic_resources[] = { 296static struct resource iic_resources[] = {
@@ -321,9 +312,6 @@ static struct platform_device iic_device = {
321 .id = 0, /* "i2c0" clock */ 312 .id = 0, /* "i2c0" clock */
322 .num_resources = ARRAY_SIZE(iic_resources), 313 .num_resources = ARRAY_SIZE(iic_resources),
323 .resource = iic_resources, 314 .resource = iic_resources,
324 .archdata = {
325 .hwblk_id = HWBLK_IIC,
326 },
327}; 315};
328 316
329static struct uio_info vpu_platform_data = { 317static struct uio_info vpu_platform_data = {
@@ -352,9 +340,6 @@ static struct platform_device vpu_device = {
352 }, 340 },
353 .resource = vpu_resources, 341 .resource = vpu_resources,
354 .num_resources = ARRAY_SIZE(vpu_resources), 342 .num_resources = ARRAY_SIZE(vpu_resources),
355 .archdata = {
356 .hwblk_id = HWBLK_VPU,
357 },
358}; 343};
359 344
360static struct uio_info veu_platform_data = { 345static struct uio_info veu_platform_data = {
@@ -383,9 +368,6 @@ static struct platform_device veu_device = {
383 }, 368 },
384 .resource = veu_resources, 369 .resource = veu_resources,
385 .num_resources = ARRAY_SIZE(veu_resources), 370 .num_resources = ARRAY_SIZE(veu_resources),
386 .archdata = {
387 .hwblk_id = HWBLK_VEU,
388 },
389}; 371};
390 372
391static struct uio_info jpu_platform_data = { 373static struct uio_info jpu_platform_data = {
@@ -414,9 +396,6 @@ static struct platform_device jpu_device = {
414 }, 396 },
415 .resource = jpu_resources, 397 .resource = jpu_resources,
416 .num_resources = ARRAY_SIZE(jpu_resources), 398 .num_resources = ARRAY_SIZE(jpu_resources),
417 .archdata = {
418 .hwblk_id = HWBLK_JPU,
419 },
420}; 399};
421 400
422static struct sh_timer_config cmt_platform_data = { 401static struct sh_timer_config cmt_platform_data = {
@@ -446,9 +425,6 @@ static struct platform_device cmt_device = {
446 }, 425 },
447 .resource = cmt_resources, 426 .resource = cmt_resources,
448 .num_resources = ARRAY_SIZE(cmt_resources), 427 .num_resources = ARRAY_SIZE(cmt_resources),
449 .archdata = {
450 .hwblk_id = HWBLK_CMT,
451 },
452}; 428};
453 429
454static struct sh_timer_config tmu0_platform_data = { 430static struct sh_timer_config tmu0_platform_data = {
@@ -477,9 +453,6 @@ static struct platform_device tmu0_device = {
477 }, 453 },
478 .resource = tmu0_resources, 454 .resource = tmu0_resources,
479 .num_resources = ARRAY_SIZE(tmu0_resources), 455 .num_resources = ARRAY_SIZE(tmu0_resources),
480 .archdata = {
481 .hwblk_id = HWBLK_TMU,
482 },
483}; 456};
484 457
485static struct sh_timer_config tmu1_platform_data = { 458static struct sh_timer_config tmu1_platform_data = {
@@ -508,9 +481,6 @@ static struct platform_device tmu1_device = {
508 }, 481 },
509 .resource = tmu1_resources, 482 .resource = tmu1_resources,
510 .num_resources = ARRAY_SIZE(tmu1_resources), 483 .num_resources = ARRAY_SIZE(tmu1_resources),
511 .archdata = {
512 .hwblk_id = HWBLK_TMU,
513 },
514}; 484};
515 485
516static struct sh_timer_config tmu2_platform_data = { 486static struct sh_timer_config tmu2_platform_data = {
@@ -538,9 +508,6 @@ static struct platform_device tmu2_device = {
538 }, 508 },
539 .resource = tmu2_resources, 509 .resource = tmu2_resources,
540 .num_resources = ARRAY_SIZE(tmu2_resources), 510 .num_resources = ARRAY_SIZE(tmu2_resources),
541 .archdata = {
542 .hwblk_id = HWBLK_TMU,
543 },
544}; 511};
545 512
546static struct siu_platform siu_platform_data = { 513static struct siu_platform siu_platform_data = {
@@ -571,9 +538,6 @@ static struct platform_device siu_device = {
571 }, 538 },
572 .resource = siu_resources, 539 .resource = siu_resources,
573 .num_resources = ARRAY_SIZE(siu_resources), 540 .num_resources = ARRAY_SIZE(siu_resources),
574 .archdata = {
575 .hwblk_id = HWBLK_SIU,
576 },
577}; 541};
578 542
579static struct platform_device *sh7722_devices[] __initdata = { 543static struct platform_device *sh7722_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 3c2810d8f72e..a188c9ea4393 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -158,9 +158,6 @@ static struct platform_device vpu_device = {
158 }, 158 },
159 .resource = vpu_resources, 159 .resource = vpu_resources,
160 .num_resources = ARRAY_SIZE(vpu_resources), 160 .num_resources = ARRAY_SIZE(vpu_resources),
161 .archdata = {
162 .hwblk_id = HWBLK_VPU,
163 },
164}; 161};
165 162
166static struct uio_info veu0_platform_data = { 163static struct uio_info veu0_platform_data = {
@@ -189,9 +186,6 @@ static struct platform_device veu0_device = {
189 }, 186 },
190 .resource = veu0_resources, 187 .resource = veu0_resources,
191 .num_resources = ARRAY_SIZE(veu0_resources), 188 .num_resources = ARRAY_SIZE(veu0_resources),
192 .archdata = {
193 .hwblk_id = HWBLK_VEU2H0,
194 },
195}; 189};
196 190
197static struct uio_info veu1_platform_data = { 191static struct uio_info veu1_platform_data = {
@@ -220,9 +214,6 @@ static struct platform_device veu1_device = {
220 }, 214 },
221 .resource = veu1_resources, 215 .resource = veu1_resources,
222 .num_resources = ARRAY_SIZE(veu1_resources), 216 .num_resources = ARRAY_SIZE(veu1_resources),
223 .archdata = {
224 .hwblk_id = HWBLK_VEU2H1,
225 },
226}; 217};
227 218
228static struct sh_timer_config cmt_platform_data = { 219static struct sh_timer_config cmt_platform_data = {
@@ -252,9 +243,6 @@ static struct platform_device cmt_device = {
252 }, 243 },
253 .resource = cmt_resources, 244 .resource = cmt_resources,
254 .num_resources = ARRAY_SIZE(cmt_resources), 245 .num_resources = ARRAY_SIZE(cmt_resources),
255 .archdata = {
256 .hwblk_id = HWBLK_CMT,
257 },
258}; 246};
259 247
260static struct sh_timer_config tmu0_platform_data = { 248static struct sh_timer_config tmu0_platform_data = {
@@ -283,9 +271,6 @@ static struct platform_device tmu0_device = {
283 }, 271 },
284 .resource = tmu0_resources, 272 .resource = tmu0_resources,
285 .num_resources = ARRAY_SIZE(tmu0_resources), 273 .num_resources = ARRAY_SIZE(tmu0_resources),
286 .archdata = {
287 .hwblk_id = HWBLK_TMU0,
288 },
289}; 274};
290 275
291static struct sh_timer_config tmu1_platform_data = { 276static struct sh_timer_config tmu1_platform_data = {
@@ -314,9 +299,6 @@ static struct platform_device tmu1_device = {
314 }, 299 },
315 .resource = tmu1_resources, 300 .resource = tmu1_resources,
316 .num_resources = ARRAY_SIZE(tmu1_resources), 301 .num_resources = ARRAY_SIZE(tmu1_resources),
317 .archdata = {
318 .hwblk_id = HWBLK_TMU0,
319 },
320}; 302};
321 303
322static struct sh_timer_config tmu2_platform_data = { 304static struct sh_timer_config tmu2_platform_data = {
@@ -344,9 +326,6 @@ static struct platform_device tmu2_device = {
344 }, 326 },
345 .resource = tmu2_resources, 327 .resource = tmu2_resources,
346 .num_resources = ARRAY_SIZE(tmu2_resources), 328 .num_resources = ARRAY_SIZE(tmu2_resources),
347 .archdata = {
348 .hwblk_id = HWBLK_TMU0,
349 },
350}; 329};
351 330
352static struct sh_timer_config tmu3_platform_data = { 331static struct sh_timer_config tmu3_platform_data = {
@@ -374,9 +353,6 @@ static struct platform_device tmu3_device = {
374 }, 353 },
375 .resource = tmu3_resources, 354 .resource = tmu3_resources,
376 .num_resources = ARRAY_SIZE(tmu3_resources), 355 .num_resources = ARRAY_SIZE(tmu3_resources),
377 .archdata = {
378 .hwblk_id = HWBLK_TMU1,
379 },
380}; 356};
381 357
382static struct sh_timer_config tmu4_platform_data = { 358static struct sh_timer_config tmu4_platform_data = {
@@ -404,9 +380,6 @@ static struct platform_device tmu4_device = {
404 }, 380 },
405 .resource = tmu4_resources, 381 .resource = tmu4_resources,
406 .num_resources = ARRAY_SIZE(tmu4_resources), 382 .num_resources = ARRAY_SIZE(tmu4_resources),
407 .archdata = {
408 .hwblk_id = HWBLK_TMU1,
409 },
410}; 383};
411 384
412static struct sh_timer_config tmu5_platform_data = { 385static struct sh_timer_config tmu5_platform_data = {
@@ -434,9 +407,6 @@ static struct platform_device tmu5_device = {
434 }, 407 },
435 .resource = tmu5_resources, 408 .resource = tmu5_resources,
436 .num_resources = ARRAY_SIZE(tmu5_resources), 409 .num_resources = ARRAY_SIZE(tmu5_resources),
437 .archdata = {
438 .hwblk_id = HWBLK_TMU1,
439 },
440}; 410};
441 411
442static struct resource rtc_resources[] = { 412static struct resource rtc_resources[] = {
@@ -467,9 +437,6 @@ static struct platform_device rtc_device = {
467 .id = -1, 437 .id = -1,
468 .num_resources = ARRAY_SIZE(rtc_resources), 438 .num_resources = ARRAY_SIZE(rtc_resources),
469 .resource = rtc_resources, 439 .resource = rtc_resources,
470 .archdata = {
471 .hwblk_id = HWBLK_RTC,
472 },
473}; 440};
474 441
475static struct r8a66597_platdata r8a66597_data = { 442static struct r8a66597_platdata r8a66597_data = {
@@ -499,9 +466,6 @@ static struct platform_device sh7723_usb_host_device = {
499 }, 466 },
500 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 467 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources),
501 .resource = sh7723_usb_host_resources, 468 .resource = sh7723_usb_host_resources,
502 .archdata = {
503 .hwblk_id = HWBLK_USB,
504 },
505}; 469};
506 470
507static struct resource iic_resources[] = { 471static struct resource iic_resources[] = {
@@ -523,9 +487,6 @@ static struct platform_device iic_device = {
523 .id = 0, /* "i2c0" clock */ 487 .id = 0, /* "i2c0" clock */
524 .num_resources = ARRAY_SIZE(iic_resources), 488 .num_resources = ARRAY_SIZE(iic_resources),
525 .resource = iic_resources, 489 .resource = iic_resources,
526 .archdata = {
527 .hwblk_id = HWBLK_IIC,
528 },
529}; 490};
530 491
531static struct platform_device *sh7723_devices[] __initdata = { 492static struct platform_device *sh7723_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index a37dd72c3671..4c671cfe68aa 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -214,7 +214,7 @@ static struct resource sh7724_dmae0_resources[] = {
214 .flags = IORESOURCE_MEM, 214 .flags = IORESOURCE_MEM,
215 }, 215 },
216 { 216 {
217 /* DMA error IRQ */ 217 .name = "error_irq",
218 .start = 78, 218 .start = 78,
219 .end = 78, 219 .end = 78,
220 .flags = IORESOURCE_IRQ, 220 .flags = IORESOURCE_IRQ,
@@ -248,7 +248,7 @@ static struct resource sh7724_dmae1_resources[] = {
248 .flags = IORESOURCE_MEM, 248 .flags = IORESOURCE_MEM,
249 }, 249 },
250 { 250 {
251 /* DMA error IRQ */ 251 .name = "error_irq",
252 .start = 74, 252 .start = 74,
253 .end = 74, 253 .end = 74,
254 .flags = IORESOURCE_IRQ, 254 .flags = IORESOURCE_IRQ,
@@ -275,9 +275,6 @@ static struct platform_device dma0_device = {
275 .dev = { 275 .dev = {
276 .platform_data = &dma_platform_data, 276 .platform_data = &dma_platform_data,
277 }, 277 },
278 .archdata = {
279 .hwblk_id = HWBLK_DMAC0,
280 },
281}; 278};
282 279
283static struct platform_device dma1_device = { 280static struct platform_device dma1_device = {
@@ -288,9 +285,6 @@ static struct platform_device dma1_device = {
288 .dev = { 285 .dev = {
289 .platform_data = &dma_platform_data, 286 .platform_data = &dma_platform_data,
290 }, 287 },
291 .archdata = {
292 .hwblk_id = HWBLK_DMAC1,
293 },
294}; 288};
295 289
296/* Serial */ 290/* Serial */
@@ -434,9 +428,6 @@ static struct platform_device rtc_device = {
434 .id = -1, 428 .id = -1,
435 .num_resources = ARRAY_SIZE(rtc_resources), 429 .num_resources = ARRAY_SIZE(rtc_resources),
436 .resource = rtc_resources, 430 .resource = rtc_resources,
437 .archdata = {
438 .hwblk_id = HWBLK_RTC,
439 },
440}; 431};
441 432
442/* I2C0 */ 433/* I2C0 */
@@ -459,9 +450,6 @@ static struct platform_device iic0_device = {
459 .id = 0, /* "i2c0" clock */ 450 .id = 0, /* "i2c0" clock */
460 .num_resources = ARRAY_SIZE(iic0_resources), 451 .num_resources = ARRAY_SIZE(iic0_resources),
461 .resource = iic0_resources, 452 .resource = iic0_resources,
462 .archdata = {
463 .hwblk_id = HWBLK_IIC0,
464 },
465}; 453};
466 454
467/* I2C1 */ 455/* I2C1 */
@@ -484,9 +472,6 @@ static struct platform_device iic1_device = {
484 .id = 1, /* "i2c1" clock */ 472 .id = 1, /* "i2c1" clock */
485 .num_resources = ARRAY_SIZE(iic1_resources), 473 .num_resources = ARRAY_SIZE(iic1_resources),
486 .resource = iic1_resources, 474 .resource = iic1_resources,
487 .archdata = {
488 .hwblk_id = HWBLK_IIC1,
489 },
490}; 475};
491 476
492/* VPU */ 477/* VPU */
@@ -516,9 +501,6 @@ static struct platform_device vpu_device = {
516 }, 501 },
517 .resource = vpu_resources, 502 .resource = vpu_resources,
518 .num_resources = ARRAY_SIZE(vpu_resources), 503 .num_resources = ARRAY_SIZE(vpu_resources),
519 .archdata = {
520 .hwblk_id = HWBLK_VPU,
521 },
522}; 504};
523 505
524/* VEU0 */ 506/* VEU0 */
@@ -548,9 +530,6 @@ static struct platform_device veu0_device = {
548 }, 530 },
549 .resource = veu0_resources, 531 .resource = veu0_resources,
550 .num_resources = ARRAY_SIZE(veu0_resources), 532 .num_resources = ARRAY_SIZE(veu0_resources),
551 .archdata = {
552 .hwblk_id = HWBLK_VEU0,
553 },
554}; 533};
555 534
556/* VEU1 */ 535/* VEU1 */
@@ -580,9 +559,6 @@ static struct platform_device veu1_device = {
580 }, 559 },
581 .resource = veu1_resources, 560 .resource = veu1_resources,
582 .num_resources = ARRAY_SIZE(veu1_resources), 561 .num_resources = ARRAY_SIZE(veu1_resources),
583 .archdata = {
584 .hwblk_id = HWBLK_VEU1,
585 },
586}; 562};
587 563
588/* BEU0 */ 564/* BEU0 */
@@ -612,9 +588,6 @@ static struct platform_device beu0_device = {
612 }, 588 },
613 .resource = beu0_resources, 589 .resource = beu0_resources,
614 .num_resources = ARRAY_SIZE(beu0_resources), 590 .num_resources = ARRAY_SIZE(beu0_resources),
615 .archdata = {
616 .hwblk_id = HWBLK_BEU0,
617 },
618}; 591};
619 592
620/* BEU1 */ 593/* BEU1 */
@@ -644,9 +617,6 @@ static struct platform_device beu1_device = {
644 }, 617 },
645 .resource = beu1_resources, 618 .resource = beu1_resources,
646 .num_resources = ARRAY_SIZE(beu1_resources), 619 .num_resources = ARRAY_SIZE(beu1_resources),
647 .archdata = {
648 .hwblk_id = HWBLK_BEU1,
649 },
650}; 620};
651 621
652static struct sh_timer_config cmt_platform_data = { 622static struct sh_timer_config cmt_platform_data = {
@@ -676,9 +646,6 @@ static struct platform_device cmt_device = {
676 }, 646 },
677 .resource = cmt_resources, 647 .resource = cmt_resources,
678 .num_resources = ARRAY_SIZE(cmt_resources), 648 .num_resources = ARRAY_SIZE(cmt_resources),
679 .archdata = {
680 .hwblk_id = HWBLK_CMT,
681 },
682}; 649};
683 650
684static struct sh_timer_config tmu0_platform_data = { 651static struct sh_timer_config tmu0_platform_data = {
@@ -707,9 +674,6 @@ static struct platform_device tmu0_device = {
707 }, 674 },
708 .resource = tmu0_resources, 675 .resource = tmu0_resources,
709 .num_resources = ARRAY_SIZE(tmu0_resources), 676 .num_resources = ARRAY_SIZE(tmu0_resources),
710 .archdata = {
711 .hwblk_id = HWBLK_TMU0,
712 },
713}; 677};
714 678
715static struct sh_timer_config tmu1_platform_data = { 679static struct sh_timer_config tmu1_platform_data = {
@@ -738,9 +702,6 @@ static struct platform_device tmu1_device = {
738 }, 702 },
739 .resource = tmu1_resources, 703 .resource = tmu1_resources,
740 .num_resources = ARRAY_SIZE(tmu1_resources), 704 .num_resources = ARRAY_SIZE(tmu1_resources),
741 .archdata = {
742 .hwblk_id = HWBLK_TMU0,
743 },
744}; 705};
745 706
746static struct sh_timer_config tmu2_platform_data = { 707static struct sh_timer_config tmu2_platform_data = {
@@ -768,9 +729,6 @@ static struct platform_device tmu2_device = {
768 }, 729 },
769 .resource = tmu2_resources, 730 .resource = tmu2_resources,
770 .num_resources = ARRAY_SIZE(tmu2_resources), 731 .num_resources = ARRAY_SIZE(tmu2_resources),
771 .archdata = {
772 .hwblk_id = HWBLK_TMU0,
773 },
774}; 732};
775 733
776 734
@@ -799,9 +757,6 @@ static struct platform_device tmu3_device = {
799 }, 757 },
800 .resource = tmu3_resources, 758 .resource = tmu3_resources,
801 .num_resources = ARRAY_SIZE(tmu3_resources), 759 .num_resources = ARRAY_SIZE(tmu3_resources),
802 .archdata = {
803 .hwblk_id = HWBLK_TMU1,
804 },
805}; 760};
806 761
807static struct sh_timer_config tmu4_platform_data = { 762static struct sh_timer_config tmu4_platform_data = {
@@ -829,9 +784,6 @@ static struct platform_device tmu4_device = {
829 }, 784 },
830 .resource = tmu4_resources, 785 .resource = tmu4_resources,
831 .num_resources = ARRAY_SIZE(tmu4_resources), 786 .num_resources = ARRAY_SIZE(tmu4_resources),
832 .archdata = {
833 .hwblk_id = HWBLK_TMU1,
834 },
835}; 787};
836 788
837static struct sh_timer_config tmu5_platform_data = { 789static struct sh_timer_config tmu5_platform_data = {
@@ -859,9 +811,6 @@ static struct platform_device tmu5_device = {
859 }, 811 },
860 .resource = tmu5_resources, 812 .resource = tmu5_resources,
861 .num_resources = ARRAY_SIZE(tmu5_resources), 813 .num_resources = ARRAY_SIZE(tmu5_resources),
862 .archdata = {
863 .hwblk_id = HWBLK_TMU1,
864 },
865}; 814};
866 815
867/* JPU */ 816/* JPU */
@@ -891,9 +840,6 @@ static struct platform_device jpu_device = {
891 }, 840 },
892 .resource = jpu_resources, 841 .resource = jpu_resources,
893 .num_resources = ARRAY_SIZE(jpu_resources), 842 .num_resources = ARRAY_SIZE(jpu_resources),
894 .archdata = {
895 .hwblk_id = HWBLK_JPU,
896 },
897}; 843};
898 844
899/* SPU2DSP0 */ 845/* SPU2DSP0 */
@@ -923,9 +869,6 @@ static struct platform_device spu0_device = {
923 }, 869 },
924 .resource = spu0_resources, 870 .resource = spu0_resources,
925 .num_resources = ARRAY_SIZE(spu0_resources), 871 .num_resources = ARRAY_SIZE(spu0_resources),
926 .archdata = {
927 .hwblk_id = HWBLK_SPU,
928 },
929}; 872};
930 873
931/* SPU2DSP1 */ 874/* SPU2DSP1 */
@@ -955,9 +898,6 @@ static struct platform_device spu1_device = {
955 }, 898 },
956 .resource = spu1_resources, 899 .resource = spu1_resources,
957 .num_resources = ARRAY_SIZE(spu1_resources), 900 .num_resources = ARRAY_SIZE(spu1_resources),
958 .archdata = {
959 .hwblk_id = HWBLK_SPU,
960 },
961}; 901};
962 902
963static struct platform_device *sh7724_devices[] __initdata = { 903static struct platform_device *sh7724_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 05559295d2ca..a7b2da6b3a1a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -465,6 +465,7 @@ static struct resource sh7757_dmae0_resources[] = {
465 .flags = IORESOURCE_MEM, 465 .flags = IORESOURCE_MEM,
466 }, 466 },
467 { 467 {
468 .name = "error_irq",
468 .start = 34, 469 .start = 34,
469 .end = 34, 470 .end = 34,
470 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 471 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
@@ -486,7 +487,7 @@ static struct resource sh7757_dmae1_resources[] = {
486 .flags = IORESOURCE_MEM, 487 .flags = IORESOURCE_MEM,
487 }, 488 },
488 { 489 {
489 /* DMA error */ 490 .name = "error_irq",
490 .start = 34, 491 .start = 34,
491 .end = 34, 492 .end = 34,
492 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 493 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
@@ -556,7 +557,7 @@ static struct resource sh7757_dmae2_resources[] = {
556 .flags = IORESOURCE_MEM, 557 .flags = IORESOURCE_MEM,
557 }, 558 },
558 { 559 {
559 /* DMA error */ 560 .name = "error_irq",
560 .start = 323, 561 .start = 323,
561 .end = 323, 562 .end = 323,
562 .flags = IORESOURCE_IRQ, 563 .flags = IORESOURCE_IRQ,
@@ -590,7 +591,7 @@ static struct resource sh7757_dmae3_resources[] = {
590 .flags = IORESOURCE_MEM, 591 .flags = IORESOURCE_MEM,
591 }, 592 },
592 { 593 {
593 /* DMA error */ 594 .name = "error_irq",
594 .start = 324, 595 .start = 324,
595 .end = 324, 596 .end = 324,
596 .flags = IORESOURCE_IRQ, 597 .flags = IORESOURCE_IRQ,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 3d4d2075c19a..d431b0052d0c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -322,6 +322,7 @@ static struct resource sh7780_dmae0_resources[] = {
322 }, 322 },
323 { 323 {
324 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */ 324 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
325 .name = "error_irq",
325 .start = 34, 326 .start = 34,
326 .end = 34, 327 .end = 34,
327 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 328 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
@@ -338,6 +339,7 @@ static struct resource sh7780_dmae1_resources[] = {
338 /* DMAC1 has no DMARS */ 339 /* DMAC1 has no DMARS */
339 { 340 {
340 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */ 341 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
342 .name = "error_irq",
341 .start = 46, 343 .start = 46,
342 .end = 46, 344 .end = 46,
343 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 345 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index b29e6340414a..81588ef15a6c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -376,6 +376,7 @@ static struct resource sh7785_dmae0_resources[] = {
376 }, 376 },
377 { 377 {
378 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */ 378 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
379 .name = "error_irq",
379 .start = 33, 380 .start = 33,
380 .end = 33, 381 .end = 33,
381 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 382 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
@@ -392,6 +393,7 @@ static struct resource sh7785_dmae1_resources[] = {
392 /* DMAC1 has no DMARS */ 393 /* DMAC1 has no DMARS */
393 { 394 {
394 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */ 395 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
396 .name = "error_irq",
395 .start = 52, 397 .start = 52,
396 .end = 52, 398 .end = 52,
397 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 399 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index dd5e709f9821..599022d73b28 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -518,7 +518,7 @@ static struct resource dmac0_resources[] = {
518 .end = 0xfe00900b, 518 .end = 0xfe00900b,
519 .flags = IORESOURCE_MEM, 519 .flags = IORESOURCE_MEM,
520 }, { 520 }, {
521 /* DMA error IRQ */ 521 .name = "error_irq",
522 .start = evt2irq(0x5c0), 522 .start = evt2irq(0x5c0),
523 .end = evt2irq(0x5c0), 523 .end = evt2irq(0x5c0),
524 .flags = IORESOURCE_IRQ, 524 .flags = IORESOURCE_IRQ,
diff --git a/arch/sh/kernel/cpu/shmobile/Makefile b/arch/sh/kernel/cpu/shmobile/Makefile
index a39f88ea1a85..e8a5111e848a 100644
--- a/arch/sh/kernel/cpu/shmobile/Makefile
+++ b/arch/sh/kernel/cpu/shmobile/Makefile
@@ -5,4 +5,3 @@
5# Power Management & Sleep mode 5# Power Management & Sleep mode
6obj-$(CONFIG_PM) += pm.o sleep.o 6obj-$(CONFIG_PM) += pm.o sleep.o
7obj-$(CONFIG_CPU_IDLE) += cpuidle.o 7obj-$(CONFIG_CPU_IDLE) += cpuidle.o
8obj-$(CONFIG_PM_RUNTIME) += pm_runtime.o
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
index 1cc257c9b1e3..6d62eb40e750 100644
--- a/arch/sh/kernel/cpu/shmobile/cpuidle.c
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -17,7 +17,6 @@
17#include <linux/export.h> 17#include <linux/export.h>
18#include <asm/suspend.h> 18#include <asm/suspend.h>
19#include <asm/uaccess.h> 19#include <asm/uaccess.h>
20#include <asm/hwblk.h>
21 20
22static unsigned long cpuidle_mode[] = { 21static unsigned long cpuidle_mode[] = {
23 SUSP_SH_SLEEP, /* regular sleep mode */ 22 SUSP_SH_SLEEP, /* regular sleep mode */
@@ -29,7 +28,7 @@ static int cpuidle_sleep_enter(struct cpuidle_device *dev,
29 struct cpuidle_driver *drv, 28 struct cpuidle_driver *drv,
30 int index) 29 int index)
31{ 30{
32 unsigned long allowed_mode = arch_hwblk_sleep_mode(); 31 unsigned long allowed_mode = SUSP_SH_SLEEP;
33 ktime_t before, after; 32 ktime_t before, after;
34 int requested_state = index; 33 int requested_state = index;
35 int allowed_state; 34 int allowed_state;
diff --git a/arch/sh/kernel/cpu/shmobile/pm_runtime.c b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
deleted file mode 100644
index bf280c812d2f..000000000000
--- a/arch/sh/kernel/cpu/shmobile/pm_runtime.c
+++ /dev/null
@@ -1,319 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/shmobile/pm_runtime.c
3 *
4 * Runtime PM support code for SuperH Mobile
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/pm_runtime.h>
16#include <linux/platform_device.h>
17#include <linux/mutex.h>
18#include <asm/hwblk.h>
19
20static DEFINE_SPINLOCK(hwblk_lock);
21static LIST_HEAD(hwblk_idle_list);
22static struct work_struct hwblk_work;
23
24extern struct hwblk_info *hwblk_info;
25
26static void platform_pm_runtime_not_idle(struct platform_device *pdev)
27{
28 unsigned long flags;
29
30 /* remove device from idle list */
31 spin_lock_irqsave(&hwblk_lock, flags);
32 if (test_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags)) {
33 list_del(&pdev->archdata.entry);
34 __clear_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags);
35 }
36 spin_unlock_irqrestore(&hwblk_lock, flags);
37}
38
39static int __platform_pm_runtime_resume(struct platform_device *pdev)
40{
41 struct device *d = &pdev->dev;
42 struct pdev_archdata *ad = &pdev->archdata;
43 int hwblk = ad->hwblk_id;
44 int ret = -ENOSYS;
45
46 dev_dbg(d, "__platform_pm_runtime_resume() [%d]\n", hwblk);
47
48 if (d->driver) {
49 hwblk_enable(hwblk_info, hwblk);
50 ret = 0;
51
52 if (test_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags)) {
53 if (d->driver->pm && d->driver->pm->runtime_resume)
54 ret = d->driver->pm->runtime_resume(d);
55
56 if (!ret)
57 clear_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
58 else
59 hwblk_disable(hwblk_info, hwblk);
60 }
61 }
62
63 dev_dbg(d, "__platform_pm_runtime_resume() [%d] - returns %d\n",
64 hwblk, ret);
65
66 return ret;
67}
68
69static int __platform_pm_runtime_suspend(struct platform_device *pdev)
70{
71 struct device *d = &pdev->dev;
72 struct pdev_archdata *ad = &pdev->archdata;
73 int hwblk = ad->hwblk_id;
74 int ret = -ENOSYS;
75
76 dev_dbg(d, "__platform_pm_runtime_suspend() [%d]\n", hwblk);
77
78 if (d->driver) {
79 BUG_ON(!test_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags));
80 ret = 0;
81
82 if (d->driver->pm && d->driver->pm->runtime_suspend) {
83 hwblk_enable(hwblk_info, hwblk);
84 ret = d->driver->pm->runtime_suspend(d);
85 hwblk_disable(hwblk_info, hwblk);
86 }
87
88 if (!ret) {
89 set_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
90 platform_pm_runtime_not_idle(pdev);
91 hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE);
92 }
93 }
94
95 dev_dbg(d, "__platform_pm_runtime_suspend() [%d] - returns %d\n",
96 hwblk, ret);
97
98 return ret;
99}
100
101static void platform_pm_runtime_work(struct work_struct *work)
102{
103 struct platform_device *pdev;
104 unsigned long flags;
105 int ret;
106
107 /* go through the idle list and suspend one device at a time */
108 do {
109 spin_lock_irqsave(&hwblk_lock, flags);
110 if (list_empty(&hwblk_idle_list))
111 pdev = NULL;
112 else
113 pdev = list_first_entry(&hwblk_idle_list,
114 struct platform_device,
115 archdata.entry);
116 spin_unlock_irqrestore(&hwblk_lock, flags);
117
118 if (pdev) {
119 mutex_lock(&pdev->archdata.mutex);
120 ret = __platform_pm_runtime_suspend(pdev);
121
122 /* at this point the platform device may be:
123 * suspended: ret = 0, FLAG_SUSP set, clock stopped
124 * failed: ret < 0, FLAG_IDLE set, clock stopped
125 */
126 mutex_unlock(&pdev->archdata.mutex);
127 } else {
128 ret = -ENODEV;
129 }
130 } while (!ret);
131}
132
133/* this function gets called from cpuidle context when all devices in the
134 * main power domain are unused but some are counted as idle, ie the hwblk
135 * counter values are (HWBLK_CNT_USAGE == 0) && (HWBLK_CNT_IDLE != 0)
136 */
137void platform_pm_runtime_suspend_idle(void)
138{
139 queue_work(pm_wq, &hwblk_work);
140}
141
142static int default_platform_runtime_suspend(struct device *dev)
143{
144 struct platform_device *pdev = to_platform_device(dev);
145 struct pdev_archdata *ad = &pdev->archdata;
146 unsigned long flags;
147 int hwblk = ad->hwblk_id;
148 int ret = 0;
149
150 dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
151
152 /* ignore off-chip platform devices */
153 if (!hwblk)
154 goto out;
155
156 /* interrupt context not allowed */
157 might_sleep();
158
159 /* catch misconfigured drivers not starting with resume */
160 if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &ad->flags)) {
161 ret = -EINVAL;
162 goto out;
163 }
164
165 /* serialize */
166 mutex_lock(&ad->mutex);
167
168 /* disable clock */
169 hwblk_disable(hwblk_info, hwblk);
170
171 /* put device on idle list */
172 spin_lock_irqsave(&hwblk_lock, flags);
173 list_add_tail(&ad->entry, &hwblk_idle_list);
174 __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags);
175 spin_unlock_irqrestore(&hwblk_lock, flags);
176
177 /* increase idle count */
178 hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_IDLE);
179
180 /* at this point the platform device is:
181 * idle: ret = 0, FLAG_IDLE set, clock stopped
182 */
183 mutex_unlock(&ad->mutex);
184
185out:
186 dev_dbg(dev, "%s() [%d] returns %d\n",
187 __func__, hwblk, ret);
188
189 return ret;
190}
191
192static int default_platform_runtime_resume(struct device *dev)
193{
194 struct platform_device *pdev = to_platform_device(dev);
195 struct pdev_archdata *ad = &pdev->archdata;
196 int hwblk = ad->hwblk_id;
197 int ret = 0;
198
199 dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
200
201 /* ignore off-chip platform devices */
202 if (!hwblk)
203 goto out;
204
205 /* interrupt context not allowed */
206 might_sleep();
207
208 /* serialize */
209 mutex_lock(&ad->mutex);
210
211 /* make sure device is removed from idle list */
212 platform_pm_runtime_not_idle(pdev);
213
214 /* decrease idle count */
215 if (!test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags) &&
216 !test_bit(PDEV_ARCHDATA_FLAG_SUSP, &pdev->archdata.flags))
217 hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE);
218
219 /* resume the device if needed */
220 ret = __platform_pm_runtime_resume(pdev);
221
222 /* the driver has been initialized now, so clear the init flag */
223 clear_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
224
225 /* at this point the platform device may be:
226 * resumed: ret = 0, flags = 0, clock started
227 * failed: ret < 0, FLAG_SUSP set, clock stopped
228 */
229 mutex_unlock(&ad->mutex);
230out:
231 dev_dbg(dev, "%s() [%d] returns %d\n",
232 __func__, hwblk, ret);
233
234 return ret;
235}
236
237static int default_platform_runtime_idle(struct device *dev)
238{
239 struct platform_device *pdev = to_platform_device(dev);
240 int hwblk = pdev->archdata.hwblk_id;
241 int ret = 0;
242
243 dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
244
245 /* ignore off-chip platform devices */
246 if (!hwblk)
247 goto out;
248
249 /* interrupt context not allowed, use pm_runtime_put()! */
250 might_sleep();
251
252 /* suspend synchronously to disable clocks immediately */
253 ret = pm_runtime_suspend(dev);
254out:
255 dev_dbg(dev, "%s() [%d] done!\n", __func__, hwblk);
256 return ret;
257}
258
259static struct dev_pm_domain default_pm_domain = {
260 .ops = {
261 .runtime_suspend = default_platform_runtime_suspend,
262 .runtime_resume = default_platform_runtime_resume,
263 .runtime_idle = default_platform_runtime_idle,
264 USE_PLATFORM_PM_SLEEP_OPS
265 },
266};
267
268static int platform_bus_notify(struct notifier_block *nb,
269 unsigned long action, void *data)
270{
271 struct device *dev = data;
272 struct platform_device *pdev = to_platform_device(dev);
273 int hwblk = pdev->archdata.hwblk_id;
274
275 /* ignore off-chip platform devices */
276 if (!hwblk)
277 return 0;
278
279 switch (action) {
280 case BUS_NOTIFY_ADD_DEVICE:
281 INIT_LIST_HEAD(&pdev->archdata.entry);
282 mutex_init(&pdev->archdata.mutex);
283 /* platform devices without drivers should be disabled */
284 hwblk_enable(hwblk_info, hwblk);
285 hwblk_disable(hwblk_info, hwblk);
286 /* make sure driver re-inits itself once */
287 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
288 dev->pm_domain = &default_pm_domain;
289 break;
290 /* TODO: add BUS_NOTIFY_BIND_DRIVER and increase idle count */
291 case BUS_NOTIFY_BOUND_DRIVER:
292 /* keep track of number of devices in use per hwblk */
293 hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_DEVICES);
294 break;
295 case BUS_NOTIFY_UNBOUND_DRIVER:
296 /* keep track of number of devices in use per hwblk */
297 hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_DEVICES);
298 /* make sure driver re-inits itself once */
299 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
300 break;
301 case BUS_NOTIFY_DEL_DEVICE:
302 dev->pm_domain = NULL;
303 break;
304 }
305 return 0;
306}
307
308static struct notifier_block platform_bus_notifier = {
309 .notifier_call = platform_bus_notify
310};
311
312static int __init sh_pm_runtime_init(void)
313{
314 INIT_WORK(&hwblk_work, platform_pm_runtime_work);
315
316 bus_register_notifier(&platform_bus_type, &platform_bus_notifier);
317 return 0;
318}
319core_initcall(sh_pm_runtime_init);
diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
index 2b15ae60c3a0..f67601cb3f1f 100644
--- a/arch/sh/kernel/entry-common.S
+++ b/arch/sh/kernel/entry-common.S
@@ -145,6 +145,7 @@ work_notifysig:
145 mov r15, r4 145 mov r15, r4
146 mov r12, r5 ! set arg1(save_r0) 146 mov r12, r5 ! set arg1(save_r0)
147 mov r0, r6 147 mov r0, r6
148 sti
148 mov.l 2f, r1 149 mov.l 2f, r1
149 mov.l 3f, r0 150 mov.l 3f, r0
150 jmp @r1 151 jmp @r1
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index 579cd2ca358d..a7a55ed43a59 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -588,9 +588,6 @@ static void do_signal(struct pt_regs *regs, unsigned int save_r0)
588 if (!user_mode(regs)) 588 if (!user_mode(regs))
589 return; 589 return;
590 590
591 if (try_to_freeze())
592 goto no_signal;
593
594 if (current_thread_info()->status & TS_RESTORE_SIGMASK) 591 if (current_thread_info()->status & TS_RESTORE_SIGMASK)
595 oldset = &current->saved_sigmask; 592 oldset = &current->saved_sigmask;
596 else 593 else
@@ -618,7 +615,6 @@ static void do_signal(struct pt_regs *regs, unsigned int save_r0)
618 return; 615 return;
619 } 616 }
620 617
621no_signal:
622 /* Did we come from a system call? */ 618 /* Did we come from a system call? */
623 if (regs->tra >= 0) { 619 if (regs->tra >= 0) {
624 /* Restart the system call - no handlers present */ 620 /* Restart the system call - no handlers present */
diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c
index 5a9f1f10ebf4..6b5603fe274b 100644
--- a/arch/sh/kernel/signal_64.c
+++ b/arch/sh/kernel/signal_64.c
@@ -98,9 +98,6 @@ static int do_signal(struct pt_regs *regs, sigset_t *oldset)
98 if (!user_mode(regs)) 98 if (!user_mode(regs))
99 return 1; 99 return 1;
100 100
101 if (try_to_freeze())
102 goto no_signal;
103
104 if (current_thread_info()->status & TS_RESTORE_SIGMASK) 101 if (current_thread_info()->status & TS_RESTORE_SIGMASK)
105 oldset = &current->saved_sigmask; 102 oldset = &current->saved_sigmask;
106 else if (!oldset) 103 else if (!oldset)
@@ -125,7 +122,6 @@ static int do_signal(struct pt_regs *regs, sigset_t *oldset)
125 } 122 }
126 } 123 }
127 124
128no_signal:
129 /* Did we come from a system call? */ 125 /* Did we come from a system call? */
130 if (regs->syscall_nr >= 0) { 126 if (regs->syscall_nr >= 0) {
131 /* Restart the system call - no handlers present */ 127 /* Restart the system call - no handlers present */
diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c
index 8a0072de2bcc..552c8fcf9416 100644
--- a/arch/sh/kernel/time.c
+++ b/arch/sh/kernel/time.c
@@ -21,7 +21,6 @@
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <linux/rtc.h> 22#include <linux/rtc.h>
23#include <asm/clock.h> 23#include <asm/clock.h>
24#include <asm/hwblk.h>
25#include <asm/rtc.h> 24#include <asm/rtc.h>
26 25
27/* Dummy RTC ops */ 26/* Dummy RTC ops */
@@ -110,7 +109,6 @@ void __init time_init(void)
110 if (board_time_init) 109 if (board_time_init)
111 board_time_init(); 110 board_time_init();
112 111
113 hwblk_init();
114 clk_init(); 112 clk_init();
115 113
116 late_time_init = sh_late_time_init; 114 late_time_init = sh_late_time_init;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 01:25:21 -0500