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-rw-r--r--arch/sh/kernel/cpu/irq/intc2.c25
-rw-r--r--arch/sh/kernel/cpu/irq/ipr.c6
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7780.c36
3 files changed, 36 insertions, 31 deletions
diff --git a/arch/sh/kernel/cpu/irq/intc2.c b/arch/sh/kernel/cpu/irq/intc2.c
index 74ca576a7ce5..74defe76a058 100644
--- a/arch/sh/kernel/cpu/irq/intc2.c
+++ b/arch/sh/kernel/cpu/irq/intc2.c
@@ -11,22 +11,29 @@
11 * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780. 11 * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
12 */ 12 */
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/irq.h> 14#include <linux/interrupt.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <asm/system.h> 16
17#if defined(CONFIG_CPU_SUBTYPE_SH7760)
18#define INTC2_BASE 0xfe080000
19#define INTC2_INTMSK (INTC2_BASE + 0x40)
20#define INTC2_INTMSKCLR (INTC2_BASE + 0x60)
21#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
22#define INTC2_BASE 0xffd40000
23#define INTC2_INTMSK (INTC2_BASE + 0x38)
24#define INTC2_INTMSKCLR (INTC2_BASE + 0x3c)
25#endif
17 26
18static void disable_intc2_irq(unsigned int irq) 27static void disable_intc2_irq(unsigned int irq)
19{ 28{
20 struct intc2_data *p = get_irq_chip_data(irq); 29 struct intc2_data *p = get_irq_chip_data(irq);
21 ctrl_outl(1 << p->msk_shift, 30 ctrl_outl(1 << p->msk_shift, INTC2_INTMSK + p->msk_offset);
22 INTC2_BASE + INTC2_INTMSK_OFFSET + p->msk_offset);
23} 31}
24 32
25static void enable_intc2_irq(unsigned int irq) 33static void enable_intc2_irq(unsigned int irq)
26{ 34{
27 struct intc2_data *p = get_irq_chip_data(irq); 35 struct intc2_data *p = get_irq_chip_data(irq);
28 ctrl_outl(1 << p->msk_shift, 36 ctrl_outl(1 << p->msk_shift, INTC2_INTMSKCLR + p->msk_offset);
29 INTC2_BASE + INTC2_INTMSKCLR_OFFSET + p->msk_offset);
30} 37}
31 38
32static struct irq_chip intc2_irq_chip = { 39static struct irq_chip intc2_irq_chip = {
@@ -61,12 +68,10 @@ void make_intc2_irq(struct intc2_data *table, unsigned int nr_irqs)
61 /* Set the priority level */ 68 /* Set the priority level */
62 local_irq_save(flags); 69 local_irq_save(flags);
63 70
64 ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + 71 ipr = ctrl_inl(INTC2_BASE + p->ipr_offset);
65 p->ipr_offset);
66 ipr &= ~(0xf << p->ipr_shift); 72 ipr &= ~(0xf << p->ipr_shift);
67 ipr |= p->priority << p->ipr_shift; 73 ipr |= p->priority << p->ipr_shift;
68 ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + 74 ctrl_outl(ipr, INTC2_BASE + p->ipr_offset);
69 p->ipr_offset);
70 75
71 local_irq_restore(flags); 76 local_irq_restore(flags);
72 77
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index f7a2bae1df94..a181ccdf2906 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -19,10 +19,8 @@
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/module.h> 21#include <linux/module.h>
22#include <asm/system.h> 22#include <linux/io.h>
23#include <asm/io.h> 23#include <linux/interrupt.h>
24#include <asm/machvec.h>
25
26 24
27static void disable_ipr_irq(unsigned int irq) 25static void disable_ipr_irq(unsigned int irq)
28{ 26{
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7780.c b/arch/sh/kernel/cpu/sh4/setup-sh7780.c
index 4a2b9e01b91f..9aeaa2ddaa28 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7780.c
@@ -79,25 +79,27 @@ static int __init sh7780_devices_setup(void)
79__initcall(sh7780_devices_setup); 79__initcall(sh7780_devices_setup);
80 80
81static struct intc2_data intc2_irq_table[] = { 81static struct intc2_data intc2_irq_table[] = {
82 { 28, 0, 24, 0, INTC_TMU0_MSK, 2 }, 82 { 28, 0, 24, 0, 0, 2 }, /* TMU0 */
83 { 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
84 { 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
85 { 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
86 { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
87 { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
88 { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
89 { SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
90 83
91 { SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, 84 { 21, 1, 0, 0, 2, 2 },
92 { SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, 85 { 22, 1, 1, 0, 2, 2 },
93 { SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, 86 { 23, 1, 2, 0, 2, 2 },
94 { SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
95 87
96 { PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY }, 88 { 40, 8, 24, 0, 3, 3 }, /* SCIF0 ERI */
97 { PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY }, 89 { 41, 8, 24, 0, 3, 3 }, /* SCIF0 RXI */
98 { PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY }, 90 { 42, 8, 24, 0, 3, 3 }, /* SCIF0 BRI */
99 { PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY }, 91 { 43, 8, 24, 0, 3, 3 }, /* SCIF0 TXI */
100 { PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY }, 92
93 { 76, 8, 16, 0, 4, 3 }, /* SCIF1 ERI */
94 { 77, 8, 16, 0, 4, 3 }, /* SCIF1 RXI */
95 { 78, 8, 16, 0, 4, 3 }, /* SCIF1 BRI */
96 { 79, 8, 16, 0, 4, 3 }, /* SCIF1 TXI */
97
98 { 64, 0x10, 8, 0, 14, 2 }, /* PCIC0 */
99 { 65, 0x10, 0, 0, 15, 2 }, /* PCIC1 */
100 { 66, 0x14, 24, 0, 16, 2 }, /* PCIC2 */
101 { 67, 0x14, 16, 0, 17, 2 }, /* PCIC3 */
102 { 68, 0x14, 8, 0, 18, 2 }, /* PCIC4 */
101}; 103};
102 104
103void __init init_IRQ_intc2(void) 105void __init init_IRQ_intc2(void)