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-rw-r--r--arch/sh/kernel/cpu/init.c30
-rw-r--r--arch/sh/kernel/cpu/sh2/probe.c32
-rw-r--r--arch/sh/kernel/cpu/sh2a/probe.c16
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c42
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c185
-rw-r--r--arch/sh/kernel/process.c5
-rw-r--r--arch/sh/kernel/setup.c49
-rw-r--r--arch/sh/kernel/signal.c6
-rw-r--r--arch/sh/kernel/traps.c2
9 files changed, 189 insertions, 178 deletions
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 6c3c7687e81f..4b339a640b13 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -48,7 +48,7 @@ static void __init cache_init(void)
48{ 48{
49 unsigned long ccr, flags; 49 unsigned long ccr, flags;
50 50
51 if (cpu_data->type == CPU_SH_NONE) 51 if (current_cpu_data.type == CPU_SH_NONE)
52 panic("Unknown CPU"); 52 panic("Unknown CPU");
53 53
54 jump_to_P2(); 54 jump_to_P2();
@@ -68,7 +68,7 @@ static void __init cache_init(void)
68 if (ccr & CCR_CACHE_ENABLE) { 68 if (ccr & CCR_CACHE_ENABLE) {
69 unsigned long ways, waysize, addrstart; 69 unsigned long ways, waysize, addrstart;
70 70
71 waysize = cpu_data->dcache.sets; 71 waysize = current_cpu_data.dcache.sets;
72 72
73#ifdef CCR_CACHE_ORA 73#ifdef CCR_CACHE_ORA
74 /* 74 /*
@@ -79,7 +79,7 @@ static void __init cache_init(void)
79 waysize >>= 1; 79 waysize >>= 1;
80#endif 80#endif
81 81
82 waysize <<= cpu_data->dcache.entry_shift; 82 waysize <<= current_cpu_data.dcache.entry_shift;
83 83
84#ifdef CCR_CACHE_EMODE 84#ifdef CCR_CACHE_EMODE
85 /* If EMODE is not set, we only have 1 way to flush. */ 85 /* If EMODE is not set, we only have 1 way to flush. */
@@ -87,7 +87,7 @@ static void __init cache_init(void)
87 ways = 1; 87 ways = 1;
88 else 88 else
89#endif 89#endif
90 ways = cpu_data->dcache.ways; 90 ways = current_cpu_data.dcache.ways;
91 91
92 addrstart = CACHE_OC_ADDRESS_ARRAY; 92 addrstart = CACHE_OC_ADDRESS_ARRAY;
93 do { 93 do {
@@ -95,10 +95,10 @@ static void __init cache_init(void)
95 95
96 for (addr = addrstart; 96 for (addr = addrstart;
97 addr < addrstart + waysize; 97 addr < addrstart + waysize;
98 addr += cpu_data->dcache.linesz) 98 addr += current_cpu_data.dcache.linesz)
99 ctrl_outl(0, addr); 99 ctrl_outl(0, addr);
100 100
101 addrstart += cpu_data->dcache.way_incr; 101 addrstart += current_cpu_data.dcache.way_incr;
102 } while (--ways); 102 } while (--ways);
103 } 103 }
104 104
@@ -110,7 +110,7 @@ static void __init cache_init(void)
110 110
111#ifdef CCR_CACHE_EMODE 111#ifdef CCR_CACHE_EMODE
112 /* Force EMODE if possible */ 112 /* Force EMODE if possible */
113 if (cpu_data->dcache.ways > 1) 113 if (current_cpu_data.dcache.ways > 1)
114 flags |= CCR_CACHE_EMODE; 114 flags |= CCR_CACHE_EMODE;
115 else 115 else
116 flags &= ~CCR_CACHE_EMODE; 116 flags &= ~CCR_CACHE_EMODE;
@@ -127,10 +127,10 @@ static void __init cache_init(void)
127#ifdef CONFIG_SH_OCRAM 127#ifdef CONFIG_SH_OCRAM
128 /* Turn on OCRAM -- halve the OC */ 128 /* Turn on OCRAM -- halve the OC */
129 flags |= CCR_CACHE_ORA; 129 flags |= CCR_CACHE_ORA;
130 cpu_data->dcache.sets >>= 1; 130 current_cpu_data.dcache.sets >>= 1;
131 131
132 cpu_data->dcache.way_size = cpu_data->dcache.sets * 132 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
133 cpu_data->dcache.linesz; 133 current_cpu_data.dcache.linesz;
134#endif 134#endif
135 135
136 ctrl_outl(flags, CCR); 136 ctrl_outl(flags, CCR);
@@ -172,7 +172,7 @@ static void __init dsp_init(void)
172 172
173 /* If the DSP bit is still set, this CPU has a DSP */ 173 /* If the DSP bit is still set, this CPU has a DSP */
174 if (sr & SR_DSP) 174 if (sr & SR_DSP)
175 cpu_data->flags |= CPU_HAS_DSP; 175 current_cpu_data.flags |= CPU_HAS_DSP;
176 176
177 /* Now that we've determined the DSP status, clear the DSP bit. */ 177 /* Now that we've determined the DSP status, clear the DSP bit. */
178 release_dsp(); 178 release_dsp();
@@ -204,18 +204,18 @@ asmlinkage void __init sh_cpu_init(void)
204 cache_init(); 204 cache_init();
205 205
206 shm_align_mask = max_t(unsigned long, 206 shm_align_mask = max_t(unsigned long,
207 cpu_data->dcache.way_size - 1, 207 current_cpu_data.dcache.way_size - 1,
208 PAGE_SIZE - 1); 208 PAGE_SIZE - 1);
209 209
210 /* Disable the FPU */ 210 /* Disable the FPU */
211 if (fpu_disabled) { 211 if (fpu_disabled) {
212 printk("FPU Disabled\n"); 212 printk("FPU Disabled\n");
213 cpu_data->flags &= ~CPU_HAS_FPU; 213 current_cpu_data.flags &= ~CPU_HAS_FPU;
214 disable_fpu(); 214 disable_fpu();
215 } 215 }
216 216
217 /* FPU initialization */ 217 /* FPU initialization */
218 if ((cpu_data->flags & CPU_HAS_FPU)) { 218 if ((current_cpu_data.flags & CPU_HAS_FPU)) {
219 clear_thread_flag(TIF_USEDFPU); 219 clear_thread_flag(TIF_USEDFPU);
220 clear_used_math(); 220 clear_used_math();
221 } 221 }
@@ -233,7 +233,7 @@ asmlinkage void __init sh_cpu_init(void)
233 /* Disable the DSP */ 233 /* Disable the DSP */
234 if (dsp_disabled) { 234 if (dsp_disabled) {
235 printk("DSP Disabled\n"); 235 printk("DSP Disabled\n");
236 cpu_data->flags &= ~CPU_HAS_DSP; 236 current_cpu_data.flags &= ~CPU_HAS_DSP;
237 release_dsp(); 237 release_dsp();
238 } 238 }
239#endif 239#endif
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index ba527d9b5024..108e81b682ed 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -18,27 +18,27 @@
18int __init detect_cpu_and_cache_system(void) 18int __init detect_cpu_and_cache_system(void)
19{ 19{
20#if defined(CONFIG_CPU_SUBTYPE_SH7604) 20#if defined(CONFIG_CPU_SUBTYPE_SH7604)
21 cpu_data->type = CPU_SH7604; 21 current_cpu_data.type = CPU_SH7604;
22 cpu_data->dcache.ways = 4; 22 current_cpu_data.dcache.ways = 4;
23 cpu_data->dcache.way_incr = (1<<10); 23 current_cpu_data.dcache.way_incr = (1<<10);
24 cpu_data->dcache.sets = 64; 24 current_cpu_data.dcache.sets = 64;
25 cpu_data->dcache.entry_shift = 4; 25 current_cpu_data.dcache.entry_shift = 4;
26 cpu_data->dcache.linesz = L1_CACHE_BYTES; 26 current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
27 cpu_data->dcache.flags = 0; 27 current_cpu_data.dcache.flags = 0;
28#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 28#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
29 cpu_data->type = CPU_SH7619; 29 current_cpu_data.type = CPU_SH7619;
30 cpu_data->dcache.ways = 4; 30 current_cpu_data.dcache.ways = 4;
31 cpu_data->dcache.way_incr = (1<<12); 31 current_cpu_data.dcache.way_incr = (1<<12);
32 cpu_data->dcache.sets = 256; 32 current_cpu_data.dcache.sets = 256;
33 cpu_data->dcache.entry_shift = 4; 33 current_cpu_data.dcache.entry_shift = 4;
34 cpu_data->dcache.linesz = L1_CACHE_BYTES; 34 current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
35 cpu_data->dcache.flags = 0; 35 current_cpu_data.dcache.flags = 0;
36#endif 36#endif
37 /* 37 /*
38 * SH-2 doesn't have separate caches 38 * SH-2 doesn't have separate caches
39 */ 39 */
40 cpu_data->dcache.flags |= SH_CACHE_COMBINED; 40 current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
41 cpu_data->icache = cpu_data->dcache; 41 current_cpu_data.icache = current_cpu_data.dcache;
42 42
43 return 0; 43 return 0;
44} 44}
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index 87c6c0542089..426f6db01fc6 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -17,14 +17,14 @@
17int __init detect_cpu_and_cache_system(void) 17int __init detect_cpu_and_cache_system(void)
18{ 18{
19 /* Just SH7206 for now .. */ 19 /* Just SH7206 for now .. */
20 cpu_data->type = CPU_SH7206; 20 current_cpu_data.type = CPU_SH7206;
21 21
22 cpu_data->dcache.ways = 4; 22 current_cpu_data.dcache.ways = 4;
23 cpu_data->dcache.way_incr = (1 << 11); 23 current_cpu_data.dcache.way_incr = (1 << 11);
24 cpu_data->dcache.sets = 128; 24 current_cpu_data.dcache.sets = 128;
25 cpu_data->dcache.entry_shift = 4; 25 current_cpu_data.dcache.entry_shift = 4;
26 cpu_data->dcache.linesz = L1_CACHE_BYTES; 26 current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
27 cpu_data->dcache.flags = 0; 27 current_cpu_data.dcache.flags = 0;
28 28
29 /* 29 /*
30 * The icache is the same as the dcache as far as this setup is 30 * The icache is the same as the dcache as far as this setup is
@@ -32,7 +32,7 @@ int __init detect_cpu_and_cache_system(void)
32 * lacks the U bit that the dcache has, none of this has any bearing 32 * lacks the U bit that the dcache has, none of this has any bearing
33 * on the cache info. 33 * on the cache info.
34 */ 34 */
35 cpu_data->icache = cpu_data->dcache; 35 current_cpu_data.icache = current_cpu_data.dcache;
36 36
37 return 0; 37 return 0;
38} 38}
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index e67098836290..821b0ab7b528 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -50,41 +50,41 @@ int __init detect_cpu_and_cache_system(void)
50 50
51 back_to_P1(); 51 back_to_P1();
52 52
53 cpu_data->dcache.ways = 4; 53 current_cpu_data.dcache.ways = 4;
54 cpu_data->dcache.entry_shift = 4; 54 current_cpu_data.dcache.entry_shift = 4;
55 cpu_data->dcache.linesz = L1_CACHE_BYTES; 55 current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
56 cpu_data->dcache.flags = 0; 56 current_cpu_data.dcache.flags = 0;
57 57
58 /* 58 /*
59 * 7709A/7729 has 16K cache (256-entry), while 7702 has only 59 * 7709A/7729 has 16K cache (256-entry), while 7702 has only
60 * 2K(direct) 7702 is not supported (yet) 60 * 2K(direct) 7702 is not supported (yet)
61 */ 61 */
62 if (data0 == data1 && data2 == data3) { /* Shadow */ 62 if (data0 == data1 && data2 == data3) { /* Shadow */
63 cpu_data->dcache.way_incr = (1 << 11); 63 current_cpu_data.dcache.way_incr = (1 << 11);
64 cpu_data->dcache.entry_mask = 0x7f0; 64 current_cpu_data.dcache.entry_mask = 0x7f0;
65 cpu_data->dcache.sets = 128; 65 current_cpu_data.dcache.sets = 128;
66 cpu_data->type = CPU_SH7708; 66 current_cpu_data.type = CPU_SH7708;
67 67
68 cpu_data->flags |= CPU_HAS_MMU_PAGE_ASSOC; 68 current_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
69 } else { /* 7709A or 7729 */ 69 } else { /* 7709A or 7729 */
70 cpu_data->dcache.way_incr = (1 << 12); 70 current_cpu_data.dcache.way_incr = (1 << 12);
71 cpu_data->dcache.entry_mask = 0xff0; 71 current_cpu_data.dcache.entry_mask = 0xff0;
72 cpu_data->dcache.sets = 256; 72 current_cpu_data.dcache.sets = 256;
73 cpu_data->type = CPU_SH7729; 73 current_cpu_data.type = CPU_SH7729;
74 74
75#if defined(CONFIG_CPU_SUBTYPE_SH7706) 75#if defined(CONFIG_CPU_SUBTYPE_SH7706)
76 cpu_data->type = CPU_SH7706; 76 current_cpu_data.type = CPU_SH7706;
77#endif 77#endif
78#if defined(CONFIG_CPU_SUBTYPE_SH7710) 78#if defined(CONFIG_CPU_SUBTYPE_SH7710)
79 cpu_data->type = CPU_SH7710; 79 current_cpu_data.type = CPU_SH7710;
80#endif 80#endif
81#if defined(CONFIG_CPU_SUBTYPE_SH7705) 81#if defined(CONFIG_CPU_SUBTYPE_SH7705)
82 cpu_data->type = CPU_SH7705; 82 current_cpu_data.type = CPU_SH7705;
83 83
84#if defined(CONFIG_SH7705_CACHE_32KB) 84#if defined(CONFIG_SH7705_CACHE_32KB)
85 cpu_data->dcache.way_incr = (1 << 13); 85 current_cpu_data.dcache.way_incr = (1 << 13);
86 cpu_data->dcache.entry_mask = 0x1ff0; 86 current_cpu_data.dcache.entry_mask = 0x1ff0;
87 cpu_data->dcache.sets = 512; 87 current_cpu_data.dcache.sets = 512;
88 ctrl_outl(CCR_CACHE_32KB, CCR3); 88 ctrl_outl(CCR_CACHE_32KB, CCR3);
89#else 89#else
90 ctrl_outl(CCR_CACHE_16KB, CCR3); 90 ctrl_outl(CCR_CACHE_16KB, CCR3);
@@ -95,8 +95,8 @@ int __init detect_cpu_and_cache_system(void)
95 /* 95 /*
96 * SH-3 doesn't have separate caches 96 * SH-3 doesn't have separate caches
97 */ 97 */
98 cpu_data->dcache.flags |= SH_CACHE_COMBINED; 98 current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
99 cpu_data->icache = cpu_data->dcache; 99 current_cpu_data.icache = current_cpu_data.dcache;
100 100
101 return 0; 101 return 0;
102} 102}
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index b26e2bc5894d..9d28c88d2f9d 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -10,11 +10,10 @@
10 * License. See the file "COPYING" in the main directory of this archive 10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details. 11 * for more details.
12 */ 12 */
13
14#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/io.h>
15#include <asm/processor.h> 15#include <asm/processor.h>
16#include <asm/cache.h> 16#include <asm/cache.h>
17#include <asm/io.h>
18 17
19int __init detect_cpu_and_cache_system(void) 18int __init detect_cpu_and_cache_system(void)
20{ 19{
@@ -36,20 +35,20 @@ int __init detect_cpu_and_cache_system(void)
36 /* 35 /*
37 * Setup some sane SH-4 defaults for the icache 36 * Setup some sane SH-4 defaults for the icache
38 */ 37 */
39 cpu_data->icache.way_incr = (1 << 13); 38 current_cpu_data.icache.way_incr = (1 << 13);
40 cpu_data->icache.entry_shift = 5; 39 current_cpu_data.icache.entry_shift = 5;
41 cpu_data->icache.sets = 256; 40 current_cpu_data.icache.sets = 256;
42 cpu_data->icache.ways = 1; 41 current_cpu_data.icache.ways = 1;
43 cpu_data->icache.linesz = L1_CACHE_BYTES; 42 current_cpu_data.icache.linesz = L1_CACHE_BYTES;
44 43
45 /* 44 /*
46 * And again for the dcache .. 45 * And again for the dcache ..
47 */ 46 */
48 cpu_data->dcache.way_incr = (1 << 14); 47 current_cpu_data.dcache.way_incr = (1 << 14);
49 cpu_data->dcache.entry_shift = 5; 48 current_cpu_data.dcache.entry_shift = 5;
50 cpu_data->dcache.sets = 512; 49 current_cpu_data.dcache.sets = 512;
51 cpu_data->dcache.ways = 1; 50 current_cpu_data.dcache.ways = 1;
52 cpu_data->dcache.linesz = L1_CACHE_BYTES; 51 current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
53 52
54 /* 53 /*
55 * Setup some generic flags we can probe 54 * Setup some generic flags we can probe
@@ -57,16 +56,16 @@ int __init detect_cpu_and_cache_system(void)
57 */ 56 */
58 if (((pvr >> 16) & 0xff) == 0x10) { 57 if (((pvr >> 16) & 0xff) == 0x10) {
59 if ((cvr & 0x02000000) == 0) 58 if ((cvr & 0x02000000) == 0)
60 cpu_data->flags |= CPU_HAS_L2_CACHE; 59 current_cpu_data.flags |= CPU_HAS_L2_CACHE;
61 if ((cvr & 0x10000000) == 0) 60 if ((cvr & 0x10000000) == 0)
62 cpu_data->flags |= CPU_HAS_DSP; 61 current_cpu_data.flags |= CPU_HAS_DSP;
63 62
64 cpu_data->flags |= CPU_HAS_LLSC; 63 current_cpu_data.flags |= CPU_HAS_LLSC;
65 } 64 }
66 65
67 /* FPU detection works for everyone */ 66 /* FPU detection works for everyone */
68 if ((cvr & 0x20000000) == 1) 67 if ((cvr & 0x20000000) == 1)
69 cpu_data->flags |= CPU_HAS_FPU; 68 current_cpu_data.flags |= CPU_HAS_FPU;
70 69
71 /* Mask off the upper chip ID */ 70 /* Mask off the upper chip ID */
72 pvr &= 0xffff; 71 pvr &= 0xffff;
@@ -77,147 +76,151 @@ int __init detect_cpu_and_cache_system(void)
77 */ 76 */
78 switch (pvr) { 77 switch (pvr) {
79 case 0x205: 78 case 0x205:
80 cpu_data->type = CPU_SH7750; 79 current_cpu_data.type = CPU_SH7750;
81 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | 80 current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
82 CPU_HAS_PERF_COUNTER; 81 CPU_HAS_PERF_COUNTER;
83 break; 82 break;
84 case 0x206: 83 case 0x206:
85 cpu_data->type = CPU_SH7750S; 84 current_cpu_data.type = CPU_SH7750S;
86 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | 85 current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
87 CPU_HAS_PERF_COUNTER; 86 CPU_HAS_PERF_COUNTER;
88 break; 87 break;
89 case 0x1100: 88 case 0x1100:
90 cpu_data->type = CPU_SH7751; 89 current_cpu_data.type = CPU_SH7751;
91 cpu_data->flags |= CPU_HAS_FPU; 90 current_cpu_data.flags |= CPU_HAS_FPU;
92 break; 91 break;
93 case 0x2000: 92 case 0x2000:
94 cpu_data->type = CPU_SH73180; 93 current_cpu_data.type = CPU_SH73180;
95 cpu_data->icache.ways = 4; 94 current_cpu_data.icache.ways = 4;
96 cpu_data->dcache.ways = 4; 95 current_cpu_data.dcache.ways = 4;
97 cpu_data->flags |= CPU_HAS_LLSC; 96 current_cpu_data.flags |= CPU_HAS_LLSC;
98 break; 97 break;
99 case 0x2001: 98 case 0x2001:
100 case 0x2004: 99 case 0x2004:
101 cpu_data->type = CPU_SH7770; 100 current_cpu_data.type = CPU_SH7770;
102 cpu_data->icache.ways = 4; 101 current_cpu_data.icache.ways = 4;
103 cpu_data->dcache.ways = 4; 102 current_cpu_data.dcache.ways = 4;
104 103
105 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_LLSC; 104 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
106 break; 105 break;
107 case 0x2006: 106 case 0x2006:
108 case 0x200A: 107 case 0x200A:
109 if (prr == 0x61) 108 if (prr == 0x61)
110 cpu_data->type = CPU_SH7781; 109 current_cpu_data.type = CPU_SH7781;
111 else 110 else
112 cpu_data->type = CPU_SH7780; 111 current_cpu_data.type = CPU_SH7780;
113 112
114 cpu_data->icache.ways = 4; 113 current_cpu_data.icache.ways = 4;
115 cpu_data->dcache.ways = 4; 114 current_cpu_data.dcache.ways = 4;
116 115
117 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 116 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
118 CPU_HAS_LLSC; 117 CPU_HAS_LLSC;
119 break; 118 break;
120 case 0x3000: 119 case 0x3000:
121 case 0x3003: 120 case 0x3003:
122 case 0x3009: 121 case 0x3009:
123 cpu_data->type = CPU_SH7343; 122 current_cpu_data.type = CPU_SH7343;
124 cpu_data->icache.ways = 4; 123 current_cpu_data.icache.ways = 4;
125 cpu_data->dcache.ways = 4; 124 current_cpu_data.dcache.ways = 4;
126 cpu_data->flags |= CPU_HAS_LLSC; 125 current_cpu_data.flags |= CPU_HAS_LLSC;
127 break; 126 break;
128 case 0x3008: 127 case 0x3008:
129 if (prr == 0xa0) { 128 if (prr == 0xa0) {
130 cpu_data->type = CPU_SH7722; 129 current_cpu_data.type = CPU_SH7722;
131 cpu_data->icache.ways = 4; 130 current_cpu_data.icache.ways = 4;
132 cpu_data->dcache.ways = 4; 131 current_cpu_data.dcache.ways = 4;
133 cpu_data->flags |= CPU_HAS_LLSC; 132 current_cpu_data.flags |= CPU_HAS_LLSC;
134 } 133 }
135 break; 134 break;
136 case 0x8000: 135 case 0x8000:
137 cpu_data->type = CPU_ST40RA; 136 current_cpu_data.type = CPU_ST40RA;
138 cpu_data->flags |= CPU_HAS_FPU; 137 current_cpu_data.flags |= CPU_HAS_FPU;
139 break; 138 break;
140 case 0x8100: 139 case 0x8100:
141 cpu_data->type = CPU_ST40GX1; 140 current_cpu_data.type = CPU_ST40GX1;
142 cpu_data->flags |= CPU_HAS_FPU; 141 current_cpu_data.flags |= CPU_HAS_FPU;
143 break; 142 break;
144 case 0x700: 143 case 0x700:
145 cpu_data->type = CPU_SH4_501; 144 current_cpu_data.type = CPU_SH4_501;
146 cpu_data->icache.ways = 2; 145 current_cpu_data.icache.ways = 2;
147 cpu_data->dcache.ways = 2; 146 current_cpu_data.dcache.ways = 2;
148 break; 147 break;
149 case 0x600: 148 case 0x600:
150 cpu_data->type = CPU_SH4_202; 149 current_cpu_data.type = CPU_SH4_202;
151 cpu_data->icache.ways = 2; 150 current_cpu_data.icache.ways = 2;
152 cpu_data->dcache.ways = 2; 151 current_cpu_data.dcache.ways = 2;
153 cpu_data->flags |= CPU_HAS_FPU; 152 current_cpu_data.flags |= CPU_HAS_FPU;
154 break; 153 break;
155 case 0x500 ... 0x501: 154 case 0x500 ... 0x501:
156 switch (prr) { 155 switch (prr) {
157 case 0x10: 156 case 0x10:
158 cpu_data->type = CPU_SH7750R; 157 current_cpu_data.type = CPU_SH7750R;
159 break; 158 break;
160 case 0x11: 159 case 0x11:
161 cpu_data->type = CPU_SH7751R; 160 current_cpu_data.type = CPU_SH7751R;
162 break; 161 break;
163 case 0x50 ... 0x5f: 162 case 0x50 ... 0x5f:
164 cpu_data->type = CPU_SH7760; 163 current_cpu_data.type = CPU_SH7760;
165 break; 164 break;
166 } 165 }
167 166
168 cpu_data->icache.ways = 2; 167 current_cpu_data.icache.ways = 2;
169 cpu_data->dcache.ways = 2; 168 current_cpu_data.dcache.ways = 2;
170 169
171 cpu_data->flags |= CPU_HAS_FPU; 170 current_cpu_data.flags |= CPU_HAS_FPU;
172 171
173 break; 172 break;
174 default: 173 default:
175 cpu_data->type = CPU_SH_NONE; 174 current_cpu_data.type = CPU_SH_NONE;
176 break; 175 break;
177 } 176 }
178 177
179#ifdef CONFIG_SH_DIRECT_MAPPED 178#ifdef CONFIG_SH_DIRECT_MAPPED
180 cpu_data->icache.ways = 1; 179 current_cpu_data.icache.ways = 1;
181 cpu_data->dcache.ways = 1; 180 current_cpu_data.dcache.ways = 1;
181#endif
182
183#ifdef CONFIG_CPU_HAS_PTEA
184 current_cpu_data.flags |= CPU_HAS_PTEA;
182#endif 185#endif
183 186
184 /* 187 /*
185 * On anything that's not a direct-mapped cache, look to the CVR 188 * On anything that's not a direct-mapped cache, look to the CVR
186 * for I/D-cache specifics. 189 * for I/D-cache specifics.
187 */ 190 */
188 if (cpu_data->icache.ways > 1) { 191 if (current_cpu_data.icache.ways > 1) {
189 size = sizes[(cvr >> 20) & 0xf]; 192 size = sizes[(cvr >> 20) & 0xf];
190 cpu_data->icache.way_incr = (size >> 1); 193 current_cpu_data.icache.way_incr = (size >> 1);
191 cpu_data->icache.sets = (size >> 6); 194 current_cpu_data.icache.sets = (size >> 6);
192 195
193 } 196 }
194 197
195 /* Setup the rest of the I-cache info */ 198 /* Setup the rest of the I-cache info */
196 cpu_data->icache.entry_mask = cpu_data->icache.way_incr - 199 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
197 cpu_data->icache.linesz; 200 current_cpu_data.icache.linesz;
198 201
199 cpu_data->icache.way_size = cpu_data->icache.sets * 202 current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
200 cpu_data->icache.linesz; 203 current_cpu_data.icache.linesz;
201 204
202 /* And the rest of the D-cache */ 205 /* And the rest of the D-cache */
203 if (cpu_data->dcache.ways > 1) { 206 if (current_cpu_data.dcache.ways > 1) {
204 size = sizes[(cvr >> 16) & 0xf]; 207 size = sizes[(cvr >> 16) & 0xf];
205 cpu_data->dcache.way_incr = (size >> 1); 208 current_cpu_data.dcache.way_incr = (size >> 1);
206 cpu_data->dcache.sets = (size >> 6); 209 current_cpu_data.dcache.sets = (size >> 6);
207 } 210 }
208 211
209 cpu_data->dcache.entry_mask = cpu_data->dcache.way_incr - 212 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
210 cpu_data->dcache.linesz; 213 current_cpu_data.dcache.linesz;
211 214
212 cpu_data->dcache.way_size = cpu_data->dcache.sets * 215 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
213 cpu_data->dcache.linesz; 216 current_cpu_data.dcache.linesz;
214 217
215 /* 218 /*
216 * Setup the L2 cache desc 219 * Setup the L2 cache desc
217 * 220 *
218 * SH-4A's have an optional PIPT L2. 221 * SH-4A's have an optional PIPT L2.
219 */ 222 */
220 if (cpu_data->flags & CPU_HAS_L2_CACHE) { 223 if (current_cpu_data.flags & CPU_HAS_L2_CACHE) {
221 /* 224 /*
222 * Size calculation is much more sensible 225 * Size calculation is much more sensible
223 * than it is for the L1. 226 * than it is for the L1.
@@ -228,16 +231,22 @@ int __init detect_cpu_and_cache_system(void)
228 231
229 BUG_ON(!size); 232 BUG_ON(!size);
230 233
231 cpu_data->scache.way_incr = (1 << 16); 234 current_cpu_data.scache.way_incr = (1 << 16);
232 cpu_data->scache.entry_shift = 5; 235 current_cpu_data.scache.entry_shift = 5;
233 cpu_data->scache.ways = 4; 236 current_cpu_data.scache.ways = 4;
234 cpu_data->scache.linesz = L1_CACHE_BYTES; 237 current_cpu_data.scache.linesz = L1_CACHE_BYTES;
235 cpu_data->scache.entry_mask = 238
236 (cpu_data->scache.way_incr - cpu_data->scache.linesz); 239 current_cpu_data.scache.entry_mask =
237 cpu_data->scache.sets = size / 240 (current_cpu_data.scache.way_incr -
238 (cpu_data->scache.linesz * cpu_data->scache.ways); 241 current_cpu_data.scache.linesz);
239 cpu_data->scache.way_size = 242
240 (cpu_data->scache.sets * cpu_data->scache.linesz); 243 current_cpu_data.scache.sets = size /
244 (current_cpu_data.scache.linesz *
245 current_cpu_data.scache.ways);
246
247 current_cpu_data.scache.way_size =
248 (current_cpu_data.scache.sets *
249 current_cpu_data.scache.linesz);
241 } 250 }
242 251
243 return 0; 252 return 0;
diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c
index 0298f0faa6e6..9d6a438b3eaf 100644
--- a/arch/sh/kernel/process.c
+++ b/arch/sh/kernel/process.c
@@ -293,13 +293,14 @@ static void ubc_set_tracing(int asid, unsigned long pc)
293 293
294#ifdef CONFIG_MMU 294#ifdef CONFIG_MMU
295 /* We don't have any ASID settings for the SH-2! */ 295 /* We don't have any ASID settings for the SH-2! */
296 if (cpu_data->type != CPU_SH7604) 296 if (current_cpu_data.type != CPU_SH7604)
297 ctrl_outb(asid, UBC_BASRA); 297 ctrl_outb(asid, UBC_BASRA);
298#endif 298#endif
299 299
300 ctrl_outl(0, UBC_BAMRA); 300 ctrl_outl(0, UBC_BAMRA);
301 301
302 if (cpu_data->type == CPU_SH7729 || cpu_data->type == CPU_SH7710) { 302 if (current_cpu_data.type == CPU_SH7729 ||
303 current_cpu_data.type == CPU_SH7710) {
303 ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA); 304 ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA);
304 ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR); 305 ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR);
305 } else { 306 } else {
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index d6b817aa568f..98802ab28211 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -1,14 +1,11 @@
1/* 1/*
2 * linux/arch/sh/kernel/setup.c 2 * arch/sh/kernel/setup.c
3 * 3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2002, 2003 Paul Mundt
6 */
7
8/*
9 * This file handles the architecture-dependent parts of initialization 4 * This file handles the architecture-dependent parts of initialization
5 *
6 * Copyright (C) 1999 Niibe Yutaka
7 * Copyright (C) 2002 - 2006 Paul Mundt
10 */ 8 */
11
12#include <linux/screen_info.h> 9#include <linux/screen_info.h>
13#include <linux/ioport.h> 10#include <linux/ioport.h>
14#include <linux/init.h> 11#include <linux/init.h>
@@ -395,9 +392,9 @@ static const char *cpu_name[] = {
395 [CPU_SH_NONE] = "Unknown" 392 [CPU_SH_NONE] = "Unknown"
396}; 393};
397 394
398const char *get_cpu_subtype(void) 395const char *get_cpu_subtype(struct sh_cpuinfo *c)
399{ 396{
400 return cpu_name[boot_cpu_data.type]; 397 return cpu_name[c->type];
401} 398}
402 399
403#ifdef CONFIG_PROC_FS 400#ifdef CONFIG_PROC_FS
@@ -407,19 +404,19 @@ static const char *cpu_flags[] = {
407 "ptea", "llsc", "l2", NULL 404 "ptea", "llsc", "l2", NULL
408}; 405};
409 406
410static void show_cpuflags(struct seq_file *m) 407static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
411{ 408{
412 unsigned long i; 409 unsigned long i;
413 410
414 seq_printf(m, "cpu flags\t:"); 411 seq_printf(m, "cpu flags\t:");
415 412
416 if (!cpu_data->flags) { 413 if (!c->flags) {
417 seq_printf(m, " %s\n", cpu_flags[0]); 414 seq_printf(m, " %s\n", cpu_flags[0]);
418 return; 415 return;
419 } 416 }
420 417
421 for (i = 0; cpu_flags[i]; i++) 418 for (i = 0; cpu_flags[i]; i++)
422 if ((cpu_data->flags & (1 << i))) 419 if ((c->flags & (1 << i)))
423 seq_printf(m, " %s", cpu_flags[i+1]); 420 seq_printf(m, " %s", cpu_flags[i+1]);
424 421
425 seq_printf(m, "\n"); 422 seq_printf(m, "\n");
@@ -441,16 +438,20 @@ static void show_cacheinfo(struct seq_file *m, const char *type,
441 */ 438 */
442static int show_cpuinfo(struct seq_file *m, void *v) 439static int show_cpuinfo(struct seq_file *m, void *v)
443{ 440{
444 unsigned int cpu = smp_processor_id(); 441 struct sh_cpuinfo *c = v;
442 unsigned int cpu = c - cpu_data;
443
444 if (!cpu_online(cpu))
445 return 0;
445 446
446 if (!cpu && cpu_online(cpu)) 447 if (cpu == 0)
447 seq_printf(m, "machine\t\t: %s\n", get_system_type()); 448 seq_printf(m, "machine\t\t: %s\n", get_system_type());
448 449
449 seq_printf(m, "processor\t: %d\n", cpu); 450 seq_printf(m, "processor\t: %d\n", cpu);
450 seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine); 451 seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
451 seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype()); 452 seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
452 453
453 show_cpuflags(m); 454 show_cpuflags(m, c);
454 455
455 seq_printf(m, "cache type\t: "); 456 seq_printf(m, "cache type\t: ");
456 457
@@ -459,22 +460,22 @@ static int show_cpuinfo(struct seq_file *m, void *v)
459 * unified cache on the SH-2 and SH-3, as well as the harvard 460 * unified cache on the SH-2 and SH-3, as well as the harvard
460 * style cache on the SH-4. 461 * style cache on the SH-4.
461 */ 462 */
462 if (boot_cpu_data.icache.flags & SH_CACHE_COMBINED) { 463 if (c->icache.flags & SH_CACHE_COMBINED) {
463 seq_printf(m, "unified\n"); 464 seq_printf(m, "unified\n");
464 show_cacheinfo(m, "cache", boot_cpu_data.icache); 465 show_cacheinfo(m, "cache", c->icache);
465 } else { 466 } else {
466 seq_printf(m, "split (harvard)\n"); 467 seq_printf(m, "split (harvard)\n");
467 show_cacheinfo(m, "icache", boot_cpu_data.icache); 468 show_cacheinfo(m, "icache", c->icache);
468 show_cacheinfo(m, "dcache", boot_cpu_data.dcache); 469 show_cacheinfo(m, "dcache", c->dcache);
469 } 470 }
470 471
471 /* Optional secondary cache */ 472 /* Optional secondary cache */
472 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) 473 if (c->flags & CPU_HAS_L2_CACHE)
473 show_cacheinfo(m, "scache", boot_cpu_data.scache); 474 show_cacheinfo(m, "scache", c->scache);
474 475
475 seq_printf(m, "bogomips\t: %lu.%02lu\n", 476 seq_printf(m, "bogomips\t: %lu.%02lu\n",
476 boot_cpu_data.loops_per_jiffy/(500000/HZ), 477 c->loops_per_jiffy/(500000/HZ),
477 (boot_cpu_data.loops_per_jiffy/(5000/HZ)) % 100); 478 (c->loops_per_jiffy/(5000/HZ)) % 100);
478 479
479 return show_clocks(m); 480 return show_clocks(m);
480} 481}
diff --git a/arch/sh/kernel/signal.c b/arch/sh/kernel/signal.c
index 379c88bf5d9a..32f10a03fbb5 100644
--- a/arch/sh/kernel/signal.c
+++ b/arch/sh/kernel/signal.c
@@ -127,7 +127,7 @@ static inline int restore_sigcontext_fpu(struct sigcontext __user *sc)
127{ 127{
128 struct task_struct *tsk = current; 128 struct task_struct *tsk = current;
129 129
130 if (!(cpu_data->flags & CPU_HAS_FPU)) 130 if (!(current_cpu_data.flags & CPU_HAS_FPU))
131 return 0; 131 return 0;
132 132
133 set_used_math(); 133 set_used_math();
@@ -140,7 +140,7 @@ static inline int save_sigcontext_fpu(struct sigcontext __user *sc,
140{ 140{
141 struct task_struct *tsk = current; 141 struct task_struct *tsk = current;
142 142
143 if (!(cpu_data->flags & CPU_HAS_FPU)) 143 if (!(current_cpu_data.flags & CPU_HAS_FPU))
144 return 0; 144 return 0;
145 145
146 if (!used_math()) { 146 if (!used_math()) {
@@ -181,7 +181,7 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *r0_p
181#undef COPY 181#undef COPY
182 182
183#ifdef CONFIG_SH_FPU 183#ifdef CONFIG_SH_FPU
184 if (cpu_data->flags & CPU_HAS_FPU) { 184 if (current_cpu_data.flags & CPU_HAS_FPU) {
185 int owned_fp; 185 int owned_fp;
186 struct task_struct *tsk = current; 186 struct task_struct *tsk = current;
187 187
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index e91224faf6c4..e9f168f60f95 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -641,7 +641,7 @@ int is_dsp_inst(struct pt_regs *regs)
641 * Safe guard if DSP mode is already enabled or we're lacking 641 * Safe guard if DSP mode is already enabled or we're lacking
642 * the DSP altogether. 642 * the DSP altogether.
643 */ 643 */
644 if (!(cpu_data->flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) 644 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
645 return 0; 645 return 0;
646 646
647 get_user(inst, ((unsigned short *) regs->pc)); 647 get_user(inst, ((unsigned short *) regs->pc));
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 22:51:33 -0500