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-rw-r--r--arch/sh/kernel/cpu/irq/intc2.c165
-rw-r--r--arch/sh/kernel/cpu/irq/ipr.c111
-rw-r--r--arch/sh/kernel/cpu/irq/pint.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/ex.S9
-rw-r--r--arch/sh/kernel/cpu/sh4/ex.S9
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c63
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7780.c27
-rw-r--r--arch/sh/kernel/irq.c2
-rw-r--r--arch/sh/kernel/process.c12
-rw-r--r--arch/sh/kernel/syscalls.S3
-rw-r--r--arch/sh/kernel/traps.c167
-rw-r--r--arch/sh/kernel/vmlinux.lds.S8
12 files changed, 289 insertions, 295 deletions
diff --git a/arch/sh/kernel/cpu/irq/intc2.c b/arch/sh/kernel/cpu/irq/intc2.c
index d4b2bb7e08c7..74ca576a7ce5 100644
--- a/arch/sh/kernel/cpu/irq/intc2.c
+++ b/arch/sh/kernel/cpu/irq/intc2.c
@@ -11,10 +11,9 @@
11 * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780. 11 * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
12 */ 12 */
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/irq.h> 14#include <linux/irq.h>
15#include <linux/io.h>
16#include <asm/system.h> 16#include <asm/system.h>
17#include <asm/io.h>
18 17
19static void disable_intc2_irq(unsigned int irq) 18static void disable_intc2_irq(unsigned int irq)
20{ 19{
@@ -31,7 +30,7 @@ static void enable_intc2_irq(unsigned int irq)
31} 30}
32 31
33static struct irq_chip intc2_irq_chip = { 32static struct irq_chip intc2_irq_chip = {
34 .typename = "intc2", 33 .name = "INTC2",
35 .mask = disable_intc2_irq, 34 .mask = disable_intc2_irq,
36 .unmask = enable_intc2_irq, 35 .unmask = enable_intc2_irq,
37 .mask_ack = disable_intc2_irq, 36 .mask_ack = disable_intc2_irq,
@@ -45,150 +44,36 @@ static struct irq_chip intc2_irq_chip = {
45 * PIO1 which is INTPRI00[19,16] and INTMSK00[13] 44 * PIO1 which is INTPRI00[19,16] and INTMSK00[13]
46 * would be: ^ ^ ^ ^ 45 * would be: ^ ^ ^ ^
47 * | | | | 46 * | | | |
48 * make_intc2_irq(84, 0, 16, 0, 13); 47 * { 84, 0, 16, 0, 13 },
48 *
49 * in the intc2_data table.
49 */ 50 */
50void make_intc2_irq(struct intc2_data *p) 51void make_intc2_irq(struct intc2_data *table, unsigned int nr_irqs)
51{ 52{
52 unsigned int flags; 53 int i;
53 unsigned long ipr;
54
55 disable_irq_nosync(p->irq);
56
57 /* Set the priority level */
58 local_irq_save(flags);
59
60 ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
61 ipr &= ~(0xf << p->ipr_shift);
62 ipr |= p->priority << p->ipr_shift;
63 ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
64
65 local_irq_restore(flags);
66 54
67 set_irq_chip_and_handler(p->irq, &intc2_irq_chip, handle_level_irq); 55 for (i = 0; i < nr_irqs; i++) {
68 set_irq_chip_data(p->irq, p); 56 unsigned long ipr, flags;
57 struct intc2_data *p = table + i;
69 58
70 enable_intc2_irq(p->irq); 59 disable_irq_nosync(p->irq);
71}
72 60
73static struct intc2_data intc2_irq_table[] = { 61 /* Set the priority level */
74#if defined(CONFIG_CPU_SUBTYPE_ST40) 62 local_irq_save(flags);
75 {64, 0, 0, 0, 0, 13}, /* PCI serr */
76 {65, 0, 4, 0, 1, 13}, /* PCI err */
77 {66, 0, 4, 0, 2, 13}, /* PCI ad */
78 {67, 0, 4, 0, 3, 13}, /* PCI pwd down */
79 {72, 0, 8, 0, 5, 13}, /* DMAC INT0 */
80 {73, 0, 8, 0, 6, 13}, /* DMAC INT1 */
81 {74, 0, 8, 0, 7, 13}, /* DMAC INT2 */
82 {75, 0, 8, 0, 8, 13}, /* DMAC INT3 */
83 {76, 0, 8, 0, 9, 13}, /* DMAC INT4 */
84 {78, 0, 8, 0, 11, 13}, /* DMAC ERR */
85 {80, 0, 12, 0, 12, 13}, /* PIO0 */
86 {84, 0, 16, 0, 13, 13}, /* PIO1 */
87 {88, 0, 20, 0, 14, 13}, /* PIO2 */
88 {112, 4, 0, 4, 0, 13}, /* Mailbox */
89 #ifdef CONFIG_CPU_SUBTYPE_ST40GX1
90 {116, 4, 4, 4, 4, 13}, /* SSC0 */
91 {120, 4, 8, 4, 8, 13}, /* IR Blaster */
92 {124, 4, 12, 4, 12, 13}, /* USB host */
93 {128, 4, 16, 4, 16, 13}, /* Video processor BLITTER */
94 {132, 4, 20, 4, 20, 13}, /* UART0 */
95 {134, 4, 20, 4, 22, 13}, /* UART2 */
96 {136, 4, 24, 4, 24, 13}, /* IO_PIO0 */
97 {140, 4, 28, 4, 28, 13}, /* EMPI */
98 {144, 8, 0, 8, 0, 13}, /* MAFE */
99 {148, 8, 4, 8, 4, 13}, /* PWM */
100 {152, 8, 8, 8, 8, 13}, /* SSC1 */
101 {156, 8, 12, 8, 12, 13}, /* IO_PIO1 */
102 {160, 8, 16, 8, 16, 13}, /* USB target */
103 {164, 8, 20, 8, 20, 13}, /* UART1 */
104 {168, 8, 24, 8, 24, 13}, /* Teletext */
105 {172, 8, 28, 8, 28, 13}, /* VideoSync VTG */
106 {173, 8, 28, 8, 29, 13}, /* VideoSync DVP0 */
107 {174, 8, 28, 8, 30, 13}, /* VideoSync DVP1 */
108#endif
109#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
110/*
111 * SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0
112 */
113 /* INTPRIO0 | INTMSK0 */
114 {48, 0, 28, 0, 31, 3}, /* IRQ 4 */
115 {49, 0, 24, 0, 30, 3}, /* IRQ 3 */
116 {50, 0, 20, 0, 29, 3}, /* IRQ 2 */
117 {51, 0, 16, 0, 28, 3}, /* IRQ 1 */
118 /* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */
119 /* INTPRIO4 | INTMSK0 */
120 {56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
121 {57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
122 {58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
123 {59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
124 {60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
125 {61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
126 {62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
127 {63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
128 /* INTPRIO8 | INTMSK0 */
129 {52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
130 {53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
131 {54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
132 {55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
133 {64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
134 {65, 8, 24, 0, 16, 3}, /* LCDC */
135 /* 66, 67 unused */
136 {68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
137 {69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
138 {70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
139 /* 71 unused */
140 {72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
141 {73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
142 {74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
143 {75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
144 {76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
145 {77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
146 {78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
147 {79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
148 /* | INTMSK4 */
149 {80, 8, 4, 4, 23, 3}, /* SIM_ERI */
150 {81, 8, 4, 4, 22, 3}, /* SIM_RXI */
151 {82, 8, 4, 4, 21, 3}, /* SIM_TXI */
152 {83, 8, 4, 4, 20, 3}, /* SIM_TEI */
153 {84, 8, 0, 4, 19, 3}, /* HSPII */
154 /* INTPRIOC | INTMSK4 */
155 /* 85-87 unused/reserved */
156 {88, 12, 20, 4, 18, 3}, /* MMCI0 */
157 {89, 12, 20, 4, 17, 3}, /* MMCI1 */
158 {90, 12, 20, 4, 16, 3}, /* MMCI2 */
159 {91, 12, 20, 4, 15, 3}, /* MMCI3 */
160 {92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/
161 /* 93-107 reserved/undocumented */
162 {108,12, 4, 4, 1, 3}, /* ADC */
163 {109,12, 0, 4, 0, 3}, /* CMTI */
164 /* 110-111 reserved/unused */
165#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
166 { TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2},
167 { 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
168 { 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
169 { 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
170 { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
171 { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
172 { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
173 { SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
174 63
175 { SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, 64 ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET +
176 { SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, 65 p->ipr_offset);
177 { SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, 66 ipr &= ~(0xf << p->ipr_shift);
178 { SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, 67 ipr |= p->priority << p->ipr_shift;
68 ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET +
69 p->ipr_offset);
179 70
180 { PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY }, 71 local_irq_restore(flags);
181 { PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },
182 { PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },
183 { PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },
184 { PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },
185#endif
186};
187 72
188void __init init_IRQ_intc2(void) 73 set_irq_chip_and_handler_name(p->irq, &intc2_irq_chip,
189{ 74 handle_level_irq, "level");
190 int i; 75 set_irq_chip_data(p->irq, p);
191 76
192 for (i = 0; i < ARRAY_SIZE(intc2_irq_table); i++) 77 enable_intc2_irq(p->irq);
193 make_intc2_irq(intc2_irq_table + i); 78 }
194} 79}
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 8944abdf6e1c..a0089563cbfc 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -23,93 +23,81 @@
23#include <asm/io.h> 23#include <asm/io.h>
24#include <asm/machvec.h> 24#include <asm/machvec.h>
25 25
26struct ipr_data {
27 unsigned int addr; /* Address of Interrupt Priority Register */
28 int shift; /* Shifts of the 16-bit data */
29 int priority; /* The priority */
30};
31 26
32static void disable_ipr_irq(unsigned int irq) 27static void disable_ipr_irq(unsigned int irq)
33{ 28{
34 struct ipr_data *p = get_irq_chip_data(irq); 29 struct ipr_data *p = get_irq_chip_data(irq);
30 int shift = p->shift*4;
35 /* Set the priority in IPR to 0 */ 31 /* Set the priority in IPR to 0 */
36 ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr); 32 ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << shift)), p->addr);
37} 33}
38 34
39static void enable_ipr_irq(unsigned int irq) 35static void enable_ipr_irq(unsigned int irq)
40{ 36{
41 struct ipr_data *p = get_irq_chip_data(irq); 37 struct ipr_data *p = get_irq_chip_data(irq);
38 int shift = p->shift*4;
42 /* Set priority in IPR back to original value */ 39 /* Set priority in IPR back to original value */
43 ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr); 40 ctrl_outw(ctrl_inw(p->addr) | (p->priority << shift), p->addr);
44} 41}
45 42
46static struct irq_chip ipr_irq_chip = { 43static struct irq_chip ipr_irq_chip = {
47 .name = "ipr", 44 .name = "IPR",
48 .mask = disable_ipr_irq, 45 .mask = disable_ipr_irq,
49 .unmask = enable_ipr_irq, 46 .unmask = enable_ipr_irq,
50 .mask_ack = disable_ipr_irq, 47 .mask_ack = disable_ipr_irq,
51}; 48};
52 49
53void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority) 50void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs)
54{ 51{
55 struct ipr_data ipr_data; 52 int i;
56 53
57 disable_irq_nosync(irq); 54 for (i = 0; i < nr_irqs; i++) {
58 55 unsigned int irq = table[i].irq;
59 ipr_data.addr = addr; 56 disable_irq_nosync(irq);
60 ipr_data.shift = pos*4; /* POSition (0-3) x 4 means shift */ 57 set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
61 ipr_data.priority = priority; 58 handle_level_irq, "level");
62 59 set_irq_chip_data(irq, &table[i]);
63 set_irq_chip_and_handler(irq, &ipr_irq_chip, handle_level_irq); 60 enable_ipr_irq(irq);
64 set_irq_chip_data(irq, &ipr_data); 61 }
65
66 enable_ipr_irq(irq);
67} 62}
63EXPORT_SYMBOL(make_ipr_irq);
68 64
69/* XXX: This needs to die a horrible death.. */ 65static struct ipr_data sys_ipr_map[] = {
70void __init init_IRQ(void)
71{
72#ifndef CONFIG_CPU_SUBTYPE_SH7780 66#ifndef CONFIG_CPU_SUBTYPE_SH7780
73 make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY); 67 { TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY },
74 make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY); 68 { TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY },
75#ifdef RTC_IRQ 69#ifdef RTC_IRQ
76 make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY); 70 { RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY },
77#endif 71#endif
78
79#ifdef SCI_ERI_IRQ 72#ifdef SCI_ERI_IRQ
80 make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 73 { SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
81 make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 74 { SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
82 make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 75 { SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
83#endif 76#endif
84
85#ifdef SCIF1_ERI_IRQ 77#ifdef SCIF1_ERI_IRQ
86 make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 78 { SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
87 make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 79 { SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
88 make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 80 { SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
89 make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 81 { SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
90#endif 82#endif
91
92#if defined(CONFIG_CPU_SUBTYPE_SH7300) 83#if defined(CONFIG_CPU_SUBTYPE_SH7300)
93 make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY); 84 { SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
94 make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 85 { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
95 make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 86 { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
96 make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); 87 { VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
97#endif 88#endif
98
99#ifdef SCIF_ERI_IRQ 89#ifdef SCIF_ERI_IRQ
100 make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 90 { SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
101 make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 91 { SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
102 make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 92 { SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
103 make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 93 { SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
104#endif 94#endif
105
106#ifdef IRDA_ERI_IRQ 95#ifdef IRDA_ERI_IRQ
107 make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 96 { IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
108 make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 97 { IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
109 make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 98 { IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
110 make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 99 { IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
111#endif 100#endif
112
113#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 101#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
114 defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 102 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
115 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 103 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
@@ -123,14 +111,19 @@ void __init init_IRQ(void)
123 * You should set corresponding bits of PFC to "00" 111 * You should set corresponding bits of PFC to "00"
124 * to enable these interrupts. 112 * to enable these interrupts.
125 */ 113 */
126 make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY); 114 { IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY },
127 make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY); 115 { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY },
128 make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY); 116 { IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY },
129 make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY); 117 { IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY },
130 make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY); 118 { IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY },
131 make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY); 119 { IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY },
132#endif 120#endif
133#endif 121#endif
122};
123
124void __init init_IRQ(void)
125{
126 make_ipr_irq(sys_ipr_map, ARRAY_SIZE(sys_ipr_map));
134 127
135#ifdef CONFIG_CPU_HAS_PINT_IRQ 128#ifdef CONFIG_CPU_HAS_PINT_IRQ
136 init_IRQ_pint(); 129 init_IRQ_pint();
@@ -152,5 +145,3 @@ int ipr_irq_demux(int irq)
152 return irq; 145 return irq;
153} 146}
154#endif 147#endif
155
156EXPORT_SYMBOL(make_ipr_irq);
diff --git a/arch/sh/kernel/cpu/irq/pint.c b/arch/sh/kernel/cpu/irq/pint.c
index 17f47b373d6e..f60007783a21 100644
--- a/arch/sh/kernel/cpu/irq/pint.c
+++ b/arch/sh/kernel/cpu/irq/pint.c
@@ -84,12 +84,16 @@ void make_pint_irq(unsigned int irq)
84 disable_pint_irq(irq); 84 disable_pint_irq(irq);
85} 85}
86 86
87static struct ipr_data pint_ipr_map[] = {
88 { PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY },
89 { PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY },
90};
91
87void __init init_IRQ_pint(void) 92void __init init_IRQ_pint(void)
88{ 93{
89 int i; 94 int i;
90 95
91 make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY); 96 make_ipr_irq(pint_ipr_map, ARRAY_SIZE(pint_ipr_map));
92 make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY);
93 97
94 enable_irq(PINT0_IRQ); 98 enable_irq(PINT0_IRQ);
95 enable_irq(PINT8_IRQ); 99 enable_irq(PINT8_IRQ);
diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S
index 6be46f0686b7..ba3082d640b5 100644
--- a/arch/sh/kernel/cpu/sh3/ex.S
+++ b/arch/sh/kernel/cpu/sh3/ex.S
@@ -4,7 +4,7 @@
4 * The SH-3 exception vector table. 4 * The SH-3 exception vector table.
5 5
6 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka 6 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
7 * Copyright (C) 2003 Paul Mundt 7 * Copyright (C) 2003 - 2006 Paul Mundt
8 * 8 *
9 * This file is subject to the terms and conditions of the GNU General Public 9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive 10 * License. See the file "COPYING" in the main directory of this archive
@@ -49,3 +49,10 @@ ENTRY(nmi_slot)
49#endif 49#endif
50ENTRY(user_break_point_trap) 50ENTRY(user_break_point_trap)
51 .long break_point_trap /* 1E0 */ 51 .long break_point_trap /* 1E0 */
52
53 /*
54 * Pad the remainder of the table out, exceptions residing in far
55 * away offsets can be manually inserted in to their appropriate
56 * location via set_exception_table_{evt,vec}().
57 */
58 .balign 4096,0,4096
diff --git a/arch/sh/kernel/cpu/sh4/ex.S b/arch/sh/kernel/cpu/sh4/ex.S
index 3f4cd043e900..ac8ab57413cc 100644
--- a/arch/sh/kernel/cpu/sh4/ex.S
+++ b/arch/sh/kernel/cpu/sh4/ex.S
@@ -4,7 +4,7 @@
4 * The SH-4 exception vector table. 4 * The SH-4 exception vector table.
5 5
6 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka 6 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
7 * Copyright (C) 2003 Paul Mundt 7 * Copyright (C) 2003 - 2006 Paul Mundt
8 * 8 *
9 * This file is subject to the terms and conditions of the GNU General Public 9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive 10 * License. See the file "COPYING" in the main directory of this archive
@@ -53,3 +53,10 @@ ENTRY(nmi_slot)
53#endif 53#endif
54ENTRY(user_break_point_trap) 54ENTRY(user_break_point_trap)
55 .long break_point_trap /* 1E0 */ 55 .long break_point_trap /* 1E0 */
56
57 /*
58 * Pad the remainder of the table out, exceptions residing in far
59 * away offsets can be manually inserted in to their appropriate
60 * location via set_exception_table_{evt,vec}().
61 */
62 .balign 4096,0,4096
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 97f1c9af35d6..07e5377bf550 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -51,3 +51,66 @@ static int __init sh7760_devices_setup(void)
51 ARRAY_SIZE(sh7760_devices)); 51 ARRAY_SIZE(sh7760_devices));
52} 52}
53__initcall(sh7760_devices_setup); 53__initcall(sh7760_devices_setup);
54
55/*
56 * SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0
57 */
58static struct intc2_data intc2_irq_table[] = {
59 /* INTPRIO0 | INTMSK0 */
60 {48, 0, 28, 0, 31, 3}, /* IRQ 4 */
61 {49, 0, 24, 0, 30, 3}, /* IRQ 3 */
62 {50, 0, 20, 0, 29, 3}, /* IRQ 2 */
63 {51, 0, 16, 0, 28, 3}, /* IRQ 1 */
64 /* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */
65 /* INTPRIO4 | INTMSK0 */
66 {56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
67 {57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
68 {58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
69 {59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
70 {60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
71 {61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
72 {62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
73 {63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
74 /* INTPRIO8 | INTMSK0 */
75 {52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
76 {53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
77 {54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
78 {55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
79 {64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
80 {65, 8, 24, 0, 16, 3}, /* LCDC */
81 /* 66, 67 unused */
82 {68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
83 {69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
84 {70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
85 /* 71 unused */
86 {72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
87 {73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
88 {74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
89 {75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
90 {76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
91 {77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
92 {78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
93 {79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
94 /* | INTMSK4 */
95 {80, 8, 4, 4, 23, 3}, /* SIM_ERI */
96 {81, 8, 4, 4, 22, 3}, /* SIM_RXI */
97 {82, 8, 4, 4, 21, 3}, /* SIM_TXI */
98 {83, 8, 4, 4, 20, 3}, /* SIM_TEI */
99 {84, 8, 0, 4, 19, 3}, /* HSPII */
100 /* INTPRIOC | INTMSK4 */
101 /* 85-87 unused/reserved */
102 {88, 12, 20, 4, 18, 3}, /* MMCI0 */
103 {89, 12, 20, 4, 17, 3}, /* MMCI1 */
104 {90, 12, 20, 4, 16, 3}, /* MMCI2 */
105 {91, 12, 20, 4, 15, 3}, /* MMCI3 */
106 {92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/
107 /* 93-107 reserved/undocumented */
108 {108,12, 4, 4, 1, 3}, /* ADC */
109 {109,12, 0, 4, 0, 3}, /* CMTI */
110 /* 110-111 reserved/unused */
111};
112
113void __init init_IRQ_intc2(void)
114{
115 make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
116}
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7780.c b/arch/sh/kernel/cpu/sh4/setup-sh7780.c
index 72493f259edc..814ddb226531 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7780.c
@@ -77,3 +77,30 @@ static int __init sh7780_devices_setup(void)
77 ARRAY_SIZE(sh7780_devices)); 77 ARRAY_SIZE(sh7780_devices));
78} 78}
79__initcall(sh7780_devices_setup); 79__initcall(sh7780_devices_setup);
80
81static struct intc2_data intc2_irq_table[] = {
82 { TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2 },
83 { 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
84 { 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
85 { 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
86 { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
87 { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
88 { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
89 { SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
90
91 { SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
92 { SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
93 { SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
94 { SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
95
96 { PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY },
97 { PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },
98 { PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },
99 { PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },
100 { PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },
101};
102
103void __init init_IRQ_intc2(void)
104{
105 make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
106}
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index acf2602569c4..944128ce9706 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -54,7 +54,7 @@ int show_interrupts(struct seq_file *p, void *v)
54 for_each_online_cpu(j) 54 for_each_online_cpu(j)
55 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); 55 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
56 seq_printf(p, " %14s", irq_desc[i].chip->name); 56 seq_printf(p, " %14s", irq_desc[i].chip->name);
57 seq_printf(p, "-%s", handle_irq_name(irq_desc[i].handle_irq)); 57 seq_printf(p, "-%-8s", irq_desc[i].name);
58 seq_printf(p, " %s", action->name); 58 seq_printf(p, " %s", action->name);
59 59
60 for (action=action->next; action; action = action->next) 60 for (action=action->next; action; action = action->next)
diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c
index 91516dca4a85..a52b13ac6b7f 100644
--- a/arch/sh/kernel/process.c
+++ b/arch/sh/kernel/process.c
@@ -105,7 +105,7 @@ void show_regs(struct pt_regs * regs)
105{ 105{
106 printk("\n"); 106 printk("\n");
107 printk("Pid : %d, Comm: %20s\n", current->pid, current->comm); 107 printk("Pid : %d, Comm: %20s\n", current->pid, current->comm);
108 print_symbol("PC is at %s\n", regs->pc); 108 print_symbol("PC is at %s\n", instruction_pointer(regs));
109 printk("PC : %08lx SP : %08lx SR : %08lx ", 109 printk("PC : %08lx SP : %08lx SR : %08lx ",
110 regs->pc, regs->regs[15], regs->sr); 110 regs->pc, regs->regs[15], regs->sr);
111#ifdef CONFIG_MMU 111#ifdef CONFIG_MMU
@@ -130,15 +130,7 @@ void show_regs(struct pt_regs * regs)
130 printk("MACH: %08lx MACL: %08lx GBR : %08lx PR : %08lx\n", 130 printk("MACH: %08lx MACL: %08lx GBR : %08lx PR : %08lx\n",
131 regs->mach, regs->macl, regs->gbr, regs->pr); 131 regs->mach, regs->macl, regs->gbr, regs->pr);
132 132
133 /* 133 show_trace(NULL, (unsigned long *)regs->regs[15], regs);
134 * If we're in kernel mode, dump the stack too..
135 */
136 if (!user_mode(regs)) {
137 extern void show_task(unsigned long *sp);
138 unsigned long sp = regs->regs[15];
139
140 show_task((unsigned long *)sp);
141 }
142} 134}
143 135
144/* 136/*
diff --git a/arch/sh/kernel/syscalls.S b/arch/sh/kernel/syscalls.S
index 768334e95075..ca81976e9e34 100644
--- a/arch/sh/kernel/syscalls.S
+++ b/arch/sh/kernel/syscalls.S
@@ -351,3 +351,6 @@ ENTRY(sys_call_table)
351 .long sys_sync_file_range 351 .long sys_sync_file_range
352 .long sys_tee /* 315 */ 352 .long sys_tee /* 315 */
353 .long sys_vmsplice 353 .long sys_vmsplice
354 .long sys_move_pages
355 .long sys_getcpu
356 .long sys_epoll_pwait
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index c2c597e09482..53dfa55f3156 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -1,38 +1,25 @@
1/* $Id: traps.c,v 1.17 2004/05/02 01:46:30 sugioka Exp $ 1/*
2 * 2 * 'traps.c' handles hardware traps and faults after we have saved some
3 * linux/arch/sh/traps.c 3 * state in 'entry.S'.
4 * 4 *
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka 5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf 6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells 7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002, 2003 Paul Mundt 8 * Copyright (C) 2002 - 2006 Paul Mundt
9 */ 9 *
10 10 * This file is subject to the terms and conditions of the GNU General Public
11/* 11 * License. See the file "COPYING" in the main directory of this archive
12 * 'Traps.c' handles hardware traps and faults after we have saved some 12 * for more details.
13 * state in 'entry.S'.
14 */ 13 */
15#include <linux/sched.h>
16#include <linux/kernel.h> 14#include <linux/kernel.h>
17#include <linux/string.h>
18#include <linux/errno.h>
19#include <linux/ptrace.h> 15#include <linux/ptrace.h>
20#include <linux/timer.h>
21#include <linux/mm.h>
22#include <linux/smp.h>
23#include <linux/smp_lock.h>
24#include <linux/init.h> 16#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/spinlock.h> 17#include <linux/spinlock.h>
27#include <linux/module.h> 18#include <linux/module.h>
28#include <linux/kallsyms.h> 19#include <linux/kallsyms.h>
29 20#include <linux/io.h>
30#include <asm/system.h> 21#include <asm/system.h>
31#include <asm/uaccess.h> 22#include <asm/uaccess.h>
32#include <asm/io.h>
33#include <asm/atomic.h>
34#include <asm/processor.h>
35#include <asm/sections.h>
36 23
37#ifdef CONFIG_SH_KGDB 24#ifdef CONFIG_SH_KGDB
38#include <asm/kgdb.h> 25#include <asm/kgdb.h>
@@ -53,13 +40,32 @@
53#define TRAP_ILLEGAL_SLOT_INST 13 40#define TRAP_ILLEGAL_SLOT_INST 13
54#endif 41#endif
55 42
56/* 43static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
57 * These constants are for searching for possible module text 44{
58 * segments. VMALLOC_OFFSET comes from mm/vmalloc.c; MODULE_RANGE is 45 unsigned long p;
59 * a guess of how much space is likely to be vmalloced. 46 int i;
60 */ 47
61#define VMALLOC_OFFSET (8*1024*1024) 48 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
62#define MODULE_RANGE (8*1024*1024) 49
50 for (p = bottom & ~31; p < top; ) {
51 printk("%04lx: ", p & 0xffff);
52
53 for (i = 0; i < 8; i++, p += 4) {
54 unsigned int val;
55
56 if (p < bottom || p >= top)
57 printk(" ");
58 else {
59 if (__get_user(val, (unsigned int __user *)p)) {
60 printk("\n");
61 return;
62 }
63 printk("%08x ", val);
64 }
65 }
66 printk("\n");
67 }
68}
63 69
64DEFINE_SPINLOCK(die_lock); 70DEFINE_SPINLOCK(die_lock);
65 71
@@ -69,14 +75,28 @@ void die(const char * str, struct pt_regs * regs, long err)
69 75
70 console_verbose(); 76 console_verbose();
71 spin_lock_irq(&die_lock); 77 spin_lock_irq(&die_lock);
78 bust_spinlocks(1);
79
72 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); 80 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
81
73 CHK_REMOTE_DEBUG(regs); 82 CHK_REMOTE_DEBUG(regs);
83 print_modules();
74 show_regs(regs); 84 show_regs(regs);
85
86 printk("Process: %s (pid: %d, stack limit = %p)\n",
87 current->comm, current->pid, task_stack_page(current) + 1);
88
89 if (!user_mode(regs) || in_interrupt())
90 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
91 (unsigned long)task_stack_page(current));
92
93 bust_spinlocks(0);
75 spin_unlock_irq(&die_lock); 94 spin_unlock_irq(&die_lock);
76 do_exit(SIGSEGV); 95 do_exit(SIGSEGV);
77} 96}
78 97
79static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err) 98static inline void die_if_kernel(const char *str, struct pt_regs *regs,
99 long err)
80{ 100{
81 if (!user_mode(regs)) 101 if (!user_mode(regs))
82 die(str, regs, err); 102 die(str, regs, err);
@@ -93,8 +113,7 @@ static int handle_unaligned_notify_count = 10;
93 */ 113 */
94static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err) 114static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
95{ 115{
96 if (!user_mode(regs)) 116 if (!user_mode(regs)) {
97 {
98 const struct exception_table_entry *fixup; 117 const struct exception_table_entry *fixup;
99 fixup = search_exception_tables(regs->pc); 118 fixup = search_exception_tables(regs->pc);
100 if (fixup) { 119 if (fixup) {
@@ -550,7 +569,10 @@ int is_dsp_inst(struct pt_regs *regs)
550#define is_dsp_inst(regs) (0) 569#define is_dsp_inst(regs) (0)
551#endif /* CONFIG_SH_DSP */ 570#endif /* CONFIG_SH_DSP */
552 571
553extern int do_fpu_inst(unsigned short, struct pt_regs*); 572/* arch/sh/kernel/cpu/sh4/fpu.c */
573extern int do_fpu_inst(unsigned short, struct pt_regs *);
574extern asmlinkage void do_fpu_state_restore(unsigned long r4, unsigned long r5,
575 unsigned long r6, unsigned long r7, struct pt_regs regs);
554 576
555asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5, 577asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
556 unsigned long r6, unsigned long r7, 578 unsigned long r6, unsigned long r7,
@@ -709,14 +731,20 @@ void __init per_cpu_trap_init(void)
709 : "memory"); 731 : "memory");
710} 732}
711 733
712void __init trap_init(void) 734void *set_exception_table_vec(unsigned int vec, void *handler)
713{ 735{
714 extern void *exception_handling_table[]; 736 extern void *exception_handling_table[];
737 void *old_handler;
738
739 old_handler = exception_handling_table[vec];
740 exception_handling_table[vec] = handler;
741 return old_handler;
742}
715 743
716 exception_handling_table[TRAP_RESERVED_INST] 744void __init trap_init(void)
717 = (void *)do_reserved_inst; 745{
718 exception_handling_table[TRAP_ILLEGAL_SLOT_INST] 746 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
719 = (void *)do_illegal_slot_inst; 747 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
720 748
721#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \ 749#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
722 defined(CONFIG_SH_FPU_EMU) 750 defined(CONFIG_SH_FPU_EMU)
@@ -725,61 +753,54 @@ void __init trap_init(void)
725 * reserved. They'll be handled in the math-emu case, or faulted on 753 * reserved. They'll be handled in the math-emu case, or faulted on
726 * otherwise. 754 * otherwise.
727 */ 755 */
728 /* entry 64 corresponds to EXPEVT=0x800 */ 756 set_exception_table_evt(0x800, do_reserved_inst);
729 exception_handling_table[64] = (void *)do_reserved_inst; 757 set_exception_table_evt(0x820, do_illegal_slot_inst);
730 exception_handling_table[65] = (void *)do_illegal_slot_inst; 758#elif defined(CONFIG_SH_FPU)
759 set_exception_table_evt(0x800, do_fpu_state_restore);
760 set_exception_table_evt(0x820, do_fpu_state_restore);
731#endif 761#endif
732 762
733 /* Setup VBR for boot cpu */ 763 /* Setup VBR for boot cpu */
734 per_cpu_trap_init(); 764 per_cpu_trap_init();
735} 765}
736 766
737void show_stack(struct task_struct *tsk, unsigned long *sp) 767void show_trace(struct task_struct *tsk, unsigned long *sp,
768 struct pt_regs *regs)
738{ 769{
739 unsigned long *stack, addr; 770 unsigned long addr;
740 unsigned long module_start = VMALLOC_START;
741 unsigned long module_end = VMALLOC_END;
742 int i = 1;
743
744 if (!tsk)
745 tsk = current;
746 if (tsk == current)
747 sp = (unsigned long *)current_stack_pointer;
748 else
749 sp = (unsigned long *)tsk->thread.sp;
750 771
751 stack = sp; 772 if (regs && user_mode(regs))
773 return;
752 774
753 printk("\nCall trace: "); 775 printk("\nCall trace: ");
754#ifdef CONFIG_KALLSYMS 776#ifdef CONFIG_KALLSYMS
755 printk("\n"); 777 printk("\n");
756#endif 778#endif
757 779
758 while (!kstack_end(stack)) { 780 while (!kstack_end(sp)) {
759 addr = *stack++; 781 addr = *sp++;
760 if (((addr >= (unsigned long)_text) && 782 if (kernel_text_address(addr))
761 (addr <= (unsigned long)_etext)) || 783 print_ip_sym(addr);
762 ((addr >= module_start) && (addr <= module_end))) {
763 /*
764 * For 80-columns display, 6 entry is maximum.
765 * NOTE: '[<8c00abcd>] ' consumes 13 columns .
766 */
767#ifndef CONFIG_KALLSYMS
768 if (i && ((i % 6) == 0))
769 printk("\n ");
770#endif
771 printk("[<%08lx>] ", addr);
772 print_symbol("%s\n", addr);
773 i++;
774 }
775 } 784 }
776 785
777 printk("\n"); 786 printk("\n");
778} 787}
779 788
780void show_task(unsigned long *sp) 789void show_stack(struct task_struct *tsk, unsigned long *sp)
781{ 790{
782 show_stack(NULL, sp); 791 unsigned long stack;
792
793 if (!tsk)
794 tsk = current;
795 if (tsk == current)
796 sp = (unsigned long *)current_stack_pointer;
797 else
798 sp = (unsigned long *)tsk->thread.sp;
799
800 stack = (unsigned long)sp;
801 dump_mem("Stack: ", stack, THREAD_SIZE +
802 (unsigned long)task_stack_page(tsk));
803 show_trace(tsk, sp, NULL);
783} 804}
784 805
785void dump_stack(void) 806void dump_stack(void)
diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S
index 5eb930918186..77b4026d5688 100644
--- a/arch/sh/kernel/vmlinux.lds.S
+++ b/arch/sh/kernel/vmlinux.lds.S
@@ -76,13 +76,7 @@ SECTIONS
76 __setup_end = .; 76 __setup_end = .;
77 __initcall_start = .; 77 __initcall_start = .;
78 .initcall.init : { 78 .initcall.init : {
79 *(.initcall1.init) 79 INITCALLS
80 *(.initcall2.init)
81 *(.initcall3.init)
82 *(.initcall4.init)
83 *(.initcall5.init)
84 *(.initcall6.init)
85 *(.initcall7.init)
86 } 80 }
87 __initcall_end = .; 81 __initcall_end = .;
88 __con_initcall_start = .; 82 __con_initcall_start = .;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 15:13:15 -0500