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-rw-r--r--arch/sh/kernel/traps.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index 1edec2709efe..f558748d7543 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -107,8 +107,6 @@ static inline void die_if_kernel(const char *str, struct pt_regs *regs,
107 die(str, regs, err); 107 die(str, regs, err);
108} 108}
109 109
110static int handle_unaligned_notify_count = 10;
111
112/* 110/*
113 * try and fix up kernelspace address errors 111 * try and fix up kernelspace address errors
114 * - userspace errors just cause EFAULT to be returned, resulting in SEGV 112 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
@@ -347,6 +345,13 @@ static inline int handle_unaligned_delayslot(struct pt_regs *regs)
347#define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) 345#define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
348#define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) 346#define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
349 347
348/*
349 * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
350 * opcodes..
351 */
352#ifndef CONFIG_CPU_SH2A
353static int handle_unaligned_notify_count = 10;
354
350static int handle_unaligned_access(u16 instruction, struct pt_regs *regs) 355static int handle_unaligned_access(u16 instruction, struct pt_regs *regs)
351{ 356{
352 u_int rm; 357 u_int rm;
@@ -483,6 +488,7 @@ static int handle_unaligned_access(u16 instruction, struct pt_regs *regs)
483 regs->pc += 2; 488 regs->pc += 2;
484 return ret; 489 return ret;
485} 490}
491#endif /* CONFIG_CPU_SH2A */
486 492
487#ifdef CONFIG_CPU_HAS_SR_RB 493#ifdef CONFIG_CPU_HAS_SR_RB
488#define lookup_exception_vector(x) \ 494#define lookup_exception_vector(x) \
@@ -501,8 +507,10 @@ asmlinkage void do_address_error(struct pt_regs *regs,
501{ 507{
502 unsigned long error_code = 0; 508 unsigned long error_code = 0;
503 mm_segment_t oldfs; 509 mm_segment_t oldfs;
510#ifndef CONFIG_CPU_SH2A
504 u16 instruction; 511 u16 instruction;
505 int tmp; 512 int tmp;
513#endif
506 514
507 /* Intentional ifdef */ 515 /* Intentional ifdef */
508#ifdef CONFIG_CPU_HAS_SR_RB 516#ifdef CONFIG_CPU_HAS_SR_RB