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-rw-r--r--arch/sh/kernel/timers/Makefile2
-rw-r--r--arch/sh/kernel/timers/timer-cmt.c196
-rw-r--r--arch/sh/kernel/timers/timer-mtu2.c200
-rw-r--r--arch/sh/kernel/timers/timer-tmu.c13
-rw-r--r--arch/sh/kernel/timers/timer.c6
5 files changed, 407 insertions, 10 deletions
diff --git a/arch/sh/kernel/timers/Makefile b/arch/sh/kernel/timers/Makefile
index 151a6a304cec..bcf244ff6a12 100644
--- a/arch/sh/kernel/timers/Makefile
+++ b/arch/sh/kernel/timers/Makefile
@@ -5,4 +5,6 @@
5obj-y := timer.o 5obj-y := timer.o
6 6
7obj-$(CONFIG_SH_TMU) += timer-tmu.o 7obj-$(CONFIG_SH_TMU) += timer-tmu.o
8obj-$(CONFIG_SH_MTU2) += timer-mtu2.o
9obj-$(CONFIG_SH_CMT) += timer-cmt.o
8 10
diff --git a/arch/sh/kernel/timers/timer-cmt.c b/arch/sh/kernel/timers/timer-cmt.c
new file mode 100644
index 000000000000..a574b93a4e7b
--- /dev/null
+++ b/arch/sh/kernel/timers/timer-cmt.c
@@ -0,0 +1,196 @@
1/*
2 * arch/sh/kernel/timers/timer-cmt.c - CMT Timer Support
3 *
4 * Copyright (C) 2005 Yoshinori Sato
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/seqlock.h>
15#include <asm/timer.h>
16#include <asm/rtc.h>
17#include <asm/io.h>
18#include <asm/irq.h>
19#include <asm/clock.h>
20
21#if defined(CONFIG_CPU_SUBTYPE_SH7619)
22#define CMT_CMSTR 0xf84a0070
23#define CMT_CMCSR_0 0xf84a0072
24#define CMT_CMCNT_0 0xf84a0074
25#define CMT_CMCOR_0 0xf84a0076
26#define CMT_CMCSR_1 0xf84a0078
27#define CMT_CMCNT_1 0xf84a007a
28#define CMT_CMCOR_1 0xf84a007c
29
30#define STBCR3 0xf80a0000
31#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0)
32#define CMT_CMCSR_INIT 0x0040
33#define CMT_CMCSR_CALIB 0x0000
34#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
35#define CMT_CMSTR 0xfffec000
36#define CMT_CMCSR_0 0xfffec002
37#define CMT_CMCNT_0 0xfffec004
38#define CMT_CMCOR_0 0xfffec006
39
40#define STBCR4 0xfffe040c
41#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR4) & ~0x04, STBCR4); } while(0)
42#define CMT_CMCSR_INIT 0x0040
43#define CMT_CMCSR_CALIB 0x0000
44#else
45#error "Unknown CPU SUBTYPE"
46#endif
47
48static unsigned long cmt_timer_get_offset(void)
49{
50 int count;
51 static unsigned short count_p = 0xffff; /* for the first call after boot */
52 static unsigned long jiffies_p = 0;
53
54 /*
55 * cache volatile jiffies temporarily; we have IRQs turned off.
56 */
57 unsigned long jiffies_t;
58
59 /* timer count may underflow right here */
60 count = ctrl_inw(CMT_CMCOR_0);
61 count -= ctrl_inw(CMT_CMCNT_0);
62
63 jiffies_t = jiffies;
64
65 /*
66 * avoiding timer inconsistencies (they are rare, but they happen)...
67 * there is one kind of problem that must be avoided here:
68 * 1. the timer counter underflows
69 */
70
71 if (jiffies_t == jiffies_p) {
72 if (count > count_p) {
73 /* the nutcase */
74 if (ctrl_inw(CMT_CMCSR_0) & 0x80) { /* Check CMF bit */
75 count -= LATCH;
76 } else {
77 printk("%s (): hardware timer problem?\n",
78 __FUNCTION__);
79 }
80 }
81 } else
82 jiffies_p = jiffies_t;
83
84 count_p = count;
85
86 count = ((LATCH-1) - count) * TICK_SIZE;
87 count = (count + LATCH/2) / LATCH;
88
89 return count;
90}
91
92static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id)
93{
94 unsigned long timer_status;
95
96 /* Clear CMF bit */
97 timer_status = ctrl_inw(CMT_CMCSR_0);
98 timer_status &= ~0x80;
99 ctrl_outw(timer_status, CMT_CMCSR_0);
100
101 /*
102 * Here we are in the timer irq handler. We just have irqs locally
103 * disabled but we don't know if the timer_bh is running on the other
104 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
105 * the irq version of write_lock because as just said we have irq
106 * locally disabled. -arca
107 */
108 write_seqlock(&xtime_lock);
109 handle_timer_tick();
110 write_sequnlock(&xtime_lock);
111
112 return IRQ_HANDLED;
113}
114
115static struct irqaction cmt_irq = {
116 .name = "timer",
117 .handler = cmt_timer_interrupt,
118 .flags = IRQF_DISABLED | IRQF_TIMER,
119 .mask = CPU_MASK_NONE,
120};
121
122static void cmt_clk_init(struct clk *clk)
123{
124 u8 divisor = CMT_CMCSR_INIT & 0x3;
125 ctrl_inw(CMT_CMCSR_0);
126 ctrl_outw(CMT_CMCSR_INIT, CMT_CMCSR_0);
127 clk->parent = clk_get(NULL, "module_clk");
128 clk->rate = clk->parent->rate / (8 << (divisor << 1));
129}
130
131static void cmt_clk_recalc(struct clk *clk)
132{
133 u8 divisor = ctrl_inw(CMT_CMCSR_0) & 0x3;
134 clk->rate = clk->parent->rate / (8 << (divisor << 1));
135}
136
137static struct clk_ops cmt_clk_ops = {
138 .init = cmt_clk_init,
139 .recalc = cmt_clk_recalc,
140};
141
142static struct clk cmt0_clk = {
143 .name = "cmt0_clk",
144 .ops = &cmt_clk_ops,
145};
146
147static int cmt_timer_start(void)
148{
149 ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR);
150 return 0;
151}
152
153static int cmt_timer_stop(void)
154{
155 ctrl_outw(ctrl_inw(CMT_CMSTR) & ~0x01, CMT_CMSTR);
156 return 0;
157}
158
159static int cmt_timer_init(void)
160{
161 unsigned long interval;
162
163 cmt_clock_enable();
164
165 setup_irq(CONFIG_SH_TIMER_IRQ, &cmt_irq);
166
167 cmt0_clk.parent = clk_get(NULL, "module_clk");
168
169 cmt_timer_stop();
170
171 interval = cmt0_clk.parent->rate / 8 / HZ;
172 printk(KERN_INFO "Interval = %ld\n", interval);
173
174 ctrl_outw(interval, CMT_CMCOR_0);
175
176 clk_register(&cmt0_clk);
177 clk_enable(&cmt0_clk);
178
179 cmt_timer_start();
180
181 return 0;
182}
183
184struct sys_timer_ops cmt_timer_ops = {
185 .init = cmt_timer_init,
186 .start = cmt_timer_start,
187 .stop = cmt_timer_stop,
188#ifndef CONFIG_GENERIC_TIME
189 .get_offset = cmt_timer_get_offset,
190#endif
191};
192
193struct sys_timer cmt_timer = {
194 .name = "cmt",
195 .ops = &cmt_timer_ops,
196};
diff --git a/arch/sh/kernel/timers/timer-mtu2.c b/arch/sh/kernel/timers/timer-mtu2.c
new file mode 100644
index 000000000000..fffcd1c09873
--- /dev/null
+++ b/arch/sh/kernel/timers/timer-mtu2.c
@@ -0,0 +1,200 @@
1/*
2 * arch/sh/kernel/timers/timer-mtu2.c - MTU2 Timer Support
3 *
4 * Copyright (C) 2005 Paul Mundt
5 *
6 * Based off of arch/sh/kernel/timers/timer-tmu.c
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/seqlock.h>
16#include <asm/timer.h>
17#include <asm/io.h>
18#include <asm/irq.h>
19#include <asm/clock.h>
20
21/*
22 * We use channel 1 for our lowly system timer. Channel 2 would be the other
23 * likely candidate, but we leave it alone as it has higher divisors that
24 * would be of more use to other more interesting applications.
25 *
26 * TODO: Presently we only implement a 16-bit single-channel system timer.
27 * However, we can implement channel cascade if we go the overflow route and
28 * get away with using 2 MTU2 channels as a 32-bit timer.
29 */
30#define MTU2_TSTR 0xfffe4280
31#define MTU2_TCR_1 0xfffe4380
32#define MTU2_TMDR_1 0xfffe4381
33#define MTU2_TIOR_1 0xfffe4382
34#define MTU2_TIER_1 0xfffe4384
35#define MTU2_TSR_1 0xfffe4385
36#define MTU2_TCNT_1 0xfffe4386 /* 16-bit counter */
37#define MTU2_TGRA_1 0xfffe438a
38
39#define STBCR3 0xfffe0408
40
41#define MTU2_TSTR_CST1 (1 << 1) /* Counter Start 1 */
42
43#define MTU2_TSR_TGFA (1 << 0) /* GRA compare match */
44
45#define MTU2_TIER_TGIEA (1 << 0) /* GRA compare match interrupt enable */
46
47#define MTU2_TCR_INIT 0x22
48
49#define MTU2_TCR_CALIB 0x00
50
51static unsigned long mtu2_timer_get_offset(void)
52{
53 int count;
54 static int count_p = 0x7fff; /* for the first call after boot */
55 static unsigned long jiffies_p = 0;
56
57 /*
58 * cache volatile jiffies temporarily; we have IRQs turned off.
59 */
60 unsigned long jiffies_t;
61
62 /* timer count may underflow right here */
63 count = ctrl_inw(MTU2_TCNT_1); /* read the latched count */
64
65 jiffies_t = jiffies;
66
67 /*
68 * avoiding timer inconsistencies (they are rare, but they happen)...
69 * there is one kind of problem that must be avoided here:
70 * 1. the timer counter underflows
71 */
72
73 if (jiffies_t == jiffies_p) {
74 if (count > count_p) {
75 if (ctrl_inb(MTU2_TSR_1) & MTU2_TSR_TGFA) {
76 count -= LATCH;
77 } else {
78 printk("%s (): hardware timer problem?\n",
79 __FUNCTION__);
80 }
81 }
82 } else
83 jiffies_p = jiffies_t;
84
85 count_p = count;
86
87 count = ((LATCH-1) - count) * TICK_SIZE;
88 count = (count + LATCH/2) / LATCH;
89
90 return count;
91}
92
93static irqreturn_t mtu2_timer_interrupt(int irq, void *dev_id)
94{
95 unsigned long timer_status;
96
97 /* Clear TGFA bit */
98 timer_status = ctrl_inb(MTU2_TSR_1);
99 timer_status &= ~MTU2_TSR_TGFA;
100 ctrl_outb(timer_status, MTU2_TSR_1);
101
102 /* Do timer tick */
103 write_seqlock(&xtime_lock);
104 handle_timer_tick();
105 write_sequnlock(&xtime_lock);
106
107 return IRQ_HANDLED;
108}
109
110static struct irqaction mtu2_irq = {
111 .name = "timer",
112 .handler = mtu2_timer_interrupt,
113 .flags = IRQF_DISABLED | IRQF_TIMER,
114 .mask = CPU_MASK_NONE,
115};
116
117static unsigned int divisors[] = { 1, 4, 16, 64, 1, 1, 256 };
118
119static void mtu2_clk_init(struct clk *clk)
120{
121 u8 idx = MTU2_TCR_INIT & 0x7;
122
123 clk->rate = clk->parent->rate / divisors[idx];
124 /* Start TCNT counting */
125 ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
126
127}
128
129static void mtu2_clk_recalc(struct clk *clk)
130{
131 u8 idx = ctrl_inb(MTU2_TCR_1) & 0x7;
132 clk->rate = clk->parent->rate / divisors[idx];
133}
134
135static struct clk_ops mtu2_clk_ops = {
136 .init = mtu2_clk_init,
137 .recalc = mtu2_clk_recalc,
138};
139
140static struct clk mtu2_clk1 = {
141 .name = "mtu2_clk1",
142 .ops = &mtu2_clk_ops,
143};
144
145static int mtu2_timer_start(void)
146{
147 ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
148 return 0;
149}
150
151static int mtu2_timer_stop(void)
152{
153 ctrl_outb(ctrl_inb(MTU2_TSTR) & ~MTU2_TSTR_CST1, MTU2_TSTR);
154 return 0;
155}
156
157static int mtu2_timer_init(void)
158{
159 u8 tmp;
160 unsigned long interval;
161
162 setup_irq(CONFIG_SH_TIMER_IRQ, &mtu2_irq);
163
164 mtu2_clk1.parent = clk_get(NULL, "module_clk");
165
166 ctrl_outb(ctrl_inb(STBCR3) & (~0x20), STBCR3);
167
168 /* Normal operation */
169 ctrl_outb(0, MTU2_TMDR_1);
170 ctrl_outb(MTU2_TCR_INIT, MTU2_TCR_1);
171 ctrl_outb(0x01, MTU2_TIOR_1);
172
173 /* Enable underflow interrupt */
174 ctrl_outb(ctrl_inb(MTU2_TIER_1) | MTU2_TIER_TGIEA, MTU2_TIER_1);
175
176 interval = CONFIG_SH_PCLK_FREQ / 16 / HZ;
177 printk(KERN_INFO "Interval = %ld\n", interval);
178
179 ctrl_outw(interval, MTU2_TGRA_1);
180 ctrl_outw(0, MTU2_TCNT_1);
181
182 clk_register(&mtu2_clk1);
183 clk_enable(&mtu2_clk1);
184
185 return 0;
186}
187
188struct sys_timer_ops mtu2_timer_ops = {
189 .init = mtu2_timer_init,
190 .start = mtu2_timer_start,
191 .stop = mtu2_timer_stop,
192#ifndef CONFIG_GENERIC_TIME
193 .get_offset = mtu2_timer_get_offset,
194#endif
195};
196
197struct sys_timer mtu2_timer = {
198 .name = "mtu2",
199 .ops = &mtu2_timer_ops,
200};
diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c
index 24927015dc31..e060e71d0785 100644
--- a/arch/sh/kernel/timers/timer-tmu.c
+++ b/arch/sh/kernel/timers/timer-tmu.c
@@ -17,7 +17,6 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/spinlock.h>
21#include <linux/seqlock.h> 20#include <linux/seqlock.h>
22#include <asm/timer.h> 21#include <asm/timer.h>
23#include <asm/rtc.h> 22#include <asm/rtc.h>
@@ -31,13 +30,9 @@
31 30
32#define TMU0_TCR_CALIB 0x0000 31#define TMU0_TCR_CALIB 0x0000
33 32
34static DEFINE_SPINLOCK(tmu0_lock);
35
36static unsigned long tmu_timer_get_offset(void) 33static unsigned long tmu_timer_get_offset(void)
37{ 34{
38 int count; 35 int count;
39 unsigned long flags;
40
41 static int count_p = 0x7fffffff; /* for the first call after boot */ 36 static int count_p = 0x7fffffff; /* for the first call after boot */
42 static unsigned long jiffies_p = 0; 37 static unsigned long jiffies_p = 0;
43 38
@@ -46,7 +41,6 @@ static unsigned long tmu_timer_get_offset(void)
46 */ 41 */
47 unsigned long jiffies_t; 42 unsigned long jiffies_t;
48 43
49 spin_lock_irqsave(&tmu0_lock, flags);
50 /* timer count may underflow right here */ 44 /* timer count may underflow right here */
51 count = ctrl_inl(TMU0_TCNT); /* read the latched count */ 45 count = ctrl_inl(TMU0_TCNT); /* read the latched count */
52 46
@@ -72,7 +66,6 @@ static unsigned long tmu_timer_get_offset(void)
72 jiffies_p = jiffies_t; 66 jiffies_p = jiffies_t;
73 67
74 count_p = count; 68 count_p = count;
75 spin_unlock_irqrestore(&tmu0_lock, flags);
76 69
77 count = ((LATCH-1) - count) * TICK_SIZE; 70 count = ((LATCH-1) - count) * TICK_SIZE;
78 count = (count + LATCH/2) / LATCH; 71 count = (count + LATCH/2) / LATCH;
@@ -106,7 +99,7 @@ static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
106static struct irqaction tmu_irq = { 99static struct irqaction tmu_irq = {
107 .name = "timer", 100 .name = "timer",
108 .handler = tmu_timer_interrupt, 101 .handler = tmu_timer_interrupt,
109 .flags = IRQF_DISABLED, 102 .flags = IRQF_DISABLED | IRQF_TIMER,
110 .mask = CPU_MASK_NONE, 103 .mask = CPU_MASK_NONE,
111}; 104};
112 105
@@ -149,9 +142,9 @@ static int tmu_timer_init(void)
149{ 142{
150 unsigned long interval; 143 unsigned long interval;
151 144
152 setup_irq(TIMER_IRQ, &tmu_irq); 145 setup_irq(CONFIG_SH_TIMER_IRQ, &tmu_irq);
153 146
154 tmu0_clk.parent = clk_get("module_clk"); 147 tmu0_clk.parent = clk_get(NULL, "module_clk");
155 148
156 /* Start TMU0 */ 149 /* Start TMU0 */
157 tmu_timer_stop(); 150 tmu_timer_stop();
diff --git a/arch/sh/kernel/timers/timer.c b/arch/sh/kernel/timers/timer.c
index dc1f631053a8..a6bcc913d25e 100644
--- a/arch/sh/kernel/timers/timer.c
+++ b/arch/sh/kernel/timers/timer.c
@@ -17,6 +17,12 @@ static struct sys_timer *sys_timers[] __initdata = {
17#ifdef CONFIG_SH_TMU 17#ifdef CONFIG_SH_TMU
18 &tmu_timer, 18 &tmu_timer,
19#endif 19#endif
20#ifdef CONFIG_SH_MTU2
21 &mtu2_timer,
22#endif
23#ifdef CONFIG_SH_CMT
24 &cmt_timer,
25#endif
20 NULL, 26 NULL,
21}; 27};
22 28
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 08:01:19 -0500