diff options
Diffstat (limited to 'arch/sh/kernel/timers/timer-tmu.c')
-rw-r--r-- | arch/sh/kernel/timers/timer-tmu.c | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c index 0db3f9510336..10b5a6f17cc0 100644 --- a/arch/sh/kernel/timers/timer-tmu.c +++ b/arch/sh/kernel/timers/timer-tmu.c | |||
@@ -146,7 +146,14 @@ static irqreturn_t tmu_timer_interrupt(int irq, void *dummy) | |||
146 | _tmu_clear_status(TMU0); | 146 | _tmu_clear_status(TMU0); |
147 | _tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT); | 147 | _tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT); |
148 | 148 | ||
149 | evt->event_handler(evt); | 149 | switch (tmu0_clockevent.mode) { |
150 | case CLOCK_EVT_MODE_ONESHOT: | ||
151 | case CLOCK_EVT_MODE_PERIODIC: | ||
152 | evt->event_handler(evt); | ||
153 | break; | ||
154 | default: | ||
155 | break; | ||
156 | } | ||
150 | 157 | ||
151 | return IRQ_HANDLED; | 158 | return IRQ_HANDLED; |
152 | } | 159 | } |
@@ -237,6 +244,7 @@ static int tmu_timer_init(void) | |||
237 | !defined(CONFIG_CPU_SUBTYPE_SH7721) && \ | 244 | !defined(CONFIG_CPU_SUBTYPE_SH7721) && \ |
238 | !defined(CONFIG_CPU_SUBTYPE_SH7760) && \ | 245 | !defined(CONFIG_CPU_SUBTYPE_SH7760) && \ |
239 | !defined(CONFIG_CPU_SUBTYPE_SH7785) && \ | 246 | !defined(CONFIG_CPU_SUBTYPE_SH7785) && \ |
247 | !defined(CONFIG_CPU_SUBTYPE_SH7786) && \ | ||
240 | !defined(CONFIG_CPU_SUBTYPE_SHX3) | 248 | !defined(CONFIG_CPU_SUBTYPE_SHX3) |
241 | ctrl_outb(TMU_TOCR_INIT, TMU_TOCR); | 249 | ctrl_outb(TMU_TOCR_INIT, TMU_TOCR); |
242 | #endif | 250 | #endif |
@@ -254,7 +262,14 @@ static int tmu_timer_init(void) | |||
254 | 262 | ||
255 | _tmu_start(TMU1); | 263 | _tmu_start(TMU1); |
256 | 264 | ||
257 | sh_hpt_frequency = clk_get_rate(&tmu1_clk); | 265 | clocksource_sh.rating = 200; |
266 | clocksource_sh.mask = CLOCKSOURCE_MASK(32); | ||
267 | clocksource_sh.read = tmu_timer_read; | ||
268 | clocksource_sh.shift = 10; | ||
269 | clocksource_sh.mult = clocksource_hz2mult(clk_get_rate(&tmu1_clk), | ||
270 | clocksource_sh.shift); | ||
271 | clocksource_sh.flags = CLOCK_SOURCE_IS_CONTINUOUS; | ||
272 | clocksource_register(&clocksource_sh); | ||
258 | 273 | ||
259 | tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC, | 274 | tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC, |
260 | tmu0_clockevent.shift); | 275 | tmu0_clockevent.shift); |
@@ -264,6 +279,7 @@ static int tmu_timer_init(void) | |||
264 | clockevent_delta2ns(1, &tmu0_clockevent); | 279 | clockevent_delta2ns(1, &tmu0_clockevent); |
265 | 280 | ||
266 | tmu0_clockevent.cpumask = cpumask_of(0); | 281 | tmu0_clockevent.cpumask = cpumask_of(0); |
282 | tmu0_clockevent.rating = 100; | ||
267 | 283 | ||
268 | clockevents_register_device(&tmu0_clockevent); | 284 | clockevents_register_device(&tmu0_clockevent); |
269 | 285 | ||
@@ -274,7 +290,6 @@ static struct sys_timer_ops tmu_timer_ops = { | |||
274 | .init = tmu_timer_init, | 290 | .init = tmu_timer_init, |
275 | .start = tmu_timer_start, | 291 | .start = tmu_timer_start, |
276 | .stop = tmu_timer_stop, | 292 | .stop = tmu_timer_stop, |
277 | .read = tmu_timer_read, | ||
278 | }; | 293 | }; |
279 | 294 | ||
280 | struct sys_timer tmu_timer = { | 295 | struct sys_timer tmu_timer = { |